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Xilinx rolls out ISE Design Suite 11 for targeted design platforms!

April 27, 2009

Xilinx has now started shipping its ISE Design Suite 11.1!Source: Xilinx

This is said to be the industry’s first FPGA design solution with fully interoperable domain-specific design flows and user-specific configurations for logic, digital signal processing (DSP), embedded processing, and system-level design.

The ISE Design Suite 11.1 release is a major milestone in the delivery of targeted design platforms with simpler, smarter design methodologies for creating FPGA-based system-on-chip solutions targeting a wide variety of markets and applications.

Tom Feist, Senior Marketing Director, Xilinx Inc., said that the company has been driving the evolution of FPGA design with domain-specific development environment for targeted design platforms. The new ISE Design Suite 11.1 sets the industry standard for delivering FPGA design tools and intellectual property (IP) to embedded, DSP and logic designers.

“This is a series of announcements that Xilinx is working on. We are releasing the IC Design Suite 11, for now,” he added. “Target design platform is a focus for Xilinx right now. We are working with Vita Consortium — Vita 57.” This is the FPGA I/O Mezzanine Card (FMC) standard, which aims to bring modularity to FPGA designs.

Meeting diverse requirements of FPGA design teams
Tailored for domain-specific methodologies, Xilinx’s ISE Design Suite 11 has four configurations aligned to user-specific methodologies — logic (VHDL/Verilog), embedded, DSP, or system design. It has the FLEXnet license management to better meet the design teams’ needs.

It also delivers methodologies specific to each designer’s needs. Each configuration delivers domain specific tools and IP, and accelerates designer productivity. The Suite narrows the focus to design differentiation, and not the design flow. Besides, it leverages the robust ecosystem of third party partners.

“The goal is to build a strong foundation with the targeted deisgn platform. Each edition of the Design Suite includes all of the tools/IPs needed to create, validate and implement,” Feist added.

“We are introducing four different versions — one for the logic designers; one for the embedded designers, one for the DSP desgners; and for system integrators,” he said.

“The overall strategy is to increase designers’ productivity. To drive this to the next level, we look at the development phase of our customers. FPGA design teams face different requirements. We need to provide methodologies that are working for each one of the individuals,” Feist added. The goal being — for each new tool, provide the IP and help validate the design.

More turns/day for designers
Overall, there are improvements for all designers, leading to more turns per day. There are improvements in the place-and-route algorithms. It delivers an average of 2X faster runtimes. The second generation SmartGuide provides an additional 2X improvement. The Design Suite also supports multi-threaded place and route.

Other improvements include: XST delivers an average of 2X faster synthesis runtime; improved support for SecureIP provides faster simulation PowerPC, MGT, and PCI hard IP blocks — supports Mentor, Cadence and Synopsys simulators; 10 percent better dynamic power via place and route optimizations; and reduction of memory requirements by an average 28 of percent.

Feist clarified: “The 2X improvement in implementation is compared to 10.1, our previous release. The 2X improvement related to SmarGuide is relative to a full re-implementation. Also, the 10 percent better dynamic power via place-and-route optimizations is against the previous release.”

The Xilinx ISE Design Suite has been positioned as a key enabler for targeted design platforms. It delivers optimized tool flows for each member of the design team. Thereby, it aims to boosts user productivity, improve quality of results, accelerate time to production, and enable designers to focus on differentiation.

Who would be the main users — power or mainstream? Feist said: “This will be useful for power users as well. Even the pushbutton users will still need to do pin layout. We have tried to make this very intuitive. You can look at the different levels.”

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