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Delivering 10X design improvements: Dr. Walden C. Rhines, Mentor Graphics @ VLSID 2010

Friends, here is an overview of the remarks made by Dr. Walden C. Rhines, chairman and CEO, Mentor Graphics, during his technical keynote titled: Delivering 10X design improvements, at the ongoing VLSID 2010 in Bangalore, India.
Dr. Walden C. Rhines, CEO, Mentor Graphics, during his keynote at VLSID 2010, Bangalore, India.

Dr. Walden C. Rhines, CEO, Mentor Graphics, during his keynote at VLSID 2010.

Today, the exponential rise in complexity has quickened its pace as the industry moves toward adoption of 28 nm and below. Dr. Rhines discussed how over the next five years, 10X improvements in design methodologies are required in four areas: high-level system design, verification, embedded software development, and back-end physical design and test. According to Dr. Rhines:

* Reduced cost per function will continue on a predictable learning curve – long after Moore’s Law is obsolete.
~ 40 billion transistor (5-10 billion gate) ASIC designs in 2018.

* EDA tools for 40 billion transistor designs are available today:
— Design abstraction.
— Advanced verification methodology changes.
— Merging of physical verification with new router architectures.
— Parallelization.

* Embedded software automation (ESA) will automate software development and verification
— Just as EDA did for hardware design.

So, why has Moore’s Law been a useful approximation for 40 years? It is based upon a basic ‘Law’ of nature – the learning curve. Moore’s Law is a special case of the learning curve when two things are true:

1. Cumulative transistors produced increase exponentially with time (e.g. 2x cum volume => fixed percentage cost decrease).
2. Almost all cost reduction has come from shrinking feature sizes (and growing wafer diameter).

Learning curves
* Cost per unit decreases by a fixed percent every time total cumulative volume doubles.
* Applies to all free market products and services (over centuries) when measured in constant currency.
* Used to predict future costs.
— Aircraft industry
— Semiconductor industry
* Also true for subsystem or component costs and improvements in reliability, quality, yield, etc.

A non-linearity of growth in transistor consumption led to Moore’s Law adjustments.

Can Moore’s Law support 10X complexity?
Going forward, Moore’s Law doesn’t matter! The innovative assembly and packaging of multiple chips will drive lowest cost. The cost per function will continue to decline long after Moore’s Law is obsolete.

Growth in unit volume distinguishes semiconductors from other industries (see graph). The question is: Will transistor unit volume continue to grow at 49 percent annually for the next 10 years?

There has been constant or increasing IC unit growth. There have been only three years of negative growth in history. There has also been constant transistor unit growth. An order of magnitude increase in complexity Is likely by 2018. Therefore, what are the applications that will require 10X more transistors (per package) by 2018?

Now, computers and cell phones account for over 70 percent of semiconductor revenue. Also, semiconductor recessions are typically followed by the rapid growth of new semiconductor applications.

The economic cycle provides a boost to new DRAM intensive applications. Further, new NAND Flash applications will be accelerated by price decreases beyond Moore’s Law. The affordability of memory enables new applications and re-ignites the old appetites. The reduced memory cost drives new architectures and applications.

Dr. Rhines gave examples of how digital cameras achieved high volumes as falling prices ignited volume sales. Low prices generally tend to open up whole new markets. ASICs have even enabled sub $20 mobile handsets. The integration of new functionality also ignites demand in both new and old applications — an example being products and applications incorporating GPS.

As another example, the desktop PC market growth is slowing after 30 years. However, notebook/netbook/smartbook market appears to be headed for many years of growth ahead! Similarly, while the Internet penetration as well as mobile phone adoption are saturated in mature economies, both of them are in a high-growth mode in the emerging economies.

10X design complexity to increase by 2018
According to Dr. Rhines, the 10X design complexity will increase by 2018. The learning curve will continue to provide predictable cost reduction after Moore’s Law is obsolete. The transistor unit volume growth of nearly 50 percent per year will continue to drive the 35 percent per year cost reduction. Also, new applications will emerge to utilize the 10X growth of transistors per package, accelerated by recession-driven price reductions.

We will see a ~10X increase in transistors over the next eight years, leading up to 40 billion transistors by 2018, he added.

Delivering 10X and beyond design improvements
Four principal areas will also require 10X improvements in design methodologies. These are — high-level system design, verification, embedded software development, and back-end physical design and test.

In system level design creation, there is a need to raise the level of design abstraction from RTL to transaction-based.
* Transaction-based model generation
* System-level design and modeling standards
— C++, SystemC, UML, SysML, MatLAB

A new level of abstraction will meet 10X complexity requirements. The industry is due for next stage in abstraction. Design tools for 40 billion-transistor ICs are probably already available today, noted Dr. Rhines.

In functional verification, verification is falling further behind. We need exponential growth in verification capabilities to keep pace. A 10X increase in the number of transistors will require 1000X increase in verification. How can that be achieved? You can do the same thing, but do it faster. Or, you can eliminate redundant verification. You could also have transactional test benches, as well as mixed dynamic and formal verification. For instance, the intelligent testbench automation eliminates 90+ percent redundant verification.

Emerging Verification Techniques Near Term Productivity Gain
Emulation 100X-1000x
Intelligent Testbench 10X-100X
Transactional Testbench 500X-1,000X
Dynamic Formal 100-106X

In physical design and verification, there has traditionally been a new routing architecture every 2 ½ -3 technology nodes. You can do parallel optimization—MCMM, timing, etc. You can also merge place and route with full physical verification to reduce, or eliminate, ECO routing. Futther, you could opt for full parallelization of routing.

Lastly, the SoC design costs are forecasted to exceed $100 million within three years. Most of the SoC escalating design costs are attributable to the software development. All of these lead to the case for embedded software automation (ESA) – development and verification — in terms of re-use, automation and open standards. For instance, the Android platform has accelerated the embedded development beyond mobile phones.

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