Xilinx to build next-gen FPGAs on 28nm high-k metal gate
Xilinx Inc. has announced the foundation for a next-generation of Xilinx programmable platforms that will give system designers FPGAs that consume half the power at twice the capacity than previously possible for addressing the Programmable Imperative.
Xilinx’s architecture for next-generation FPGA products will be built on 28nm high-k metal gate (HKMG), high-performance, low-power process at TSMC and Samsung.
According to Suresh Menon, vice president, product development, Programmable Platforms Development, features of the next-generation FPGAs include:
* Reducing total power consumption enables customers to meet system integration and high-performance targets within their power budgets.
* Scalable unified architecture reduces customers’ investment developing and deploying products.
* Xilinx maximizes the value of 28nm with high-performance, low-power process to accelerate platforms for addressing the programmable imperative.
He highlighted some industry challenges. These include the decline ASICs — with development costs, risk and complexity, and time to market being 2x per node, leading to ASIC starts being 50 percent less per node and the ASIC business at -5 percent per year. The ASSP business model is also challenged. While it has grown at 22 percent CAGR from 2004-2009, the operating margins have declined by 27 percent, thus making tier 2 unsustainable.
Menon cited some examples addressing the programmable imperative — wireless communications, wired communications, industrial scientific and medical (ISM), automotive, consumer, and aerospace and defense.
Consumer demand is also driving network bandwidth. A challenge would be enable 1Terabit switch fabric and 400+Gbps line cards. This could been addressed by providing support for 1+Tbps full-duplex bandwidth for high-end switch fabric, enabling high-performance, non-blocking capability with flexibility to integrate QoS security, etc., and extending support for 40G, 100G, 200G, and 400G line cards.
Menon said, “We are delivering lower power through technology innovation, enabling the lowest power, high performance FPGA.” This is being done as follows:
* Reduce static power consumption by 50 percent.
– 28nm high-K metal gate high-performance, low power process reduces static power compared to 28nm high performance process.
* Lower dynamic power consumption using architectural innovations.
– Transistor choice and multi-gate oxide techniques reduce dynamic power consumption despite trends.
* Enable additional 20 percent power reduction using advanced tool innovations.
– Clock gating technology.
– Fifth generation partial reconfiguration.
World’s first ultra-high-end FPGA
The result — a 2x increase in capacity and IO bandwidth required to enable integrated solutions. Advanced tools reduce power and cost while enabling multiple design iterations in a single day for the world’s first ultra-high-end FPGAs.
According to Menon, Xilinx is also focusing on unified architecture. This will reduce customer’s investment in developing and deploying products. Products can now share the same blocks. This will result in migrating IP, Targeted Design Platforms, and customer designs from one FPGA family to the next.
The customer IP core libraries can now carry forward without redesign. The ecosystem can also develop and deploy broad IP and reference designs. Finally, the customer can now focus on differentiation through increased IP ease-of-use and re-use.
To achieve all of this would require optimal foundry partners for delivering the necessary capabilities. Xilinx has partnered with TSMC and Samsung for developing the next generation 28nm products.
How are Xilinx’s products moving forward? By lower power, integrating more, and meeting performance requirements. Unified architectures is shortening customer development time and preserving design investment. Xilinx is now delivering the value of 28nm technology and accelerate platforms.
All of this is being made possible by next generation Targeted Design Platforms, which will enhance and expand key platform enablers.
* Design environment enhancements.
– Design preservation, innovative clock gating, and fifth generation partial configuration.
* Interchangeable socketable IP creation
– Xilinx and ARM common interconnect.
* New targeted reference designs
– Optimized for domains and market specific requirements.
* Scalable unified board and kit strategy with FMC reuse.
– Expanding ecosystem enabling ease-of-use.