Semiconductor supply chain dynamics: Future Horizons @ IEF2011
The last decade heralded a dramatic transformation in supply chain dynamics, driven by the complexity challenge of staying on the More Moore curve. On the demand side, the high cost of fabs persuaded almost all integrated device manufacturers (IDMs) to use foundries for their leading-edge wafer supply.
The ever-increasing process complexity and its negative impact on manufacturing yields forced the adoption of sophisticated foundry-specific design-for manufacturing (DFM) techniques, effectively committing new chip designs to a single foundry and process.
At the same time, the industry adopted a much more cautious lagging rather than leading demand approach to new capacity expansion, resulting in under-supply and shortages in leading-edge wafer fab capacity. To make matters worse, the traditional oxide-based planar transistor started to misbehave at the 130nm node, as manifested by low yields and higher than anticipated power dissipation, especially when the transistors were supposed to be off, with no increase in performance, heralding the introduction of new process techniques (e.g., high-k metal gates).
Even before these structural changes have been fully digested, supply chain dynamics have been further disrupted by the prospective transition to 450mm wafer processing, to extreme ultra violet (EUV) lithography, and from planar to vertical transistor design.
Since the start of the industry, adding more IC functionality while simultaneously decreasing power consumption and increasing switching speed—a technique fundamentally known as Moore’s Law—has been achieved by simply making the transistor structure smaller. This worked virtually faultlessly down to the 130nm node when quite unexpectedly things did not work as planned. Power went up, speed did not improve and process yields collapsed. Simple scaling no longer worked, and new IC design techniques were needed.
While every attempt was made to prolong the life of the classic planar transistor structure, out went the polysilicon/silicon dioxide gate; although this transition was far from plain sailing, in came high-k metal gates spanning 65nm-28nm nodes. Just as the high-k metal gate structure gained industry-wide consensus at 28nm, it too ran out of steam at the 22nm-16nm nodes, forcing the introduction of more complex vertical versus planar transistor design and making the IC design even more process-dependent (i.e., foundry-dependent). Dual foundry sourcing, already impractical for the majority of semiconductor firms, will only get worse as line widths continue to shrink.
With more firms adopting an outsourcing strategy at 65nm and below (often misleadingly termed fab-lite or asset-lite, but in reality actually meaning fabless) the source of supply for such leading-edge processes became increasingly tight. This was driven by the limited number of foundries and remaining IDM players that could afford $3 billion fabs. There was also a deliberate change in wafer fab investment strategy, cutting back capital expenditure so capacity lagged rather than led demand to avoid the financially crippling side effects of over-capacity at the high-tech end of the market.
As can be seen from Fig. 1 here, investment in new semiconductor equipment as a percent of semiconductor sales straddled the 16.75 percent average from 1988 through 2008.
This changed in Q1 2008 when investment was cut back well before over-heating occurred and at a time when the “Main Street” economy was still in good shape; this cut back occurred a good three quarters before the Lehman Brothers global economic crash.
While new fab investment bounced back in 2010, it failed to reach the level of investment seen in 2007, was 9 percent lower than the
previous investment peak in 2000, and significantly slowed in Q4 2010, despite the fact that utilization was running at 96.6 percent and on allocation. As can be seen from Fig. 2, utilization figures have continued to increase, a situation that is not going to change given the investment cutbacks now in place.
The writing is thus now clearly on the wall; leading-edge wafer fab capacity is not going to become a commodity item, supply will be limited and longer term supply commitments are the new name of the game. The era of ever-cheaper, freely available wafers is over, at least at the leading edge. Welcome to the new world of a slowdown in processed wafer price reduction and the need to commit to capacity versus wafer procurement to guarantee sufficient availability.
Impact of 450mm
Just to add further competitive mud to the waters, 2011 saw the 450mm wafer transition gain traction. For several years now, 450mm wafer processing has been under discussion, but apart from work on setting standards, little has actually emerged. Indeed, much discussion focused on whether the industry could actually afford to make this transition, how much it would cost and who would pay for it. Whereas the major chip players wanted it, the equipment industry was universally against it—stung by the huge costs they were forced to swallow with the 300mm transition.
This climate changed dramatically during the first quarter of 2011 following Intel and TSMC’s near simultaneous announcements that they intend to roll out 450mm wafer technology in their latest fabs and Samsung’s “hints” that they would be “right up there too.” And at least three other fast followers are known to be waiting in the wings.
A parallel initiative by the European Commission to investigate the benefits of setting up 450mm semiconductor manufacturing in Europe, along with IMEC and ASML’s crucial role in the transition execution (together these firms control many of the 450mm patents) and New York State’s subsidized investment in a 450mm tool prototyping complex in Albany, added a geographic and political dimension. As such, even the most die-hard sceptics from the industry have now come round to accepting that 450mm will actually happen.
As with previous wafer size changes, the transition to 450mm wafer processing cannot be done overnight. But this time it does seem as if it will be well co-ordinated across the full industry food chain, from the advanced research centres in IMEC and Albany to the potential leading-edge semiconductor end users keen to keep up their 29 percent per year gate cost learning curve decline.
The transition from today’s 32/28nm advanced production nodes to the 11/10nm structures expected to be in early production around 2015/2016 is littered with process dislocations, both in the structure of the transistors and the means to pattern and build them, with the structures and patterning techniques different for each node.
Years 2015/2016 are also the approximate timescale for the first 450mm prototype facilities, which means that for the leading-edge memory and MPU supplier extreme ultraviolet (EUV) lithography is a must. The more conservative and longer design ramp lead times of foundries indicate that their flip will likely be one node behind in technology, albeit coincident in timing. Thus, whereas foundries do not need EUV lithography for their early 450mm production, for the rest, by 11nm EUV will be a must. The alternative option of triple- and quad-patterning immersion lithography is too slow and costly to bare thinking about.
The single biggest problem with the 300mm conversion was the fact that the process node became a rapidly moving target, starting at 250nm and, ultimately, ending up at 90nm, causing a raft of false starts and overlapping and redundant equipment development costs. It was this “wasted” research and development (R&D) cost that bruised the equipment industry so badly, hence their understandable reluctance to embrace 450mm processing.
Thus, while there are still some dissenting opinions as to whether the semiconductor process node roadmap and the transition to 450mm wafers are independent topics or if the two will need to become intrinsically linked, the fact that the industry is unwilling to repeat its 300mm mistakes and each node has its own process peculiarities, the balance of probabilities is that the node and 450mm development will be linked.
There is also an agreed and clear process introduction strategy to prove the 450mm platform first on a (relatively) mature and well-understood technology node before moving what by then is an established and well-understood 450mm platform to the then leading-edge technology node. This means that for a period of time 300mm will appear to be more node-advanced than its 450mm sibling. But it would be wrong to interpret this as an opportunity for extended or parallel 450/300mm node development—it is not. It is merely the reflection of a carefully thought out transition process; once node comparability has been established, 450mm will flip and all future advanced processing will be on a 450mm-based platform only.
While some people still argue that parallel node development will continue on 300mm and 450mm platforms, the likelihood is that this will not make economic sense, even if the equipment R&D resources are available. History has shown such transitions are both a huge drain on the infrastructure and the majority of the capacity investment dollars. This means that once the 450mm flip has occurred, all pressure (and capacity spend) will be on ways to improve 450mm productivity.
Demand from the likely fast followers such as Toshiba and the other large memory manufacturers (if Samsung goes 450mm, they have no choice); GlobalFoundries (likewise but by now competing against TSMC, Samsung and Intel all on a 450mm platform); and probably IBM (what chance does a 300mm end-of-life node-based Common Platform Alliance have against three hugely competitive 450mm-based foundry giants) will strain the equipment industry’s tool development resources further. There will thus not be enough residual investment dollars or resources available to parallel develop both platforms, nor does it make economic sense from a wafer cost point of view.
The downstream squeeze on the chip industry will be enormous. Customer pressure, limited R&D resources and dwindling long-term demand will drive the mainstream equipment industry to a “follow the 450mm dollars” strategy. Those firms on a 450mm platform will then enjoy a huge cost and technology advantage, forcing legacy 300mm capacity into ever-more boutique and specialist low volume product areas or other less-demanding applications (e.g., to cost reduce 200mm-based products).
Plus Ça change??? No, it IS different this time!
The move to 450mm will inevitably be an inflection point for the industry, with enormous ramifications for the complete semiconductor ecosystem. Those firms with 450mm capability will enjoy a huge competitive advantage of staying on the More Moore node development roadmap, a potential 30 percent lower die cost advantage and a more efficient manufacturing tool platform. The remaining 300mm platforms will be squeezed into increasingly over-crowded niches.
Transistor design complexity, new structures and increasingly tighter design rules will mean that semiconductor firms will be forced to choose a lifetime foundry partner; divorce and second sourcing will become too expensive for all but the very biggest firms to even contemplate. Only a handful of chip firms will have early access to next-generation foundry technology, giving them at least a one-year advantage over their competitors. This means many of today’s Tier 1 ex-IDMs will become foundry Tier 2 accounts—quite a humbling and significant competitive demotion.
The era of abundant leading-edge capacity is over; a deliberate over-investment strategy would be recklessly suicidal, even for an industry not best known for its rationality. Buying capacity up front will become the new industry norm, eventually to be enhanced by up-front contributions to future capacity investment costs and effectively co-owning portions of the capacity—a kind of IDM-lite model. From an equipment industry perspective, financing new tool development will mirror the airline industry model, whereby customers make long-term up-front commitments with deposits and partial payments to ensure both delivery and their place in the queue.
The combined effect that these changes will have on the semiconductor supply chain will be both far-reaching and profound, and a very different industry will emerge by the end of the decade. No longer will the industry simply muddle through the various challenges. New business models will emerge built increasingly on co-operation and partnerships, with an ever-increasing need for all parties to share the technology risks and costs.
The past adversarial-driven supplier-customer relationship will no longer be appropriate; for the first time in the industry’s history, across-the-board consolidation is unavoidable. The industry might even finally break its fixation with its inherent quarterly short-term fixation of making the quarterly number.
The issues address in this report will be debated more deeply at IEF2011 in Seville, Spain, 5-7 Oct 2011, Future Horizons 20th Annual International Industry Forum under the general theme “New Rules For Old…Achieving Success In The Age of Nano Tech”.
The event will focus on what we see as the immense paradigm shifts currently occurring in the industry as it squares up to the various technology challenges of embracing the nano-tech age (450mm, EUV, 3D transistors); the need for new business models (what Future Horizons has termed “the broken semiconductor industry model”; and the new design methodologies necessary to deal not just with the technology and manufacturing complexities but the system related challenges as well.