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Realizing EDA360: Charlie Huang, Cadence


Long-term trends are strong for semiconductor and electronics. According to databeans estimate (Feb. 2011), semiconductor revenue will likely reach $450 billion by 2015 and electronics revenuw will likely reach $2,800 billion by 2015.

Speaking at the CDNLive! 2011 event in Bangalore, India, Charlie Huang, SVP of Worldwide Field Operations, Cadence Design Systems Inc., said that the challenges in the near term are slowdown in Europe and USA. The weakness is driven by increasingly negative views on the global economy, end demand, orders and outlook. Key indicators are also showing that the economy is facing headwinds. The 2011 GDP growth projections have deteriorated since the beginning of the year. The economy has been marred by high unemployment and low consumer confidence.

As of now, innovation has been driving growth. Apps have been driving innovation, followed by video, mobility, cloud and green technology. The impact on the electronics industry is multi-fold. There is a new development paradigm and collaboration has been increasing. The IP is also expanding beyond cores and the EDA is changing.

Source: Cadence.

Source: Cadence.

The new development paradigm for system companies is to differentiate on applications and semiconductor companies must deliver on application-driven hardware-software platforms. IP has now expanded well beyond the core. EDA is also changing, and Cadence is investing to deliver on the EDA360 vision. There are multiple silicon realization challenges. Cadence silicon realization solutions enable fast, deterministic, end-to-end path to silicon success.

As an example, ARM and Cadence have collaborated on the GHz implementation of Cortex-A15. ARM chose ARM Artisan physical IP, evaluated the Cortex-A15 RTL, and supported CPF. Cadence optimized the EDA flow, experienced support at EAC, and provided EDA tool releases and iRM.

ARM, TSMC and Cadence also collaborated on the industry’s first 20nm Cortex-A15. TSMC provided the 20nm process qualification and A15 learnings. ARM handled the 20nm implementation experience, A15 considerations in 20nm and TSMC 20nm readiness milestone. Cadence provided the 20nm research to reality, contributed and grew the A15 expertise and TSMC 20nm readiness milestone.

The end result: the industry’s first 20nm Cortex-A15 tapeout, thanks to a successful three-way vertical collaboration. ARM, Cadence and TSMC engineers worked side-by-side. The project priorities included 20nm DPT implementation schedule and 20nm readiness milestone.

Huang touched upon the recent silicon realization highlights. Cadence has delivered advanced and unified end-to-end flows. This includes new integrated RTL-to-GDSII and custom/analog flows for low-power, mixed-signal, gigascale 28/20nm IP and SoCs. New tehnology from Altos Design and Azuros aquisitions improves performance and results in challenging designs.

The in-design DFM signoffs gives up to 100x performance gains. There was UVM metric-driven verification for LP, MS verification. Proven 3D-IC/silicon interposer offering was made for SiP/co-design.

Cadence has also experienced strong collaboration results with key ecosystem partners. There have been multiple 20nm/14nm test chips with multiple foundries. With TSMC, GlobalFoundries and Samsung, there have been 28nm flows and mixed-signal enablement. ARM optimized its A9 and A15 design flows.

The SoC realization challenges include finding, comparing, integrating and verifying IP. Interfaces must be verified across multiple subsystems. Cadence SoC realization solutions include memory management IP, interface IP and verification IP (VIP).

Some recent highlights of SoC realization include the industry’s first DDR4 IP solution. The complete solution includes controller, soft and hard PHY drives, VIP memory models and signal integrity reference designs. Another is the wide I/O memory controller IP for mobile apps. This includes the memory controller, PHY and integration environment. There is also the Cadence design IP roadmap with focus on 28nm. This includes the PHY and SerDes IP targeted at TSMC 28HPM, as well as the DDR, Ethernet and PCI Express.

System realization challenges include bridging the hardware-software convergence gap. This involves the time-to-market, development cost, multi-core design and verification complexity, integration of new designs and derivatives, software stack development and hardware-software convergence.

Cadence’s system realization programs include the system development suite, transaction level modelling and verification IP. Some of Cadence’s recent system realization highlights include new system development suite that bridges the hardware-software design gap to meet the demands of apps-driven electronic design. A new ARM ACE verification IP accelerates development of multiprocessor mobile devices. There is also a new verification IP for emerging mobile device standards.

Cadence is involved in several strategic programs. There is 20/14nm work with foundries, such as double patterning, in-design DFM and FinFETs. There are ARM optimized solutions, such as high-speed cores, integrated into system development suite. There are high-performance advanced-node design IP such as SerDes and analog front-end solutions. There is time to integration, which involves automation to accelerate time to market for derivative designs. Finally, there is SiP/3D-IC co-design, such as unique silicon/package/board co-design flow for SiPs and 3D-ICs.

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