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Global semiconductor industry keeps consolidating; 28nm will be stable: Dr. Wally Rhines

December 2, 2011

Dr. Wally Rhines, chairman and CEO, Mentor Graphics.

Dr. Wally Rhines, chairman and CEO, Mentor Graphics.

The global semiconductor industry keeps consolidating, said Dr. Walden (Wally) Rhines, while making the keynote presentation at the ongoing Mentor Graphics’ U2U conference in Bangalore, India.

According to a survey, the no. 1’s market share has been relatively flat since 1972. The combined share of the top five semiconductor companies has been nearly the same as that of 1972. However, the share of the top 10 companies has been nearly the same but less than the historical average. If you look at the numbers, it is also evident that Texas Instruments’ (TI) acquisition of National Semiconductors has had negligible impact. Also, the market share of the top 50 semiconductor companies continues to decline, especially in the last decade.

The answer lies in the fact that manufacturing is consolidating, while semiconductor is not! Foundries share of semiconductor revenue has increased. The share of total IC production has been flat. However, foundry capex has tripled over the last two years. Also, 28nm/32nm capacity has been sold out, and prices rising have been put on top of the next slide. Foundries are likely to revamp and record the highest market share of the 28nm/20nm market. Foundry spending is said to be at an all time high as percentage of total capex.

There have been significant design changes. In fact, 28nm has now become the ‘work horse’ technology. There have been high yields and at lower costs. The accelerated design activity has seen redesign take advantage of smalller node efficiencies. So, how can you prepare? Perhaps, do more design in less time, and use the same resources. Or, you could do less of power devices.

Significant changes are coming in design. Because of 2010/2011 capital expenditures, 28/20nm semiconductor technology will become a major “work horse” compared to previous technology generations. Plenty of wafers will be available from silicon foundries. Yields will be high and costs will be low.  As a result, design activity will accelerate beginning in late 2012 to take advantage of the 28nm capability and capacity. Favorable costs and yields will cause semiconductor companies to redesign 180/130/90/65/45nm products into 28/20nm versions while adding functionality. Totally new applications will emerge because of the 28/20nm capability and cost, thus growing the semiconductor market in 2014+.

Implications of plentiful 28/20nm foundry capacity include: 28nm will become “work horse” technology. There will be high yields and low costs, as well as an accelerated design activity. Redesigns will take advantage of smaller node cost efficiencies. New designs will leverage the additional transistors.

In future, more companies will be moving to ESL-based design. Place and route will be more in fashion — 20nm double patterning, as well as DFM and integrated verification. DFM will pave the way for designing for reliability. The metal layer stack has been doubling as device complexity has been rising. Another factor is reliability checking. Initial efforts aer being offered at TSMC AMS flow 2.0. More will be offered by TSMC for digital flow in Q4.

To meet design, cost and power pressures, there will be a move to ESL-based design that require high-level design tradeoffs performance/power and RTL low power optimization. Place and route will assume importance — 20nm double patterning, DFM and integrated verification as well as 100M+ instance capacity and top level assembly/clock tuning. DFM or design for reliability and yield ramp-up will also gain in importance.

More designs can be done in less time, at less power, and same resources. The intelligent test bench and hardware acceleration/emulation will help deal with 1000x increase in functional complexity. System design methodologies—chip, board and system level would come in, in form of signal and power integrity, 3D and embedded software.

Reliability checking is needed at all process nodes, to verify reliability issues (not just the most advanced nodes). TSMC and Mentor are jointly developing and educating the industry on the need for this new class of checks. Mentor and TSMC are also co- developing reliability kits.

Next, emulation has been a fast-growing sector of the EDA industry for the past one to two years. System design methodologies and PCBs are core to product delivery. Also, 3D ICs are adding challenges while integrating packaging issues into IC design. Early 3D IC adoption is said to be driven by performance, power and form factor. The 2.5D IC will provide long cost-effective transition.

3D-IC is adding challenges while integrating packaging issues into IC design. The early 3D-IC adoption will be driven by performance, power and form factor. The 2.5D-IC will provide a long, cost-effective transition. There will be power/performance impact on processor/memory stacks, such as wide I/O 512 bit bus on processors, flip-chip memory with chip-layout standards, and interposers. Closely coupled package and chip design will provide low power, high performance system functions.

If one looks at the 3D-IC roadmap, today, there are sensors on logic, limited-volume stacked memory and package-on-package and flip chip memories on processors. The next two to three years will see 2.5D+ chips that see rapidly increasing use of interposers, integration of logic and memory with flip chips and interposers, mixed analog, RF, logic and memory in multi-die stacks, TSVs outside active circuitry, and interchangeable use of die from different vendors in 3D-IC configurations. The future, that is five+ years from now will see 3D that embed TSVs in leading-edge logic chips, as well as mixed analog, RF, logic and memory in multi-die stacks.

In summary, because of 2010/2011 capital expenditures, silicon foundry share of 28/20nm semiconductor revenue will double versus the 65nm+ generation. 28nm will be a stable, high volume, cost-effective production technology node. There will be cost-driven redesigns of products in older technologies and new designs will leverage the increased capability.

Design methodologies will change. There will be power/performance tradeoffs at the ESL level, new physical design capabilities including DFR, DP, P&R will come up, tools will be there to ramp-up production yields more rapidly. There will be 1000X in functional verification improvement, as well as system, software and 3D design methodologies.

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