Milpitas, USA-based Sonics Inc. participated in TSMC’s Soft IP Alliance 2.0 beta program. Driving high quality soft IP eases customer integration and expedites time-to-market.
Sonic’s role in TSMC beta program
Speaking on the beta program and Sonics’ role, Frank Ferro, director of Product Marketing, Sonics, said: “TSMC’s Soft IP kit 2.0 beta program is part of TSMC’s Open Innovation Platform program that creates a complete ecosystem for customers with the overall goal of shortening design time. This is done by providing a large catalog of partner provided IP that is silicon-verified and production-proven.
For vendors like Sonics, TSMC has extended this ecosystem to include Soft-IP (IP not designed for a specific process, but delivered as RTL). The program allows Soft-IP partners to access and leverage TSMC’s process technologies to optimize power, performance and area for their IP.
IP cores are checked through TSMC’s foundry checklist to ensure the customers have optimized design results with fast IP integration built into their design. This flow also facilitates easy IP reuse for subsequent designs. The soft IP Kit beta 2.0 program is an extension of the current program through implementing additional quality checks, improving results and making the flow easier for customers.
There are several advantages to Sonics as a participant in this program. First, customers of TSMC will have access to Sonics IP through TSMC’s IP library. Given TSMC’s strong market share, this will allow Sonics IP to be visible to a large customer base. In addition, TSMC’s customers will feel securing using Sonics IP because they know that it has been put through a rigorous series of IP checks that meet the highest quality standards. It also allows Sonics early access to TSMC’s process libraries, allowing Sonics to optimize performance and area for each IP product.
So, what can the TSMC’s Soft IP Kit 2.0 do? How does Sonics enhance its capabilities? The Soft IP Kit 2.0 provides a specific RTL design flow methodology and hand-off which includes: lint (RTL coding consistency), clock domain crossings (CDC), power (CPF/UPF), physical design (routing congestion), design for test (DFT), constraints and documentation.
Using this flow enhances Sonics IP quality and reliability because many RTL errors can be caught at an early stage. As mentioned above, this flow ensures lowest power and best performance of the IP for a given process node.
Atrenta SpyGlass improves packaging
There is a role played by Atrenta SpyGlass. According to Ferro, Atrenta SpyGlass is the tool used to run all the tests. The flow was developed to TSMC’s standards and implemented by Atrenta. Given Sonics strong relationship with TSMC and Atrenta, we were invited to be a beta partner using our IP to test the new flow. A number of companies do participate in the program, although only Sonics has announced participation in the beta 2.0 program to date.
This tie up with Atrenta will likely improve IP packaging. As part of the overall flow, the final step, after all basic and advanced IP checks, is IP packaging. This step includes providing the IP with information on the design intent, set-up and analysis reports. Again, this is done using the SpyGlass tool from Atrenta.
This IP packaging was available to customers in the past via the Soft IP 1.0 program. The attraction of this type of IP packaging is a result of the growing number of IP cores being integrated into complex SoCs. As the number of third party IP grew, the need for a better, broader methodology was developed.
The outlook for the global solar PV industry does not look encouraging, at least, if recent happenings are set as benchmark. How will the global solar PV industry perform in 2013? How will the modules segment perform? How will solar cells segment perform in 2013?
Dr. Henning Wicht, director and principal analyst Photovoltaics, IHS iSuppli, said: “The industry will remain under pressure. We expect prices to decline further on all nodes. Margins will remain thin. Cell production outside of China, in particular Taiwan, can benefit from US anti-dumping tariffs on Chinese modules.
“However, Taiwanese cell producers will face difficulties, since European customer base will shrink. Module production will remain challenging. Prices are expected to decline further due to overcapacities and fierce competition.” Here is a graph of the module price decline.
There are a few other questions. Did the global solar PV industry touch 22 GW in 2012? What is the prediction for 2013? Also, how is Japan doing? Are we seeing pro REE politics there?
Dr. Wicht said that IHS iSuppli expects 31 GW of new installations in 2012. For 2013 IHS iSuppli forecasts 35 GW. “Installations in Europe
are declining, while installations in emerging markets and Asia are increasing. China, US and many of the new markets favor ground installations. Europe and Japan address more rooftops. Japan has been seeing a lot of activities in H2-2012. We expect this boom to continue into 2013.
“IHS expects that the Japanese government will adjust tariffs in 2013, since investment conditions are very generous. This is helpful to kick-start the market. However, the generous tariffs will become expensive for rate payers if maintained too long. Details on tariff adjustment are not yet defined.”
Finally, how will the industry focus on electricity storage and grid integration in 2013? And, what’s going to happen with Chinese suppliers in 2013?
Dr. Wicht replied: “Solar companies will see continuing and even increasing difficulties during 2013. Thin margins for all producers (including silicon) will maintain. Smaller players will stop production. Also 2nd and 3rd tier Chinese suppliers will partially stop production. Tier 1 Chinese players will face difficulties of financing if stock prices will not increase and companies will be excluded of Nasdaq (pending).
“Also, anti-dumping investigations in Europe can harm Chinese module business in 2013 since buyers will be careful to avoid any retroactive tariff from beginning of 2013. Strategy wise, 2013 will be a very difficult year. Electricity storage is an emerging topic, which is now addressed mainly by inverter suppliers. Grid integration of PV power is becoming a concern of EPCs and investors.”
Argon Design, a leading developer of high performance software applications for manycore communications processors, launched Argon Blaster, the industry’s first flow simulation solution for generating realistic, Internet scale traffic loads and applications to test networking and security equipment.
Blaster delivers a line rate, timing accurate, flow simulation application on an affordable PCIe acceleration card for use in standard x86 platforms. This enables OEMs to cost effectively distribute a high performance simulation and traffic generation solution throughout the engineering organization. The approach significantly reduces development time and cost, while simultaneously increasing product quality.
Blaster is designed for enterprise and carrier network operators for performance testing of flow based cyber security and network analytics applications. It enables network managers to verify that these systems are designed and deployed in a manner to match expected network loads.
High performance, accuracy rule!
Elaborating on the features, Daniel Proch, director of product management, Netronome, said: “Argon Blaster is the industry’s highest-performance and most-accurate flow simulation solution, in an affordable package. Developed by Argon Design, Blaster enables a standard x86 PC with a Netronome flow processor PCIe card to generate realistic, Internet-scale traffic loads and application mixes.
“For many networking applications, the ability to classify and manage traffic flows is key to enabling the highest level of performance and scalability. Quality of Service, Load Balancing, Firewall, Intrusion Detection, Content Inspection, Data Loss Prevention and similar applications all typically require flow-aware processing capabilities and this flow-aware traffic generation solution for development and QA. Blaster is the first traffic generation tool designed specifically for flow simulation applications. With Blaster, you can emulate up to a million unique flows with accurate, consistent, per-flow rate control.”
It will be interesting to know how Blaster will help the ISVs and OEMs generate realistic, Internet-scale traffic loads and applications to test networking and security equipment.
Blaster can be installed in any modern PC running Linux. It installs as a KVM virtual machine and can be operated from within the virtual machine or externally. It replays one more multiple .pcap files and can take that traffic and emulate any type of traffic profile from that pcap(s). The user can change the # flows per pcap file, the addressing scheme (# clients and servers based on MAC and or IP address).
From this set of knobs and given a set of pcaps with appropriate application traffic to any traffic load and application mix that is desired. Organizations can then offer:
* Performance benchmarking to isolate bottlenecks.
* Stress testing with real-world loads.
* Security testing with background, application and attack traffic.
* Quality assurance with broad spectrum of application and protocols.
Let’s find out a bit more about the role played by Netronome as well as Argon Design. Proch said: “The product is an Argon branded product that is a joint development with Argon Design. Netronome provides the accelerated flow processing hardware for the solution in the form of a standard PCIe card, and Argon designed and engineered the software. Netronome will be handling sales and marketing of the product. Software and support will be handled by Argon.”
Will there be an upgrade sometime later, next year, perhaps? “Most certainly,” he continued. “Our early access customers and internal use has already developed a robust roadmap and we anticipate these features and others to be rolled out over several subsequent software releases. We also expect to have a new hardware version based on our recently announced NFP-6xxx family of flow processors when available.”
It always gives me great pleasure chatting with Dr. Walden (Wallly) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA. 2013 is just round the corner. What lies ahead for the global semiconductor industry is a question on everyone’s lips! How will the EDA industry do next year? For that matter, what should the Indian semiconductor industry look forward to next year?
Three trends for 2013
First, I asked Dr. Wally Rhines regarding the trends in the global semiconductor industry. He cited:
* Growth in communication ICs.
* Growth in the third dimension.
* Accelerated design activity at the leading edge.
Growth in communication ICs: On the macro level, silicon area shipments continue to grow gradually, as do semiconductor unit shipments. However, there’s a major shift in application segments from computing to communications. Communications used to be only one third the size of computing in terms of semiconductor usage.
Communications are expected to surpass computing in terms of semiconductor consumption by 2014 thanks to the rapid growth of wireless applications, the incorporation of computing into communications devices like smart phones and the addition of communications to computing devices like tablet computers.
Growth in the third dimension: Shrinking feature sizes and growing wafer diameters will continue to contribute to the annual 30 percent decrease in the average cost per transistor and average 72 percent unit growth of transistors, but they will do so at a diminished rate. Fortunately, other avenues are emerging that can help sustain the semiconductor industry’s remarkable rate of growth. One largely untapped opportunity is in the third dimension, i.e. growing vertically instead of shrinking in the XY plane.
DRAM stacks of eight or more die are already possible, although they are still more expensive on a cost per bit basis compared to unstacked devices. Complex packaged systems made up of multiple heterogeneous die, memory stacked on logic and interposers to connect the die are evolving rapidly. Layers in the IC manufacturing process continue to increase as well.
Accelerated design activity at the leading edge: Another interesting trend is the recent surge in capital spending among foundries to add capacity at the leading edge. This wave of spending will result in excess capacity, at least initially, which may force foundries to lower prices to boost demand. In fact, capacity utilization data in the last few months shows a dramatic decline in utilization at 28/32nm and 22nm nodes, suggesting that excess capacity is already happening to an extent.
While differences in 28 and 20nm processes—such as double patterning—create challenges, the existing capital equipment is largely compatible with both processes. Such a high volume of wafers and the large available capacity will lead to increasingly aggressive wafer pricing over time. As a result, cost-effective wafers from foundries will encourage totally new designs that would not have been possible at today’s wafer cost.
Industry outlook 2013
So, how is the outlook for 2013 going to shape up? Dr. Rhines said: “After almost no growth in 2012, most analysts are expecting improvement in semiconductor market growth in the coming year. Currently, the analyst forecasts for the semiconductor industry in 2013 range from 4.2 percent on the low side to 16.6 percent on the high side, with most firms coming in between 6 percent and 10 percent. The average of forecasts among the major semiconductor analyst firms is approximately 8.2 percent.
“However, most semiconductor companies are less optimistic in their published outlooks. This seems to be influenced by the level of uncertainty that exists because of unknown government actions and market conditions in the US, Europe and China.”
Any more consolidations?
It would be interesting to hear Dr. Rhines’ opinion on any further consolidations within the industry. He said: “It is common misperception that the semiconductor industry is consolidating. A closer look at the data shows that the semiconductor industry has been doing the opposite. It has been DE-consolidating for more than 40 years.
“Take the #1 semiconductor supplier, Intel. Intel’s market share is the same today as it was a decade ago. And, the combined market share of the top five semiconductor suppliers has been slowly declining since the 1960s. Similar trends also apply to the top ten and top 50—both are the same or lower than they were a decade, as well as decades, ago. In fact, the combined market share of the top 50 semiconductor companies has decreased 11 points in the last 12 years.
MonolithIC 3D Inc. was established in 2009 by Dr. Zvi Or-Bach, a well-known Silicon Valley serial entrepreneur, as NuPGA. The NuPGA’s mission was to develop programmable logic technology with density, speed, and power approaching ASICs.
On the way, while developing improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D-ICs. Recognizing that this breakthrough and its many related innovations represented a paradigm shift for the entire semiconductor industry, Dr. Zvi Or-Bach changed the strategy to focus on monolithic 3D-ICs, and renamed the company MonolithIC 3D Inc.
Monolithic 3D is based in San Jose, California, USA, where I met Dr. Zvi Or-Bach, president and CEO. First, I asked him to elaborate on the technology breakthrough that allows the fabrication of semiconductor devices with multiple tiers of copper connected active devices utilizing conventional fab equipment.
Dr. Zvi Or-Bach said: “The challenge is that once interconnect made of copper (or aluminum) is in that wafer should not be process at higher than 400 degrees C. The common view is that forming single crystal transistors would require higher than 1,000 c. The common view is that forming transistor in monocrystalline silicon layer require higher than 800 c. MonolithIC 3D’s innovation is finding path to overcome the above challenge utilizing monocrystalline silicon layer and conventional fab equipment.”
MonolithIC 3D offers solutions for logic and memory technologies, with significant benefits for cost, power and operating speed. The benefits for logic is detailed in Monolithic’s blog: Is the Cost Reduction Associated with Scaling Over?
Monolithic 3D provides the equivalent of one node of scaling for every folding at fraction of the development and equipment costs. And, it provide additional benefits such as:
* Significant advantages for using the same fab, design tools.
* Heterogeneous integration.
* Process multiple layers together Nx cost improvement.
* Logic redundancy => 100x integration.
* Enable modular design.
Dr. Zvi Or-Bach added: “The benefits for memory is that allow processing multi-layers of single-crystal memories at comparable lithography cost of single layer. As of today, lithography costs dominate process costs than monolithic 3D allow future scaling at ever reduce costs and higher memory capacity.”
The company believes in collaboration with existing players in the semiconductor industry. MonolithIC 3D is not an IC producer, but rather, a technology innovator, who also file many patents which are available to be license by all industry players. Monolithic has been assigned a patent (8,294,159) developed by five co-inventors for a “method for fabrication of a semiconductor device and structure. In fact, MonolithIC 3D has now been 20 granted patents of which 20 had been already issued.
PS: I am extremely grateful to Dr. Tim Majumdar, senior RF engineering manager and inventor, who pointed me to this company.
Xilinx Inc. has announced its 20nm portfolio strategy. The 20nm portfolio will allow Xilinx to offer twice the performance at half the power. It will increase productivity by 4x, and improve integration by 1.5- 2x. Besides, there will be 20-50 percent lower BOM cost.
Xilinx’s 20nm all programmable portfolio builds on 28nm breakthroughs to stay a generation ahead. “At 20nm, we were able to break out to become an all programmable company,” said Neeraj Varma, country manager, sales, India, Australia and New Zealand, Xilinx India.
The next generation FPGAs, second generation SoCs and 3D ICs will be ‘co-optimized’ with Vivado for the most compelling alternative ever to ASICs and ASSPs. From enabling programmable logic, the Xilinx 20nm portfollio will enable programmable systems integration!
The first SoC strength design suite was shipped in Q2-2012. It has been built from ground up for the next decade of all programmable devices. Today, the Xilnix Vivado is used for over 30 percent of 28nm FPGAs and 100 percent for 3D ICs.
Xilinx has been expanding on its next generation competencies. The 3D IC expertise and supply chain has gone from homogenous to heterogenous. The SoC and embedded software has also undergone change, as have XCVRs and analog mixed signal (AMS), communications BU and applications IP, and next generation design automation. Xilinx is now charting an aggressive course forward.
Xilinx’s 20nm portfolio has been co-optimized for performance, power and integration to address the market needs at 20nm. For the next-generation FPGA,, it will provide unmatched system optimized transceivers at highest channel quality w/ second generation auto equalization. There will be higher bandwidth w/over 100 transceivers @ 33Gb/s.
There will be 2X performance optimization, with faster DSP and BRAM, DDR4, transceivers and 2x memory bandwidth. There will be over 90 percent routing architecture enabling high bandwidth bussing and fast design. One half power optimization will provide an optimized performance/watt. There will be next generation block level power management. There will be 1.5x integration/BOM in terms of 1.5x logic, DSP, BRAM, AMS, VCXO, etc. Read more…
Palo Alto, US-based Elliptic Labs has introduced the world’s first commercial touchless gesturing technology using ultrasound, designed for electronic devices and Windows 8. Elliptic’s breakthrough technology is the first of its kind commercially available and has been incorporated in the Windows 8 Gesture Suite, introduced today. So, what’s this new technology from Elliptic Labs really all about?
Well, OEMs now have a commercially available technology to integrate gesture recognition in their terminals – with extremely low power and robust detection of hand gestures. The technology is based on ultrasound, and requires a small number of low-cost components (microphones, transducers) for integration in the terminal.
The actual gesture recognition is done on the host CPU, running a power-efficient detection software provided by Elliptic labs. Ultrasonic gesture recognition has a perfect fit with Windows 8 user interface, and the company provides gestures for very simple interaction with a Windows 8 terminal with the new Modern/METRO user interface.
With this technology, you can command a laptop simply by gesturing in front of the computer, and to the sides and above the screen. A key feature of ultrasound is that Elliptic Labs supports gestures not only in the front of the computer, but also to the sides and above, enabling intuitive interactions with the terminal.
Another advantage of ultrasound is that it works in complete darkness, and in direct sunlight, which is challenging for camera-based solutions, and very important for mobile use. Yet another great news is the availability of a Software Development Kit (SDK), so that the OEMs and ISVs can adapt the technology to their particular applications. Elliptic Labs has provided a Starter Kit to get started with ultrasound gestures in minutes!
Mobiles and tablets groove!
This technology can also be used in laptops, mobiles and tablets. A Windows 8 laptop can be operated by simple gestures, which is
usually found on touch screens. The OEMs and ISVs can now create new and intuitive user interfaces for a Windows 7 or Windows 8 computer as they wish.
With the SDK, game developers can quickly port their games to support ultrasound controls, and business applications can leverage gestures for quick browsing, selection, and general operation of software. Mobiles and tables can also leverage ultrasound gestures, as the SDK is being made available also for the Android operating system.
Elliptic Labs has made use of the ultrasonic approach, which apparently, makes life easier for batteries. The amount of information from a few microphones is much smaller than the amount of information from camera-based solutions. The algorithms for ultrasound gesture recognition can execute with less instructions, resulting in significant lower power usage.
As a result, the ability to do gesture recognition can be “always on”, so users can rely on gestures for all applications of the terminal. The aspect of power consumption is of particular importance for mobile terminals.
Elliptic is a leader in ultrasonic touchless gesturing for consumer electronic devices. Its patented, low-power, responsive new technology is superior to the limited, camera-based approaches on the market. The Windows 8 Gesture Suite enables a touchless version of all touchscreen gestures in the new operating system. Combined with Elliptic’s SDK, the technology gives OEMs the flexibility to create disruptive new ways to interact with devices.
Elliptic’s ultrasound technology uses sound waves and microphones to detect movement, similar to how radar detects objects. The technology is not limited to detecting movement within camera view — it detects natural hand movements that extend beyond the camera, surrounding a device screen.
What does 2013 have in store for the global (and Indian) seniconductor industries? Will it do better than 2012 or will it be even? I had a chat with Somshubhro Pal Choudhury, managing director, Analog Devices India Pvt. Ltd recently on this subject. First, I asked about the trends in the global semiconductor industry.
Choudhury said: “Consumer and telecom have driven the growth incessantly for the past decade for the semiconductor industry and will continue to do so. Over the next three years, industry analysts estimate the global industry will grow approximately 6 percent 2013-2016 CAGR.
“Portability and wireless connectivity will continue to drive a significant portion of the industry growth. Increasingly, automotive market is becoming very lucrative as the quantity of electronics going inside automobiles is increasing phenomenally in safety, power train, smart vision and fuel efficiency applications, not to mention the use of wireless connectivity.
“Medical electronics is getting smaller, smarter with better diagnostic technologies while the demand is increasing with aging population, increased longevity and lifestyle oriented diseases. Applications such as in-home patient monitoring will use wireless connectivity to stay in contact with physicians and emergency services.
“Industrial automation, energy and defense sectors are growing with more factory automation, solar energy focus worldwide, electronic warfare and so on. Intelligent, connected, and energy-efficient systems are leading to higher electronics content, with sensors and motors distributed throughout the industrial complex being connected wirelessly.
“Finally, the wireless and wired networks that transmit and receive all these channels of data will be a major driver of growth over the next few years with proliferation of 4G and increasing amount of fiber.”
Outlook for 2013
How is the outlook for 2013 going to shape up? What are the technologies likely to make an appearance and why?
According to Chowdhury, the 4G LTE deployment should be a major applications area driving 2013. To that end RF, high-speed signal processing, and power management will be important technologies to advance the price/performance of 4G networks. MEMS technology continues to find new applications in medical, defense and industrial applications over and beyond the tablets, handsets, gaming consoles and airbag sensors in cars.
Will there be further consolidations within the industry? He added that M&A will continue to play a role in the industry. The companies in the industry are not hampered by their financial abilities to acquire businesses, but identifying complementary opportunities and successfully integrating them is not without risk.
And how does the global EDA industry look like doing in 2013? As per Choudhury, the EDA industry continues to innovate and that pace will continue in 2013. These innovations are not only driven by the challenges of moving to the next node, but also for mixed signal designs, in analog-digital co-simulation and verification domain.
ReneSola Ltd, a leading global manufacturer of solar PV modules and wafers, has introduced its new Virtus II multicrystalline modules in India. ReneSola has started providing locally produced PV modules to the Indian market and expects to provide 250 MW of India-made PV modules over a two-year period.
The India launch follows the successful introduction of the Virtus II solar modules to the US and Australian markets.
Founded in 2005, Renesola has 17 subsidiaries worldwide. Production sites located in Zhejiang, Jiangsu and Sichuan, China. The supplier estimates to ship 1,550 ingots and 700 wafers during 2012, up from 1,014.1 ingots and 295,2 million wafers in 2011.
Some of Renesola’s projects include 4MW and 2MW in Slovakia, 11.5MW in Germany, 20MW in China, 9.21MW in Italy, and 27.6MW again in Germany. A couple of Renesola’s rooftop projects include 118.8KW in Slovakia, 1.95MW and 100.8KW in Greece, 1.4MW in Belgium, 12.96KW in Bulgaria, and 806.4KW in Germany.
Virtus II modules
Characteristics of the Virtus II modules include higher power output, higher performance at same cost, same LID, and same CTM cost. Virtus ingot improves the distribution of grain size and lifetime, and provides higher lifetime and lower dislocation density. The Virtus A++ wafer allows uniform grain distribution with less defects. The Virtus A++ wafer also has much lower defects.
Major defects of conventional multi‐crystalline wafers can be reduced by the innovative controlled DSS method. The Virtus I module provides better temperature coefficient of power and lower light induced degradation compared to mono modules. The Virtus II wafer increases cell efficiency due to higher lifetime, lower dislocation and uniform grain size. The Virtus II module shows better performance and the same production cost of multi-module.
Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.
IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&D pilot line will enable full 450mm process capability for advanced nodes by early 2017.
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture.
Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.
IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.
IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.
With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.