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Xilinx announces 20nm portfolio strategy

November 14, 2012

Source: Xilinx, USA.

Source: Xilinx, USA.

Xilinx Inc. has announced its 20nm portfolio strategy. The 20nm portfolio will allow Xilinx to offer twice the performance at half the power. It will increase productivity by 4x, and improve integration by 1.5- 2x. Besides, there will be 20-50 percent lower BOM cost.

Xilinx’s 20nm all programmable portfolio builds on 28nm breakthroughs to stay a generation ahead.  “At 20nm, we were able to break out to become an all programmable company,” said Neeraj Varma, country manager, sales, India, Australia and New Zealand, Xilinx India.

The next generation FPGAs, second generation SoCs and 3D ICs will be ‘co-optimized’ with Vivado for the most compelling alternative ever to ASICs and ASSPs. From enabling programmable logic, the Xilinx 20nm portfollio will enable programmable systems integration!

The first SoC strength design suite was shipped in Q2-2012. It has been built from ground up for the next decade of all programmable devices. Today, the Xilnix Vivado is used for over 30 percent of 28nm FPGAs and 100 percent for 3D ICs.

Xilinx has been expanding on its next generation competencies. The 3D IC expertise and supply chain has gone from homogenous to heterogenous. The SoC and embedded software has also undergone change, as have XCVRs and analog mixed signal (AMS), communications BU and applications IP, and next generation design automation. Xilinx is now charting an aggressive course forward.

Xilinx’s 20nm portfolio has been co-optimized for performance, power and integration to address the market needs at 20nm. For the next-generation FPGA,, it will provide unmatched system optimized transceivers at highest channel quality w/ second generation auto equalization. There will be higher bandwidth w/over 100 transceivers @ 33Gb/s.

There will be 2X performance optimization, with faster DSP and BRAM, DDR4, transceivers and 2x memory bandwidth. There will be over 90 percent routing architecture enabling high bandwidth bussing and fast design. One half power optimization will provide an optimized performance/watt. There will be next generation block level power management. There will be 1.5x integration/BOM in terms of 1.5x logic, DSP, BRAM, AMS, VCXO, etc.

The second generation SoC will offer 2X performance optimization, second generation multi-core, one half power optimization, next-generation design tools and 2X integration/BOM. The second generation 3D IC will feature wide memory for high performance buffering, more than 5X die-to-die interconnect bandwidth, and support future XCVR protocol (56Gb/s).

The next generation of productivity will have an unmatched time to integration and implementation. The time to integration will see >100x faster C verification, >4x faster C to verified RTL, 3-100x faster RTL simulation and hardware co-simulation, and 4-5x faster IP re-use and time to IP integration.

Likewise, the to implementation and QoR will see >4x faster design closure, >3x faster incremental ECO, 20 percent better LUT utilization, up to three speed grade better performance and ~50 percent average power advantage.

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