Exar serving high-growth areas with innovative value-added solutions

Louis DiNardo.

Exar Corp., established 1971, is headquartered in Fremont, USA, and has design centers in Silicon Valley and Hangzhou, China. Louis DiNardo, president and CEO, Exar, said that the company’s strategic model is to serve high-growth markets with innovative value-added solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Exar offers solutions that includes high performance analog-mixed signal as well as data management solutions. Its current market focus is on networking and storage, industrial and embedded systems, and communications infrastructure. It is focusing on power management products, connectivity products and data management solutions.

Power management products include those for analog power management such as switching regulators, switching controllers, linear regulators, supervisory controllers, etc, For programmable power, Exar focuses on multiple output synchronous buck controllers.

Some of the products include POWER, the Exar Programmable PowerSuite 5.0. Recently, Calceda has been powering servers with the PowerXR technology.

For data compression and security, Exar is offering hardware acceleration and software solutions meant for compression and decompression, acceleration, encryption and decryption. There are high growth markets supporting social networking, industrial Internet and financial technology as well.

Exar’s Panther I is a first generation compression/security engine with the PCIe interface. The Panther II is a second generation compression and security engine with PCIe and FPGA interface.

Semicon in sub-20nm era: Business as usual or different?

We are now entering the sub-20nm era. So, will it be business as usual or is it going to be different this time? With DAC 2013 around the corner, I met up with John Chilton, senior VP, Marketing and Strategic Development for Synopsys to find out more regarding the impact of new transistor structures on design and manufacturing, 450mm wafers and the impact of transistor variability.

Impact of new transistor structures on design and manufacturing
First, let us understand what will be the impact of new transistor structures on design and manufacturing.

John Chilton.

Chilton said: “Most of the impact is really on the manufacturing end since they are effectively 3D transistors. Traditional lithography methods would not work for manufacturing the tall and thin fins where self-aligned double patterning steps are now required.

“Our broad, production-proven products have all been updated to handle the complexity of FinFETs from both the manufacturing and the designer’s end.

“From the design implementation perspective, the foundries’ and Synopsys’ goal is to provide a transparent adoption process where the methodology (from Metal 1 and above) remains essentially the same as that of previous nodes where products have been updated to handle the process complexity.”

Given the scenario, will it be possible to introduce 450mm wafer handling and new lithography successfully?

According to Chilton: “This is a question best asked of the semiconductor manufacturers and equipment vendors. Our opinion is ‘very likely’.” The semiconductor manufacturers, equipment vendors, and the EDA tool providers have a long history of introducing new technology successfully when the economics of deploying the technology is favorable.

The 300nm wafer deployment was quite complex, but was completed, for example. The introduction of double patterning at 20nm is another recent example in which manufacturers, equipment vendors and EDA companies work together to deploy a new technology.

Impact of transistor variability and other physics issues
Finally, what will be the impact of transistor variability and other physics issues?

Chilton said that as transistor scaling progresses into FinFET technologies and beyond, the variability of device behavior becomes more prominent. There are several sources of device variability.

Random doping fluctuations (RDF) are a result of the statistical nature of the position and the discreteness of the electrical charge of the dopant atoms. Whereas in past technologies the effect of the dopant atoms could be treated as a continuum of charge, FinFETs are so small that the charge distribution of the dopant atoms becomes ‘lumpy’ and variable from one transistor to the next.

With the introduction of metal gates in the advanced CMOS processes, random work function fluctuations arising from the formation of finite-sized metal grains with different lattice orientations have also become important. In this effect, each metal grain in the gate, whose crystalline orientation is random, interacts with the underlying gate dielectric and silicon in a different way, with the consequence that the channel electrons no longer see a uniform gate potential.

The other key sources of variability are due to the random location of traps and the etching and lithography processes which produce slightly different dimensions in critical shapes such as fin width and gate length.

“The impact of these variability sources is evident in the output characteristics of FinFETs and circuits, and the systematic analysis of these effects has become a priority for technology development and IP design teams alike,” he added.

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”

Dr. Wally Rhines on global semiconductor industry trends for 2013

It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.

Status of global EDA industry

Dr. Wally Rhines.

First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”

For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.

Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.

In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.

DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.

Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”

According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”

“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.

Intelligent evolution of FPGAs

Vince Hu.

FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.

There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.

Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).

Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.

In addressing power/performance challenges, 20SoC is said to be the  quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC  process is the first 32Gbps transceivers that are operating in 20nm silicon.

Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate
surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.

Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.

Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.

Five-year outlook for solar PV industry!

According to Finlay Coville, VP and team leader, NPD Solarbuzz, full year end market PV demand during 2012 reached 29.05 GW. The demand is forecast to increase to 31 GW in 2013. China is expected to replace Germany as the leading market for the first time. The global market is likely to have a CAGR exceeding 15 percent, highlighting long term confidence in global PV adoption levels.

Supply vs. demand overview in 2012
The upstream c-Si module/thin-film panel suppliers produced 30.1 GW of new product in 2012. Combined with inventory levels through the value chain, this provided 31 GW of panels to the downstream channels. 29 GW was used for market demand, while 2 GW went to the downstream inventory.

Demand overview 2013
Year 2013 is shaping up as a 31 GW demand year under the most likely scenario. Over 50 percent of the end market demand is projected to come from China, Germany and North America (USA and Canada). 2013 will be a transition year for the emerging PV territories. Both the Middle East and Africa and Emerging Asia will likely reach 1 GW.

Source: NPD Solarbuzz, USA.

PV demand in 2012 accounted for approximately 30 percent of all PV installed globally. The industry growth in 2012 is positive, but set against a backdrop of an industry that had been accustomed to year-on-year growth often exceeding 100 percent. The industry is forecast to return to double digit growth.

PV scenario forecasting continies to show divergent outcomes in 2017. A high market demand scenario assumes a strong economic environment and aggressive PV policies by way of direct incentives and lower regulatory hurdles.

Five-year cumulative demand by geography
Cumulatively, global PV demand is forecast to exceed 230 GW over the five year period to 2017. China is forecast to install 51 GW accounting for over 20 percent. Europe will continue to offer strong regional PV market. North America and Japan will provide over 61 GW of demand. Emerging markets are projected to create over 25 GW of PV demand, more than 10 percent of the cumulative total to 2017.

By application segment, the ground-mount segment will remain the single largest segment over the five years. Residential and non-residential (commercial) segments will continue to be characterized by specific end-user requirements, different supply channels and routes-to-market for upstream suppliers.

The PV industry was configured to supply over 45 GW in 2012. The industry is likely to be in an over-capacity mode in 2013, with balanced supply/demand levels restored from 2015. Market share aspirations remain a key driver for PV manufacturers. During 2013 and 2014, the capacity taken offline is likely to be more than compensated for by newly ramped capacity.

With multi-domain c-Si module production, most panels had efficiencies in the 13-16 percent band during 2012. High efficiency concepts are not likely to strongly influence the module efficiency landscape during 2013 or 2014. If high efficiency cell types gain traction, the share of modules with efficiencies above 16 percent will increase.

In 2012, a wide range of efficiencies were produced, but with levels that do not compete with c-Si modules for space-constrained applications. The range of panels available in the 12-14 percent band is likely to grow strongly from 2015 as leading suppliers benefit from process improvements. Panels below 10 percent efficiency will become obsolete.

Despite end market growth expected, revenues available to each part of the value-chain will see strong declines Y/Y in 2013. This is due to the ASPs declining at a faster rate than the end-market demand growth, within a strong overcapacity environment. Revenues are also unlikely to recover for each value-chain segment until the 2016-2017 period.

What’s with prices?
2012 was the fourth year in a row that c-Si module prices declined and was the largest Y/Y decline. As capacity throughout the PV chain has increased, the oversupply has put further pressure on the ASPs. Declines in pricing occurred further upstream, at the poly, wafer and cell segments.

Tracking SAM revenues fron selling modules into downstream channels is becoming less important to the PV industry. as a number of module suppliers take on EPC and project developer roles.

PV equipment spending
As for PV equipment spending, the most likely forecast sees capacity being added by a select gtoup of tier 1 c-Si makers during 2014. The next cyclic downturn is forecast for 2016-2017. This assumes excess capacity is added in the next upturn.

If we look at the current scope of trade disputes, there are five major markets — EU, USA, India, Canada, China — investigating products being imported, with China featuring in most cases. Most disputes are being pursued by the internal bodies, but several have been referred to the WTO for review. A growing number of emerging PV regions already have domestic content incentives.

Summary
PV demand was 29 GW in 2012, and 2013 is forecast to tip 31 GW. 230 GW of new PV demand is forecast between 2013-2017, adding to the 100 GW at the end of 2012. Eighty percent of PV demand in 2013-2017 will come from the top 10 end markets.

Now, I’m on Wikipedia! ;) Thanks everyone!! :)

Today is Holi, the festival of colors. Well, it added some more color to my life as I was told that I have been listed on Wikipedia! You can see it here!

I don’t really know who has added me there, or where they are getting all of their information. All I can humbly say is: thanks a lot, very sincerely, to Wikipedia!

Wikipedia has said I’ve been staying at my Delhi residence since 1984! Well, that’s the year my father, late, Pramode Ranjan Chakraborty, bought this house. Later, in 1986, he, along with my mother, late Mrs Bina Chakraborty, moved to this house.

Why this huge gap in our buying the house and moving in? Well, not many folks know that my parents met with a near fatal accident on Jan. 27, 1986 in the early hours of the day at New Delhi. They were going home by an auto-rickshaw to our home at Greater Kailash-II, New Delhi, when an Ambassador car rammed into their auto-rickshaw full on!

That’s also the day my life changed completely! I was still a student, playing cricket with friends, when my aunt called us from Delhi. We rushed to Delhi, to find our parents badly injured! I personally had to say goodbye to cricket, and turned attention to finding work to somehow run the family! I finally moved to Delhi in Nov. 1987, and that’s where my so-called ‘professional’ life started!

It has been a great ride ever since! All the hard work done seems to have paid off. First, I must mention Gratian Vas, who took me in at Holy Faith International back in 1988. My first brush with electronics was at SBP Consultants & Engineers a year later, followed by Electronics For You. However, it was at DiSyCom magazine, under Arun Bhattacharjee, where I learned the ropes.

Later, I was hired by late Ms Rashmi Bhushan to write for electronic components magazine published by Asian Sources Media. That’s when my life changed significantly! Not only did Asian Sources Media, now, Global Sources, hire me as the full-time telecom editor  and take me to Hong Kong, it gave me first-hand view of China and how it grew in the world of electronics! It has been a fascinating journey ever since!

Thereafter, it was at Reed Elsevier, in Singapore, where I had the late Ian Shelley, Michael Tan, Paul Beh and Swee Heng Tan for company. Everywhere, I learned a lot! That’s what I continue to do even today!

The world can give me as many awards and folks can call me anything, but I shall always remain, yours truly!

Focus on SiC power electronics business 2020

SiC is implemented in several power systems and is gaining momentum and credibility.

Yole Developpement stays convinced that the most pertinent market for SiC lands in high and very high voltage (more than 1.2kV), where applications are less cost-driven and where few incumbent technologies can’t compete in performance. This transition is on its way as several device/module makers have already planned such products at short term.

Even though EV/HEV skips SiC, the industry could expand among other apps. The only question remains: Is there enough business to make so many contenders live decently? Probably, yes, as green-techs are expanding fast, strongly requesting SiC. Newcomers should carefully manage strategy and properly size capex according to the market size.

Source: Yole Developpement, France.

Power electronics industry outlook
Electronics systems were worth $122 billion in 2012, and will likely grow to $144 billion by 2020 at a CAGR of 1.9 percent. Power inverters will grow from $41 billion in 2012 to over $70 billion by 2020 at a CAGR of 7.2 percent. Semiconductor power devices (discretes and modules) will grow from $12.5 billion in 2012 to $21.9 billion by 2020 at a CAGR of 7.9 percent. Power wafers will grow $912 million in 2012 to $1.3 billion by 2020 at a CAGR of 5.6 percent.

Looking at the power electronics market in 2012 by application and the main expectations to 2015, computer and office will account for 25 percent, industry and energy 24 percent, consumer electronics 18 percent, automotive and transport 17 percent, telecom 7 percent and others 9 percent.

The main trends expected for 2013-2015 are:
* Significant increase of automotive sector following EV and HEV ramp-up.
* Renewable energies and smart-grid implementation will drive industry sector ramp-up.
* Steady erosion of consumer segment due to pressure on price (however, volumes (units) will keep on increase).

The 2011 power devices sales by region reveals that overall, Asia is still the landing-field for more than 65 percent of power products. Most of the integrators are located in China, Japan or Korea. Europe is very dynamic as well with top players in traction, grid, PV inverter, motor control, etc. Asia leads with 39 percent, followed by Japan with 27 percent, Europe with 21 percent and North America with 13 percent.

The 2011 revenues by company/headquarter locations reveals that the big-names of the power electronics industry are historically from Japan. Nine companies of the top-20 are Japanese. There are very few power manufacturers in Asia except in Japan. Europe and US are sharing four of the top five companies. Japan leads with 42 percent, followed by Europe and North America with 28 percent each, respectively, and Asia with 2 percent.

Looking at the TAM comparison for SiC (and GaN), very high voltage, high voltage of 2kV and medium voltage of 1.2kV appear as a more comfortable area for SiC. The apps are less cost-driven and SiC added value is obvious. Low voltage from 0-900V is providing strong competition with traditional silicon technologies, SJ MOSFET and GaN. There are cost-driven apps.

Xilinx targets growing ASIC and ASSP gaps

Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.

Neeraj Varma.

To find out more about how are Xilinx’s solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: “Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the VivadoTM Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.

“Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.

“Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp.”

Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?

According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.

Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.

How are the solutions going to address the challenges with ASICs and ASSPs?

He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.

Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.

ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.

PMC’s DIGI 120G supports 10G, 40G and 100G speeds for OTN transport

PMC-Sierra Inc. has launched the PM5440 DIGI 120G, said to be the industry’s only single-chip OTN processor supporting 10G, 40G and 100G speeds for OTN transport.

Elaborating, Kevin So, senior product line manager, PMC, said: “PMC is the first to integrate support for 12x10G, 3x40G or 1x100G in a single piece of silicon to address OTN transport (point-to-point), OTN aggregation (multiplexing) and OTN switching deployments. For example, with DIGI 120G, an OEM can design a line card on a P-OTP that supports 12x10G supporting per port configurable multi-service like OC-192/STM-64, 10GE, OTU2 or Fiber Channel.”

Using the same chip and same software investment, they can also design a 3x40G card supporting 40GE, OC-768/STM-256 or OTU3. Another card can be designed to support 100GE or OTU4. An OEM can design 10+ cards across multiple platforms leveraging a single R&D investment using DIGI 120G. This also translates into the lowest cost of ownership for the OEMs, while achieving a time to market advantage.

How does OTN allow for flexible aggregation and switching from 1G to 100G? For that matter, what can this device do?

OTN is a defined as a carrier grade protocol to transparently carry and switch and aggregate multi-service traffic including 1GE all the way to 100GE over a WDM. The protocol is an ITU-T standard, and supports ODU0 (which is 1G) to ODU4 (which is 100G). In addition, OTN defines something called ODUflex, which is a flexible container that can be adjusted up and down from 1G to 100G in increments of 1G.

PMC’s DIGI 120G supports all these OTN container rates and enable the ability to multiplex and switch traffic between them. In addition, DIGI 120G provides the ability to scale ODUflex to carry packet traffic ranging from 1G to 100G without service interruption. DIGI 120G is a single chip solution that uniquely enables the transponders, muxponders and line cards on ROADMs and P-OTPs.

What are the innovations done by the PM5440 DIGI 120G? What if there is some new chip coming out?

Reducing line card power and bill-of-material by more than 50 percent, PMC’s DIGI 120G stands uniquely differentiated as:
* Industry’s only single-chip solution delivering 12x10G, 3x40G or 1x100G port densities.
* Industry’s highest number of 10G ports enabling 2x higher density 10G OTN line cards.
* Industry’s highest gain 40G/100G enhanced-FEC extending optical reach by 2x vs GFEC.
* Industry’s only 120G OTN solution with OIF’s OTN-over-Packet Fabric Protocol (OFP).
* First OTN processor to enable hitless packet traffic scaling with ITU-T’s G.hao/G.7044.
* Flexible per port client-mapping of OTN, Ethernet, Storage, IP/MPLS and SONET/SDH.
* Synchronous Ethernet (SyncE), 1588v2 Precision Time Protocol (PTP), and Ethernet Link OAM (802.3ah) delivering per port Carrier Ethernet performance.

To deliver these innovations, PMC integrated well over a billion transistors. The level of silicon integration is unprecedented – requiring engineering capabilities unmatched in the telecom industry. So added that PMC worked closely with tier-1 OEM customers from the start at the requirements phase in order to tailor the solution for their systems. As a result, the DIGI 120G is a key architectural element of their system.

By when does PMC sees enterprises ‘really’ going in for products with PM5440 DIGI 120G, to support Big Data? And, what happens if they still don’t?

So noted: “We have been working with our customers for the last few months developing their line cards using DIGI 120G. We are confident they will take their products using DIGI 120G to production in 2013.”

ROADM revolution
Does PMC actually see a reconfigurable optical add-drop multiplexer (ROADM) revolution?

According to So, a couple of things are happening in the ROADM market. On the photonics side, products are now available to allow service providers to deploy very flexible wavelength switches that are color independent, direction independent, wavelength contention-free and support flexible ITU grid widths.

On the platform architecture side, we are seeing a move away from traditional muxponders and transponders line card architectures where the client ports are fixed to a specific optical uplink port (wavelength). Instead, OEMs want to de-couple the client ports from the uplink optical capacity for great flexibility and in order to achieve better bandwidth utilization especially as the industry starts deploying 100G wavelengths.

Services in the network, especially those from the metro network edge is still largely 1G or 10G rates. To achieve this flexibility, central fabrics are added to the ROADM platform to support OTN switching. PMC’s Metro OTN processor family, including our latest DIGI 120G, enable OEMs to build line cards that can switch OTN and packet simultaneously in these platform architectures.

Finaly, is the bandwidth of common modulation format for 100G and beyond too broad for ROADMs?

Kevin So concluded: “OTN, as a protocol, is designed to scale to beyond 100G. The standard bodies are already working on this now. ROADMs, as a hardware platform will scale, but new components and technologies will likely be needed to take them beyond 100G.”