I had the pleasure of interacting many times with Norman CM Lui, CEO, Skymos back in 2006. Established 1983, Skymos Electronics Ltd is one of the foremost designers and manufacturers of chip components, specializing in multilayer chip inductors, ferrite chip beads, multilayer chip ceramic capacitors, chip resistors and resistor networks. It has been awarded ISO 9001 and 9002 approval.
It was among the few suppliers offering multilayer chip inductors, ferrite chip beads, chip resistors, low-temperature co-fired ceramic capacitors (LTCC), etc.
Back then, he spoke of the applications of MLCCs that were generally in Bluetooth, GPS, cable TV equipment, satellite, etc. For example, taxis plying with GPS would need high Q (quality) MLCCs. New applications include converged handsets, MP4 players, PS3, digital cameras and video cameras; flat-panel high-definition TVs; dual-core multiprocessors (for motherboards, notebooks, desktop PCs and scanners); and automotive electronics.
Lui said most suppliers were more concerned about the 3H – high capacitance, high voltage and high frequency – for MLCCs, as well as high Q (quality factor). The frequency of MLCCs had become much higher as the termination is done on the top, instead of the sides.
Various types of dielectric were being used for MLCCs – such as the BaTiO3, NP0/C0G, XSR/X7R and Y5V/Z5U, respectively. The X5R allowed more capacitance for MLCCs and dielectric constant (K) was higher. The NP0/C0G group supported capacitance ranging from 1pF to 1µF and up to 10nF.
As for the electrodes, Pd/Ag was being used and Ni was also being used currently. For Pd/Ag electrode, the termination was in Ag/Ni/Sn. For Ni electrode, termination was mainly in Cu/Ni/Sn. Skymos is currently focusing on the Pd/Ag electrodes for MLCCs.
One major development was the use of BME (base metal electrode). Lui said that moving from the current electrode to BME would require lot of investment of about $50 million. For using BME, suppliers would need to install all new equipment, especially for the furnace, which would be used to oxidize the Ni element.
Another development has been the improvement in capacitance. Using BME for 0402, suppliers can produce MLCCs with high capacitance, such as 2.2µF, 3.3µF/6.3V, etc. Earlier, capacitance was 0.47µF using Pd/Ag electrode. The BME could enable higher capacitance due to an increase in the number of active layers.
For instance, the dielectric was 8-10 microns when using Pd/Ag electrodes. Using BME, the dielectric became 2-3 microns. The corresponding values for 0603 type is 10µF/6.3V using BME, 47µF for 0805, and 220µF for 1206. MLCCs have replaced those applications that previously required tantalum capacitors.
Another development has been the advent of the MLCC array, which has more applications in the PC industry. This array can reduce the EMI. Skymos is offering this MLCC array. It also improves the high Q, voltage and capacitance.
On the issue of MLCCs vs. ultracapacitors, Lui said, suppliers could already reach up to 220µF capacitance via MLCC, which were replacing tantalum capacitors. The tantalum capacitors were now being used for applications requiring 220µF-330µF capacitance. As a result, all other types of capacitors were dropping in demand, as compared to MLCCs. Ultracapacitors were intended to replace the Ni battery. However, there has also been a shift to oxide batteries.
The supplier’s R&D strategy includes focusing on 3H and possibly, BME. It also reduced the insulation loss and noise by grounding. The MLCC combined a capacitor and a filter. I hope Skymos has produced 20KV MLCCs. It was already offering 10KV MLCCs.
Most of this data actually appeared in Global Sources Electronics Components magazine in 2006!
Early this month, STMicroelectronics and Freescale Semiconductor introduced a new dual-core microcontroller (MCU) family aimed at functional safety applications for car electronics.
These 32-bit devices help engineers address the challenge of applying sophisticated safety concepts to comply with current and future safety standards. The dual-core MCU family also includes features that help engineers focus on application design and simplify the challenges of safety concept development and certification.
Based on the industry-leading 32-bit Power Architecture technology, the dual-core MCU family, part-numbered SPC56EL at ST and MPC564xL at Freescale, is ideal for a wide range of automotive safety applications including electric power steering for improved vehicle efficiency, active suspension for improved dynamics and ride performance, anti-lock braking systems and radar for adaptive cruise control.
The Freescale/STMicroelectronics joint development program (JDP) is headquartered in Munich, Germany, and jointly managed by ST and Freescale.
The JDP is accelerating innovation and development of products for the automotive market. The JDP is developing 32-bit Power Architecture MCUs manufactured on 90nm technology for an array of automotive applications: a) powertrain, b) body, c) chassis and safety, and d) instrument cluster.
STMicroelectronics’ SK Yue, said: “We are developing 32-bit MCUs based on 90nm Power Architecture technology. One unique feature — it allows customer to use dual core or single core operation. The objective of this MCU is to help customers simplify design and to also reduce the overall system cost.
On the JDP, he added: “We will have more products coming out over a period of time. This JDP is targeted toward automotive products.”
Commenting on the automotive market today, he said that from June onward, the industry has been witnessing a gradual sign of recovery coming in the automotive market.
Automotive market challenges
There has been an increasing integration and system complexity. These include:
* Increasing electrification of the vehicle (replacing traditional mechanical systems).
* Mounting costs pressure leading to integration of more functionality in a single ECU.
* Subsequent increase in use of high-performance sensor systems has driven increased MCU performance needs.
There are also increasing safety expectations. Automotive system manufacturers need to guarantee the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capability. Also, a move from passive to active safety is increasing the number of safety functions distributed in many ECUs.
Finally, there is a continued demand for quality — in form of zero defects, by which, a 10x quality improvement is expected.
MCU family addresses market challenges
The MCU family offers exceptional integration and performance. These include: high-end 32-bit dual-issue Power Architecture cores, combined with comprehensive peripheral set in 90nm non-volatile-memory technology. It also provides a cost effective solution by reducing board size, chip count and logistics/support costs.
It also solves functional safety. The Functional Safety architecture has been specifically designed to support IEC61508 (SIL3) and ISO26262 (ASILD) safety standards. The architecture provides redundancy checking of all computational elements to help endure the operation of safety related tasks. The unique, dual mode of operation allows customers to choose how best to address their safety requirements without compromising on performance.
The MCU also offers best-in-class quality. It is design for quality, aiming for zero defects. The test and manufacture have been aligned to lifetime warranty needs.
The MCU family addresses the challenges of applying sophisticated safety concepts to meet future safety standards. Yue added, “There are two safety standards — we are following those guidelines.” These are the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capabilities.
The automotive industry is also targeting for zero defects. “Therefore, all suppliers in tier 1 and 2 need to come up with stringent manuyfaturing and testing process that ensures zero defects,” he said.
32-bit dual-issue, dual-core MCU family
Finally, why dual core? Yue said that the MCU helps customers to achieve to achieve safety and motor control. Hence, dual core will definitely help deliver results.
“In many automotive applications, especially in safety-related applications, we want to have redundancy for safety. In the lock-step mode, two cores run the same task simultaneously, and results are then compared to each other in every computation. If the results are not matched, it indicates that there are some problems.”
This MCU family definitely simplifies design. It uses a flexible, configurable architecture that addresses both lock-step and dual parallel operation modes on a single dual-core chip. Next, it complies with safety standards.
A redundant architecture provides a compelling solution for real-time applications that require compliance with the IEC61508 SIL3 and ISO26262 ASIL-D safety standards. It also lowers the systems cost.
Dual-core architecture reduces the need for component duplication at the system level, and lowers overall system costs.
The number of MEMS and sensors going into mobile, consumer and gaming applications is expected to continue to skyrocket. As a result, OSAT and Wafer foundry players are getting more and more interest in MEMS module packaging, as volume and complexity of MEMS SiP modules is increasing dramatically, said Dr. Eric Mourier, Yole Developpement.
It implies that IDMs needs to find second source partnersand qualify some OSATs in order to secure their supply chain. Also, standardization(coming from both foundries, OSAT, WLP houses or substrate suppliers) is critical and necessary to implement in order to keep the packaging, assembly, and test cost of MEMS modules under control. There are many different players with different designs, and it’s not likely we’ll see one solution adopted by all the players.
As for wafer-level packaging (WLP) for LEDs, WLP has not been strongly deployed in the LED industry due to associated technical challenges. In the short-term, there is ESD integration in Si substrate. In the long-term, LED drivers could be integrated at the package level for Intelligent lighting. Ultimately, there are wafer-to-wafer manufacturing schemes for certain packaget types.
Real production of HB-LEDs with a mixed approach of WLP+through silicon vias (TSV) is just starting. There are some Taiwanese players such as TSMC, Xintec, Visera, Touch MicroTech and Sibdi, and South Korea-based LG Innotek. Additional players in the semiconductor and MEMS industry are seeking to enter the field.
What exactly is smart energy profile (SEP 2) IP-based energy management for the home? Introducing the SEP 2, Tobin Richardson, chairman and CEO, ZigBee Alliance said ZigBee smart energy is the standard of choice for home area networks (HANs).
About 40+ million ZigBee electric meters are being deployed. ZigBee smart energy is being enhanced by network/communications options, support for forward-looking developments, etc. SEP 2 is a joint effort with the HomePlug Alliance. There is a vision of MAC/PHY agnostic SmartEnergy profile.
Robby Simpson, SEP 2 Technical Working Group Chair, system architect, GE Digital Energy, provided the features and benefits of Smart Energy. Features include price communication, demand response and load control, energy usage information/metering data, prepayment metering, text messaging, plug-in electric vehicles, distributed energy resources, billing communication, etc.
Example applications are many, such as smartphones, ESI in the sky, tablets, TVs, plug-in electric vehicles, PCs, solar inverters, thermostats, energy management systems, smart meters, building management systems, smart appliances, etc. There is support for a variety of architectures. The use of IP eases convergence and architecture changes. A consortium for SEP 2 interoperability (CSEP) has been established.
Skip Ashton, ZigBee Arch. review committee chair, senior apps director, Silicon Labs said implementations of SEP 2 are available from a number of companies and across several MAC/PHYs. All standard documents are available for review.
Jeff Gooding, Southern California Edison (SCE), spoke about creating SEP 2 energy ecosysyems. SEP 2 can bridge multi-platform customer technologies to create a rich ecosystem. SEP 2 customer focused solutions can allow the utilities and energy service providers to use any customer communication channel. SEP 2 pilots at SCE include a gateway pilot and a smart charging pilot. Both are separate pilots.
According to Stephen Day, VP of Technology, Coto Technology has the number 1 share in reed relays and relay products. The Coto brand is associated with the broadest portfolio, best in class quality, dedicated technical support, and a provider of innovative solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.
Coto has announced the RedRock, a new MEMS based magnetically operated switch. The RS-A-2515 is the world’s smallest wafer level packaged magnetically operated reed switch. It consumes zero power, measures 2mm3 in footprint and switches at less than 0.3W. It delivers high reliability and surface mount package.
The small footprint means use of less PCB real estate, no operate power means a longer battery life. The low switching power leads to higher reliability. The high directionality leads to resistance to stray fields. Hot switchable feature leads to higher reliability.
Together, Coto has managed to combine the best of two worlds — traditional reed switches with MEMS processing. There is high aspect ratio microfabrication (HARM). This is the first commercially available switch. It produces structures that generate strong contact closure forces. The forces are many times greater than the previous MEMS based magnetic switches. It also enables hot switching up to several hundred milliwatts.
HARM is the key to making it all possible. The benefits are many, from temperature rise vs. carry current, to RedRock contact life test, 1V 1 mA hot-switched load. RedRock allows for small size, zero power consumption and high power switching.
At the moment, Coto is leveraging RedRock into high growth applications. In the future, Coto will integrate sensor solution as well. RedRock’s unique combination of features include reed — no power and high current, and MEMS — no power and small size, as well as GMR/Hall — small size and high current — to deliver the RedRock, which features no power, small size and high current.
Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.
How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.
Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.
The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.
IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.
Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.
The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.
QuickLogic is a Silicon Valley-based fabless semiconductor company. It is an innovator of CSSPs or customer-specific standard products. It is focused on high-growth mobile markets such as consumer, enterprise and mobile enterprise.
Speaking at the ongoing 13th Global Electronics Summit in Santa Cruz, USA, Andy Pease president and CEO, QuickLogic, said it does all the drivers that actually need to be inside all the application processors. It is trying to solve the OEM dilemma for mobile market. There are the Android + ARM camp and the Windows + x86 camp, respectively. One way to solve the problem is to do software overlay to Android/Windows.
CSSPs enables the OEM hardware differentiation. It allows fastest time-to-market for custom silicon. It also extends the battery life. The reference designs showcases proven system blocks and capabilities. It is a known good starting point for CSSP development.
The application development dilemma includes optimizing for the specific vertical vs. horizontal markets. When does the integration happen for new standards? Also, how long does a company need to keep mature standards?
QuickLogic has inrtroduced catalog CSSPs. These are ready-to-integrate solutions. They are architectured, developed and verified with application processor vendors.
Platform diversity enables solutions 100 percent programmable for ultimate flexibility. Hybrid programmable/ASIC is provided for common applications requiring some customization. The go-to-market strategy includes complete solutions. It includes software drivers, firmware and application reference codes. It is a collaborative customer model.
A partner challenge could be to re-position its existing AP in new, adjacent markets and applications. QuickLogic’s solution is to provide custom design and software drivers to bridge the AP with camera interface to different types of image capture devices.
Another example is in SD memory. The premier challenge is to adapt the existing baseband processor to emerging market requirements. QuickLogic’s solution is to develop multiple custom designs and software drivers to bridge the baseband with SD memory.
Catalog CSSPs emable the OEM engineers expanded functionality beyond the application processor’s native capability. They expand the served available market of application/embedded processor companies. It scales QuickLogic’s resources across multiple end markets, applications and customers.
FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.
There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.
Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).
Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.
In addressing power/performance challenges, 20SoC is said to be the quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC process is the first 32Gbps transceivers that are operating in 20nm silicon.
Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate
surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.
Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.
Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.
Cavendish Kinetics is well known for its combined experience in MEMS, RF system design and CMOS design. Since 2008, it has focused on developing digital variable capacitors to improve wireless connectivity and data rates for mobile phones.
According to Dennis Yost, president & CEO, Cavendish Kinetics, 4G/LTE mobile devices are not yet achieving their potential. Antenna frequency tuning is an essential technology. Only metal MEMS technology has the size and performance. He was speaking at the ongoing Globalpress Electronics Summit 2013 in Santa Cruz, USA.
Cavendish claims to have the team, proven technology and real demonstrated performance. There is IP and patent protection for customers. Cavendish also owns the process.
The future of cell phone radio is needed in order to meet the performance gap. In future, you will see adaptive power amplifiers.
Antenna frequency tuning used in traditional RF applications. How do you ensure there is no loss in the component? Only MEMS has the performance and size for cell phones. Metal MEMS has almost no series resistance. No switches are required.
Previous designs required switches and different loads. Mechanical capacitors change capacitance value by moving plates – changing the area or plate distance changes the capacitance. MEMS capacitors do the same at the micrometer level.
Users can control design and manufacturing process of devices. How a MEMS is built is just as important as what you build. Success requires MEMS design expertise, MEMS process expertise and MEMS volume production expertise.
Cavendish has MEMS experts in all areas. It developed and owned MEMS manufacturing process. It uses all standard CMOS foundry technology. Innovations have so far yielded over 100 patents in manufacturing process and MEMS design.
By using the NanoMech technology performance, Cavendish Kinectics has demonstrated excellent performance in a small chip.
According to Prof. Yi Cui, Dept. of Materials, Science & Engineering, Stanford University, nanometer is an enabling technology. We can do applications such as electronics, energy, environment and health. Some examples are high energy batteries, printed energy storage devices on paper, textile and sponge, etc. He was delivering the inaugural address at the Globalpress Electronics Summit 2013, being held in Santa Cruz, USA.
High energy battery has portable and stationary applications. In portable, energy density, cost and safety are important. In stationary, cost, power, energy efficiency and ultra-long life are important. The standard is 500 cycles at 80 percent. One of the challenges of silicon anodes is that Si has 4200 mAh/g of silicon, 10 times more than carbon.
Nanowires can offer shorter distance for Li diffusion (high power), good strain release and interface control (for better cycle life), and continuous electron transport pathway (high power). In-situ transmission electron microscopy (TEM). Double walled hollow structure provides stable solid electrolyte interphase (SEI). The outer surface is static. Amprius, where Prof. Cui is CTO, is a $6 million US government funded enterprise. Amprius China started in Nanjing, in April 2012.
Another example is printed energy storage devices on paper, textile and sponge. For low-cost scaffold, paper, textile and sponge, are used. There is cellulose paper and synthetic textile, besides sponge, as well.
There can be transparent batteries. It is actually very hard to develop those. The challenges for making a transparent battery are Al film, cathode, electrolyte, etc. An idea: dimension smaller than eye’s detection limit (50-100 um). Also, grids are well aligned.
Transparent conducting electrodes provide electrical and allow light to pass through. Apps include solar cells, etc. Indium tin oxide (ITO) has a low abundance of indium, brittleness when bent, and sputtering at high cost. Electrospinning of nanofibers is done for transparent electrodes. An example is the trough-shaped nanowires.
Yet another example is the water nanofilters for killing pathogens. The processes available for killing bacteria include chemical disinfection, UV disinfection, boiling, etc.
The first generation product is currently ready at Amprius. Amprius licensed the IP from Stanford. Stanford is also an investor in Amprius.