I had the pleasure of interacting many times with Norman CM Lui, CEO, Skymos back in 2006. Established 1983, Skymos Electronics Ltd is one of the foremost designers and manufacturers of chip components, specializing in multilayer chip inductors, ferrite chip beads, multilayer chip ceramic capacitors, chip resistors and resistor networks. It has been awarded ISO 9001 and 9002 approval.
It was among the few suppliers offering multilayer chip inductors, ferrite chip beads, chip resistors, low-temperature co-fired ceramic capacitors (LTCC), etc.
Back then, he spoke of the applications of MLCCs that were generally in Bluetooth, GPS, cable TV equipment, satellite, etc. For example, taxis plying with GPS would need high Q (quality) MLCCs. New applications include converged handsets, MP4 players, PS3, digital cameras and video cameras; flat-panel high-definition TVs; dual-core multiprocessors (for motherboards, notebooks, desktop PCs and scanners); and automotive electronics.
Lui said most suppliers were more concerned about the 3H – high capacitance, high voltage and high frequency – for MLCCs, as well as high Q (quality factor). The frequency of MLCCs had become much higher as the termination is done on the top, instead of the sides.
Various types of dielectric were being used for MLCCs – such as the BaTiO3, NP0/C0G, XSR/X7R and Y5V/Z5U, respectively. The X5R allowed more capacitance for MLCCs and dielectric constant (K) was higher. The NP0/C0G group supported capacitance ranging from 1pF to 1µF and up to 10nF.
As for the electrodes, Pd/Ag was being used and Ni was also being used currently. For Pd/Ag electrode, the termination was in Ag/Ni/Sn. For Ni electrode, termination was mainly in Cu/Ni/Sn. Skymos is currently focusing on the Pd/Ag electrodes for MLCCs.
One major development was the use of BME (base metal electrode). Lui said that moving from the current electrode to BME would require lot of investment of about $50 million. For using BME, suppliers would need to install all new equipment, especially for the furnace, which would be used to oxidize the Ni element.
Another development has been the improvement in capacitance. Using BME for 0402, suppliers can produce MLCCs with high capacitance, such as 2.2µF, 3.3µF/6.3V, etc. Earlier, capacitance was 0.47µF using Pd/Ag electrode. The BME could enable higher capacitance due to an increase in the number of active layers.
For instance, the dielectric was 8-10 microns when using Pd/Ag electrodes. Using BME, the dielectric became 2-3 microns. The corresponding values for 0603 type is 10µF/6.3V using BME, 47µF for 0805, and 220µF for 1206. MLCCs have replaced those applications that previously required tantalum capacitors.
Another development has been the advent of the MLCC array, which has more applications in the PC industry. This array can reduce the EMI. Skymos is offering this MLCC array. It also improves the high Q, voltage and capacitance.
On the issue of MLCCs vs. ultracapacitors, Lui said, suppliers could already reach up to 220µF capacitance via MLCC, which were replacing tantalum capacitors. The tantalum capacitors were now being used for applications requiring 220µF-330µF capacitance. As a result, all other types of capacitors were dropping in demand, as compared to MLCCs. Ultracapacitors were intended to replace the Ni battery. However, there has also been a shift to oxide batteries.
The supplier’s R&D strategy includes focusing on 3H and possibly, BME. It also reduced the insulation loss and noise by grounding. The MLCC combined a capacitor and a filter. I hope Skymos has produced 20KV MLCCs. It was already offering 10KV MLCCs.
Most of this data actually appeared in Global Sources Electronics Components magazine in 2006!
Early this month, STMicroelectronics and Freescale Semiconductor introduced a new dual-core microcontroller (MCU) family aimed at functional safety applications for car electronics.
These 32-bit devices help engineers address the challenge of applying sophisticated safety concepts to comply with current and future safety standards. The dual-core MCU family also includes features that help engineers focus on application design and simplify the challenges of safety concept development and certification.
Based on the industry-leading 32-bit Power Architecture technology, the dual-core MCU family, part-numbered SPC56EL at ST and MPC564xL at Freescale, is ideal for a wide range of automotive safety applications including electric power steering for improved vehicle efficiency, active suspension for improved dynamics and ride performance, anti-lock braking systems and radar for adaptive cruise control.
The Freescale/STMicroelectronics joint development program (JDP) is headquartered in Munich, Germany, and jointly managed by ST and Freescale.
The JDP is accelerating innovation and development of products for the automotive market. The JDP is developing 32-bit Power Architecture MCUs manufactured on 90nm technology for an array of automotive applications: a) powertrain, b) body, c) chassis and safety, and d) instrument cluster.
STMicroelectronics’ SK Yue, said: “We are developing 32-bit MCUs based on 90nm Power Architecture technology. One unique feature — it allows customer to use dual core or single core operation. The objective of this MCU is to help customers simplify design and to also reduce the overall system cost.
On the JDP, he added: “We will have more products coming out over a period of time. This JDP is targeted toward automotive products.”
Commenting on the automotive market today, he said that from June onward, the industry has been witnessing a gradual sign of recovery coming in the automotive market.
Automotive market challenges
There has been an increasing integration and system complexity. These include:
* Increasing electrification of the vehicle (replacing traditional mechanical systems).
* Mounting costs pressure leading to integration of more functionality in a single ECU.
* Subsequent increase in use of high-performance sensor systems has driven increased MCU performance needs.
There are also increasing safety expectations. Automotive system manufacturers need to guarantee the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capability. Also, a move from passive to active safety is increasing the number of safety functions distributed in many ECUs.
Finally, there is a continued demand for quality — in form of zero defects, by which, a 10x quality improvement is expected.
MCU family addresses market challenges
The MCU family offers exceptional integration and performance. These include: high-end 32-bit dual-issue Power Architecture cores, combined with comprehensive peripheral set in 90nm non-volatile-memory technology. It also provides a cost effective solution by reducing board size, chip count and logistics/support costs.
It also solves functional safety. The Functional Safety architecture has been specifically designed to support IEC61508 (SIL3) and ISO26262 (ASILD) safety standards. The architecture provides redundancy checking of all computational elements to help endure the operation of safety related tasks. The unique, dual mode of operation allows customers to choose how best to address their safety requirements without compromising on performance.
The MCU also offers best-in-class quality. It is design for quality, aiming for zero defects. The test and manufacture have been aligned to lifetime warranty needs.
The MCU family addresses the challenges of applying sophisticated safety concepts to meet future safety standards. Yue added, “There are two safety standards — we are following those guidelines.” These are the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capabilities.
The automotive industry is also targeting for zero defects. “Therefore, all suppliers in tier 1 and 2 need to come up with stringent manuyfaturing and testing process that ensures zero defects,” he said.
32-bit dual-issue, dual-core MCU family
Finally, why dual core? Yue said that the MCU helps customers to achieve to achieve safety and motor control. Hence, dual core will definitely help deliver results.
“In many automotive applications, especially in safety-related applications, we want to have redundancy for safety. In the lock-step mode, two cores run the same task simultaneously, and results are then compared to each other in every computation. If the results are not matched, it indicates that there are some problems.”
This MCU family definitely simplifies design. It uses a flexible, configurable architecture that addresses both lock-step and dual parallel operation modes on a single dual-core chip. Next, it complies with safety standards.
A redundant architecture provides a compelling solution for real-time applications that require compliance with the IEC61508 SIL3 and ISO26262 ASIL-D safety standards. It also lowers the systems cost.
Dual-core architecture reduces the need for component duplication at the system level, and lowers overall system costs.
At the recently held Semicon West 2014, Daniel P. Tracy, senior director, Industry Research and Statistics, SEMI, presented on SEMI Materials Outlook. He estimated that semiconductor materials will see unit growth of 6 percent or more. There may be low revenue growth in a large number of segments due to the pricing pressures and change in material.
For semiconductor eequipment, he estimated ~20 percent growth this year, following two years of spending decline. It is currently estimated at ~11 percent spending growth in 2015.
Overall, the year to date estimate is positive growth vs. same period 2013, for units and materials shipments, and for equipment billings.
For equipment outlook, it is pointing to ~18 percent growth in equipment for 2014. Total equipment orders are up ~17 percent year-to-date.
For wafer fab materials outlook, the silicon area monthly shipments are at an all-time high for the moment. Lithography process chemicals saw -7 percent sales decline in 2013. The 2014 outlook is downward pressure on ASPs for some chemicals. 193nm resists are approaching $600 million. ARC has been growing 5-7 percent, respectively.
For packaging materials, the Flip Chip growth drivers are a flip chip growth of ~25 percent from 2012 to 2017 in units. There are trends toward copper pillar and micro bumps for TSV. Future flip chip growth in wireless products are driven by form factor and performance. BB and AP processors are also moving to flip chip.
There has been growth in WLP shipments. Major applications for WLP are driven by mobile products such as smartphones and tablets. It should grow at a CAGR of ~11 percent in units (2012-2017).
Solder balls were $280 million market in 2013. Shipments of lead-free solder balls continues to increase. Underfillls were $208 million in 2013. It includes underfills for flip chip and packages. The increased use of underfills for CSPs and WLPs are likely to pass the drop test in high-end mobile devices.
Wafer-level dielectrics were $94 million market in 2013. Materials and structures are likely to enhance board-level reliability performance.
Die-attach materials has over a dozen suppliers. Hitachi Chemical and Henkel account for major share of total die attach market. New players are continuing to emerge in China and Korea. Stacked-die CSP package applications have been increasing. Industry acceptance of film (flow)-over-wire (FOW) and dicing die attach film (DDF) technologies are also happening.
At Semicon West 2014, Bob Johnson, VP Research, Gartner, presented the Semiconductor Capital Spending Outlook at the SEMI/Gartner Market Symposium on July 7.
First, a look at the semiconductor revenue forecast: it is likely to grow at a 4.3 percent CAGR from 2013-2018. Logic continues to dominate, but growth falters. As per the 2013-2018 CAGRs, logic will be growing 3.5 percent, memory at 4.5 percent, and other at 6.3 percent.
As for the memory forecast, NAND should surpass DRAM. At 2013-2018 CAGRs, DRAM should grow -1.1 percent, while NAND should grow 10.8 percent. Smartphone, SSD and Ultramobile are the applications driving growth through 2018. SSDs are powering the NAND market.
Among ultramobiles, tablets should dominate through 2018. They should also take share from PCs. Next, smartphones have been dominating mobile phones.
Looking at the critical markets for capital investment, smartphones are the largest growth segment, but have been showing signs of saturation. The revenue growth could slow dramatically by 2018. Ultramobiles have the highest overall CAGR, but at the expense of PC market. Tablets are driving down semiconductor content. Desktop and notebook PCs are a large, but declining market. This also requires critical revenue to fund logic capex. Lastly, SSDs are driving NAND Flash growth. The move to data centers is driving sustainable growth.
In capital spending, memory is strong, but logic is weak through 2018. The 2014 spending is up 7.1 percent, driven by strong memory market. Strength in NAND spending will drive future growth. Note that memory oversupply in 2016 can create next cycle. NAND is the capex growth driver in memory spending.
The major semiconductor markets, which justify investment in logic leading edge capacity, are now running out of gas. Ultramobiles are cannibalizing PCs, smartphones are saturating and both are moving to lower cost alternatives. It is increasingly difficult to manufacture complex SoCs successfully at the absolute leading edge. Moore’s Law is slowing down, while costs are going up. Breakthrough technologies (i.e., EUV) are not ready when needed. Much of the intelligence of future applications is moving to the cloud. The data centers’ needs for fast, low power storage solutions are creating sustainable growth for NAND Flash.
The traditional two-year per node pace of Moore’s Law will continue to slow down. Only a few high volume/high performance applications will be able to justify the costs of 20nm and beyond. Whether this will require new or upgraded capacity is uncertain. 28nm will be a long lived node as mid-range mobility products demand higher levels of performance. Finally, the cloud will continue to grow in size and influence creating demand for new NAND Flash capacity and technology.
What does the future hold for MEMS? How can the MEMS indistry stay profitable and innovative in the next five years? The MEMS market is still in a dynamic growth with an estimated 12.3 percent CAGR over 2013-2019 in $US value, growing from $11.7 billion in 2013 to $24 billion in 2019.
This growth, principally driven by a huge expansion of consumer products, is mitigated by two main factors. First, due to a fierce competition based on pricing, the ASPs are continuously decreasing.
Second, innovation is slow and incremental, as no new devices have been successfully introduced on the market since 2003. Fierce competition based on pricing in now ongoing putting thus extreme pressure on device manufacturers.
Some trends are still impacting MEMS business. These are:
* Decrease of price in consumer electronics; ASP of MEMS microphones.
* Component size is still decreasing.
However, successful companies are still large leaders in distinct MEMS categories, such as STMicroelectronics, Knowles, etc. But maintaining growth in consumer electronic applications remains a challenge.
The market for motion sensor in cell phones and tablets is large and continuously expanding. Discrete sensors still decline, but will still be used in some platforms (OIS function for gyros). Next, 6- and 9-axis combos should grow rapidly. Because of strong price pressure and high adoption rate, the total market will stabilize from 2015.
STMicroelectronics, InvenSense and Bosch are still leaders in 3-axis gyros and 6-axis IMUs. It seems difficult for new players to compete and be profitable in this market. The automotive, industrial and medical applications of MEMS are driving growth of MEMS business. MEMS for automotive will grow from $2.6 billion in 2012 to $3.6 billion in 2018 with 5 percent CAGR.
MEMS industry is big and growing. Strong market pull observed for sensors and actuators in cell phones, automotive, medical, industrial.
• Not limited to few devices. A new wave of MEMS is coming!
• Component and die size are still being optimized while combo approaches become mainstream. And several disruptive technology approaches are now in development to keep going in term of size and price decrease.
• But the MEMS industry has not solved a critical issue: how to increase the chance of new devices to enter the market?
–RF switch, autofocus, energy harvesting devices, fuel cells… are example of devices still under development after over 10 years of effort.
–How to help companies to go faster and safer on the market with new devices?
The mass adoption of GaN on Si technology for LED applications remains uncertain. Opinions regarding the chance of success for LED-On-Si vary widely in the LED industry from unconditional enthusiasm to unjustified skepticism. Although significant improvements have been achieved, there are still some technology hurdles (such as performance, yields, CMOS compatibility, etc.).
The differential in substrate cost itself is not enough to justify the transition to GaN on Si technology. The main driver lies in the ability to manufacture in existing, depreciated CMOS fabs in 6” or 8”. For Yole Développement, if technology hurdles are cleared, GaN-on-Si LEDs will be adopted by some LED makers, but it will not become an industry standard.
Yole is more optimistic about the adoption of GaN on Si technology for power GaN devices. Contrary to LED industry, where GaN on Sapphire technology is the main stream and presents a challenging target, GaN on Si will dominate the GaN based power electronics applications. Although the GaN based devices remain more expensive than Si based devices, the overall cost of GaN device for some applications are expected to be lower three years from now according to some manufacturers.
In 2020, GaN could reach more than 7 percent of the overall power device market and GaN on Si will capture more than 1.5 percent of the overall power substrate volume, representing more than 50 percent of the overall GaN on Si wafer volume, subjecting to the hypothesis that the 600 V devices would take off in 2014-2015.
GaN targets a $15 billion served available device market. GaN can power 4 families of devices and related applications. These are blue and green laser diodes, LEDs, power electronics and RF (see image).
Regarding GaN-on-Si LED, there will be no more than 5 percent penetration by 2020. As for GaN-on-GaN, it will be less than 2 percent. Yole considers that the leading proponents of LED-On-Si will successful and eventually adopt Si for all their manufacturing. Those include Bridgelux/Toshiba, Lattice Power, TSMC and Samsung. It expects that Silicon will capture 4.4 percent of LED manufacturing by 2020.
GaN wafer could break through the $2000 per 4” wafer barrier by 2017 or 2018, enabling limited adoption in applications that require high lumen output other small surfaces.
Engineers designing FPGA applications face many challenges. Using Plunify’s automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.
Kirvy Teo said: What happens when you need to close timing in FPGA design and still can’t get it to work? Here is a new way to solve that problem – machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending “strategies”. Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.
One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can’t run seeds on a design with bad timing scores.
However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!
How has Plunify been doing this year so far? According to Teo, Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them “BCC” – Big Chinese Corporations.
Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.
Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.
What’s the future path likely to be? Teo added: “Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.
“First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!
“As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don’t know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.
Why would FPGA providers take up the solution?
The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about “Getting better results without touching your RTL code!”
Renesas Electronics recently opened its India subsidiary in Bangalore. Elaborating, Sunil Dhar, managing director of Renesas Electronics India said: “We are glad to announce the opening of Renesas Electronics India Pvt Ltd, a wholly-owned subsidiary of Renesas Electronics Singapore Pte Ltd., located in Bangalore.
“Since 2010, Renesas has been providing technical product support to its customers here via branch offices in Bangalore, Delhi and Mumbai. As part of its expansion plan, Renesas will turn our said branches into a full subsidiary.
“The branch office setup served us well when the organization was small and its role was limited. In order to expand further in terms of opening more offices in India for close customer support, and to be able to provide wider services to customers in India like reference software, hardware, reference solutions which would be developed in India, it would require us to have a permanent establishment here.
“Through this new company, we aim to expand business by providing the best solution offerings and technical support as well as a regional systems solution development expertise to the Indian market.”
How does the India R&D team play a role in global innovation and where do you see Renesas Electronics in India five years from now?
He said that over 50 percent of the Renesas India team is application development or field engineers armed with knowledge of embedded hardware and software development and support.
In order to expand the footprint in Indian markets, Renesas plans to build up a strong application engineering team. India Application engineering team will engage with the Renesas headquarters, regional offices to develop new products and solutions dedicated for emerging countries, including India.
The application engineering team and the future solution centre aim to survey the market for solution needs, prepare India designed solutions fitting the price points and specifications points as required in the Indian market. Along with the customers, the team also intends to collaborate with the design houses to create innovative solutions addressing upcoming needs of the market. Our goal is to become the most trusted semiconductor solution provider in India.
What are the India-centric solutions that would be developed from the India Application Engineering team?
Dhar added that the needs of emerging markets are usually different in both specifications as well as price points. By providing dedicated local support via the new company, and with a focus on industrial and automotive applications for two- and four-wheelers, Renesas aims to increase its MCU share in India and expand its solution offerings with rich lineup of kit solutions (MCU + SoC + power devices) and platform reference boards (boards with complete ecosystem including devices and software) to provide customers a shorter time-to-market.
The team will initially focus on automotive and particularly, two-wheeler solutions. The intention is to expand the scope of the application engineering team’s activity to industrial and consumer appliances in near term.
What is the overall India employee strength? How are the investment plans looking up?
Dhar said: “In order to expand our footprint in Indian markets, we will double our headcount in near term. Currently, we are just under 30 staff and over 50 percent of us are application development or field engineers armed with the knowledge of embedded hardware and software development and support. Upon setting up the organization in Sales and Marketing roles in the initial days, we also have plans to announce the setting up of a Solutions Centre in India to develop reference application solutions to enable our customers to use our devices.
“We are intending to invest in lab, infrastructure setup and expansion of activities in the next three to five years. Additionally, we are also considering investing towards 3rd party and IDH for enlarged business engagement.”
Trends driving automotive market in India
Regarding trends driving the automotive market in India, Dhar said that Renesas focusses on three business segments – automotive, industrial and home, OA and ICT. Renesas holds more than 40 percent global market share for automotive MCU business. Our target applications for automotive segment are automotive control and automotive infotainment and network.
Renesas has dedication applications solutions for integrated cockpit through system on chip, R-car ecosystem collaboration solution for e-mobility and automotive analog and power devices for driving, steering and braking.
As semiconductor technologies evolved, it has enabled automakers to integrate multiple applications on a single chip significantly reducing the board area; thus optimizing performance and adding new features for comfort, safety and infotainment. Power technologies have brought energy efficiency, limiting power consumption in vehicles. Advancements in process technologies will continue to drive the auto industry in the coming years.
Renesas, for instance, developed the industry’s first 28nm flash memory IP for MCUs and the first semiconductor supplier to move from 40nm to 28nm process technology.
“Trends driving auto industry in India and globally are more of less the same. However, for India market, we see a specific demand for two-wheeler solutions and that is our target in coming years,” he concluded.
Lastly, I must take the opportunity to thank Ms Shweta Dhadiwal-Baid and Ms Sharmita Mandal for making this happen! ;)
Are we at an inflection point in verification today? Delivering the guest keynote at the UVM 1.2 day, Vikas Gautam, senior director, Verification Group, Synopsys, said that today, mobile and the Internet of Things are driving growth. Naturally, the SoCs are becoming even more complex. It is also opening up new verification challenges, such as power efficiency, more software, and reducing time-to-market. There is a need to shift-left to be able to meet time-to-market goal.
The goal is to complete your verification as early as possible. There have been breakthrough verification innovations. System Verilog brought in a single language. Every 10-15 years, there has been a need to upgrade verification.
Today, many verification technologies are needed. There is a growing demand for smarter verification. There is need for much upfront verification planning. There is an automated setup and re-use with VIP. There is a need to deploy new technologies and different debug environments. The current flows are limitimg smart verification. There are disjointed environments with many tools and vendors.
Synopsys has introduced the Verification Compiler. You get access to each required technology, as well as next-gen technology. These technologies are natively integrated. All of this enables 3X verification productivity.
Regarding next gen static and formal platforms, there will be capacity and performance for SoCs. It should be compatible with implementation products and flows. There is a comprehensive set of applications. The NLP+X-Prop can help find tough wake-up bug at RTL. Simulation is tuned for the VIP. There is a ~50 percent runtime improvement.
System Verilog has brought in many new changes. Now, we have the Verification Compiler. Verdi is an open platform. It offers VIA – a platform for customizing Verdi. VIA improves the debug efficiency.
Here is the concluding part of my discussion with Sam Fuller, CTO, Analog Devices. We discussed the technology aspects of Moore’s Law and
‘More than Moore’, among other things.
Are we at the end of Moore’s Law?
First, I asked Fuller that as Gordon Moore suggested – are we about to reach the end of Moore’s Law? What will it mean for personal computing?
Fuller replied: “There is definitely still life left in Moore’s law, but we’re leaving the golden age after the wonderful ride that we have had for the last 40 years. We will continue to make chips denser, but it is becoming difficult to continue to improve the performance as well as lower the power and cost.
“Therefore, as Moore’s law goes forward, more innovation is required with each new generation. As we move from Planer CMOS to FinFET (a new technology for multi-gate architecture of transistors); from silicon to more advanced materials Moore’s law will still have life for the next decade, but we are definitely moving into its final stages.
“For personal computing, there is still a lot of innovation left before we begin to run out of ideas. There will continue to be great advances in smart phones, mobile computing and tablets because software applications are really just beginning to take advantage of the phenomenal power and capacity of today’s semiconductors. The whole concept of ‘Internet of things’ will also throw up plenty of new opportunities.
“As we put more and more sensors in our personal gadgets, in factories, in industries, in infrastructures, in hospitals, and in homes and in vehicles, it will open up a completely new set of applications. The huge amount of data generated out of these sensors and wirelessly connected to the Internet will feed into the big data and analytics. This would create a plethora of application innovations.”
What’s happening in the plane?
The plane opportunity – 90nm – 65nm – 45nm – 22nm – 20nm – 14/18nm – is starting to get difficult and probably won’t work at 12nm, for purely physics reasons. What is Analog Devices’ take on this?
Fuller said: “You are right! We have been going from 45 nm down to lower nodes, it’ll probably go down to 10 nm, but we are beginning to run into some fundamental physics issues here. After all, it’s a relatively finite number of atoms that make up the channels in these transistors. So, you’re going to have to look at innovations beyond simply going down to finer dimensions.
“There are FinFETS and other ways that can help move you into the third dimension. We’re getting to a point where we can put a lot of complexity and a number of functions on a single die. We have moved beyond purely digital design to having more analog and mixed signal components in the same chip. There are also options such as stacked dies and multiple dies.
“Beyond integration on a single chip, Analog Devices leads in advanced packaging technologies for System in a Package (SiP) where sensors, digital and analog/mixed signal components are all in a single package as the individual components would typically use different technology nodes and it might not be practical to do such integration on a single die.
“So, the challenge often gets described as “More than Moore”, which is going beyond Moore’s law, bringing those capabilities to do analog processing as well as digital and then integrating sensors for temperature sensing, pressure sensing, motion sensing and a whole range of sensors integrated for enabling the ‘Internet of Things’.
“At Analog Devices, we have the capability in analog as well as digital, and having worked for over 20 years on MEMS devices, we are particularly well positioned as we get into ‘More than Moore’.”