Search Results

Keyword: ‘bit’

Synopsys acquires Magma! And, another one bites the dust!!

December 1, 2011 4 comments

Wow! Yesterday, Synopsys signed a definitive agreement to acquire Magma Design Automation Inc. This news is interesting, and not surprising. This acquisition seemed to be on the cards, but at least, not so soon. Nevertheless!

So, that leaves Synopsys, Cadence and Mentor Graphics as the big three EDA vendors, now that Magma has been acquired.

Just a couple of months back, I was in discussion with Rajeev Madhavan, chairman and CEO, Magma, regarding Silicon One technology solutions on the sidelines of MUSIC India. Magma had outlined five technologies: Talus, Tekton, Titan, FineSim and Excalibur and expected to have the opportunity to be a dominant yield management company.

Where has all of this gone, one wonders! It can safely be assumed that the Silicon One series can very well go on, now under the guidance of Synopsys.  However, it will only add up to boosting the revenues of Synopsys in the long run.

Some time ago, one thought that the EDA industry was having four big players. Now, there are three. In between, there was news such as Cadence trying to acquire Mentor Graphics, which did not happen. Even Magma seemed to be doing fine, at least, till 2006-07.

Thereafter, it has been a slightly different story, with not only the CEO leaving Magma India, and some changes in the Indian management team, as well as certain MUSIC India events with less attendances, and so on. One can accept these as the part and parcel for any industry/organization.

On Magma’s website, there is a statement from Madhavan, which says: “Magma and Synopsys have always shared a common goal of enabling chip designers to improve performance, area and power while reducing turnaround time and costs on complex ICs,” said Rajeev Madhavan, CEO of Magma. “By joining forces now we can ensure that chip designers have access to the advanced technology they need for silicon success at 28, 20 nanometer and below.”

All the best to both Synopsys and Magma!

Solarcon India 2011 begins with record exhibitors

November 9, 2011 2 comments

Presenting the excerpts from the welcome address by Debasish Paul Choudhury, president, SEMI India, at the ongoing Solarcon India 2011, being held in Hyderabad.

This year’s show features a larger exhibition, a three-day dual track conference, and will feature three concurrent technical programs. The theme for this year’s exposition, representing the widening solar value chain in India, is “Showcasing the Solar Eco‐System: From Polysilicon to Power Plants.”

Solarcon India 2011 opens in Hyderabad, India.

Solarcon India 2011 opens in Hyderabad.

The exhibition with over 115 exhibitors from eight countries, compared to 81 exhibitors in SOLARCON India 2010, covers the entire solar value chain, will provide you an opportunity to see a wide range of new products and services offered by Indian and international companies, under one roof.

This year’s show, as many of you are aware, is certified by the US Department of Commerce (US DOC), and features an exclusive US Pavilion with 14 leading US companies participating in the exhibition. I am also delighted to welcome a 35-member Clean Tech Delegation led by the USA’s Under Secretary of Commerce for International Trade, Francisco J. Sanchez to the show.

I am delighted to have in our midst two other distinguished guests – Dr. Bharat Bhargava, director – Photovoltaics, Ministry of New & Renewable Energy, Government of India, who is widely credited to be the architect of the India’s National Solar Mission. In the same vein, I am happy to welcome Jim Brown, president, Utility Systems Business Group, First Solar Inc., the world’s largest thin film module manufacturer, with us this morning.

Featuring more than 70 speakers drawn from the industry, academia and government, the conference is themed “Charting India’s Roadmap to Solar Leadership — Translating Potential into Reality.” The conference attracts high-profile participation of solar energy leaders from all segments of the industry supply chain, academia and governments from India and around the world.

The three-day conference also includes an LED Lighting summit, co-organized with Frost & Sullivan, which will focus on SSL (solid state lighting) technology with speakers from among LED manufacturers, LED suppliers, researchers and others.

The climate in which we are holding the show this year has not been without its challenges – on two fronts: the events in Hyderabad on the one hand (which have now, we are grateful to all parties involved, returned to complete normalcy) and the considerable stress that the solar industry is under due the slowdown in the European economies, regulatory changes in the major solar markets and manufacturing over capacity resulting in a fall in PV system prices over the last two to three quarters.

This show and the support it has received are proof that the long term prospects for the solar industry remain most bright in India.

ST/Freescale intro 32-bit MCUs for safety critical applications


Early this month, STMicroelectronics and Freescale Semiconductor introduced a new dual-core microcontroller (MCU) family aimed at functional safety applications for car electronics.

These 32-bit devices help engineers address the challenge of applying sophisticated safety concepts to comply with current and future safety standards. The dual-core MCU family also includes features that help engineers focus on application design and simplify the challenges of safety concept development and certification.

Based on the industry-leading 32-bit Power Architecture technology, the dual-core MCU family, part-numbered SPC56EL at ST and MPC564xL at Freescale, is ideal for a wide range of automotive safety applications including electric power steering for improved vehicle efficiency, active suspension for improved dynamics and ride performance, anti-lock braking systems and radar for adaptive cruise control.

Freescale/STMicroelectronics JDP
The Freescale/STMicroelectronics joint development program (JDP) is headquartered in Munich, Germany, and jointly managed by ST and Freescale.

The JDP is accelerating innovation and development of products for the automotive market. The JDP is developing 32-bit Power Architecture MCUs manufactured on 90nm technology for an array of automotive applications: a) powertrain, b) body, c) chassis and safety, and d) instrument cluster.

STMicroelectronics’ SK Yue, said: “We are developing 32-bit MCUs based on 90nm Power Architecture technology. One unique feature — it allows customer to use dual core or single core operation. The objective of this MCU is to help customers simplify design and to also reduce the overall system cost.

On the JDP, he added: “We will have more products coming out over a period of time. This JDP is targeted toward automotive products.”

Commenting on the automotive market today, he said that from June onward, the industry has been witnessing a gradual sign of recovery coming in the automotive market.

1 MB safety and chassis controller -- 32-bit MCU courtesy Freescale/STMicroelectronics joint development program (JDP)

1 MB safety and chassis controller -- 32-bit MCU courtesy Freescale/STMicroelectronics joint development program (JDP)

Automotive market challenges

There has been an increasing integration and system complexity. These include:

* Increasing electrification of the vehicle (replacing traditional mechanical systems).

* Mounting costs pressure leading to integration of more functionality in a single ECU.

* Subsequent increase in use of high-performance sensor systems has driven increased MCU performance needs.

There are also increasing safety expectations. Automotive system manufacturers need to guarantee the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capability. Also, a move from passive to active safety is increasing the number of safety functions distributed in many ECUs.

Finally, there is a continued demand for quality — in form of zero defects, by which, a 10x quality improvement is expected.

MCU family addresses market challenges

The MCU family offers exceptional integration and performance. These include: high-end 32-bit dual-issue Power Architecture cores, combined with comprehensive peripheral set in 90nm non-volatile-memory technology. It also provides a cost effective solution by reducing board size, chip count and logistics/support costs.

It also solves functional safety. The Functional Safety architecture has been specifically designed to support IEC61508 (SIL3) and ISO26262 (ASILD) safety standards. The architecture provides redundancy checking of all computational elements to help endure the operation of safety related tasks. The unique, dual mode of operation allows customers to choose how best to address their safety requirements without compromising on performance.

The MCU also offers best-in-class quality. It is design for quality, aiming for zero defects. The test and manufacture have been aligned to lifetime warranty needs.

The MCU family addresses the challenges of applying sophisticated safety concepts to meet future safety standards. Yue added, “There are two safety standards — we are following those guidelines.” These are the IEC61508 (SIL3) and ISO26262 (ASILD) system-safety capabilities.

The automotive industry is also targeting for zero defects. “Therefore, all suppliers in tier 1 and 2 need to come up with stringent manuyfaturing and testing process that ensures zero defects,” he said.

32-bit dual-issue, dual-core MCU family

Finally, why dual core? Yue said that the MCU helps customers to achieve to achieve safety and motor control. Hence, dual core will definitely help deliver results.

“In many automotive applications, especially in safety-related applications, we want to have redundancy for safety. In the lock-step mode, two cores run the same task simultaneously, and results are then compared to each other in every computation. If the results are not matched, it indicates that there are some problems.”

This MCU family definitely simplifies design. It uses a flexible, configurable architecture that addresses both lock-step and dual parallel operation modes on a single dual-core chip. Next, it complies with safety standards.

A redundant architecture provides a compelling solution for real-time applications that require compliance with the IEC61508 SIL3 and ISO26262 ASIL-D safety standards. It also lowers the systems cost.

Dual-core architecture reduces the need for component duplication at the system level, and lowers overall system costs.

MindTree’s intelligent video surveillance system — a bit late, but has potential!


Recently, MindTree launched its Intelligent Video Surveillance System (IVSS). Though it seems to be a bit late in the market, the solution has tremendous potential.

Video surveillance globally is said to be a $13 billion market. In India, there has been a huge budget allocation for security worth Rs. 33,000 crores. According to MindTree, its focus is on intelligence, and that would be the company’s differentiator in the years to come.

Technology drivers for such devices include — a move from analog to IP; from networked to distributed; intelligence and analysis; use of allied technologies and standardization.

According to MindTree’s Sharmila Saha, the company wants to become an end-to-end solution provider. Its main value proposition is to bring management and analytics into all of its solutions. MindTree also has a enterprise ready hybrid product that supports both analog and IP cameras. It is starting ready to manufacture/IP licensing products.

Commenting on typical IVSS market and its characteristics, she said these included:
* public infrastructure, defence, educational institutions, etc.,
* financial institutions, retail, enterprise and home,
* server-based storage (networked video recording), and
* server based analytics.

MindTree’s differentiators are said to be the following: video analytics — the solution allows searching metadata, bandwidth management, security managenent — including tamper detection, video watermarking and secure transmission of data; and deployment — MindTree is also going standard compliant, supports multi-vendor devices, and offers customizable solutions.

Let us take a look at some of the features of MindTree’s solutions. Users can certainly do PTZ remotely, and also set camera in the patrol mode. Digital zoom is yet another feature. Image detection is done at 30fps. Image stiching is yet another feature available.

Searches can be done based on both time and data. There is also an events browser. Schedule recording can be performed by setting certain rules. H.264 is used for compressing images. MindTree has also built in face detection and face recognition as part of its video algorithms, besides Virtual TripWire.

S. Janakiraman, President and Group CEO, Product Engineering Services, pointed out that several other algorithms are being developed at the Indian Institute of Science, Bangalore. Another algorithm — image stitching — has been developed by MindTree.

The company is filing the patent for image stitching, as well as for face detection. MindTree can control the storage and network costs since its own algorithms are being used. According to him, the company is in talks with the defence, etc.

MindTree’s network surveillance system helps an existing analog surveillance system to migrate to a centralized and IP based video surveillance system while still exploiting the investment on the analog infrastructure.

Built modularly, the IVSS comprises of multiple components that can also be used individually to increase operational efficiency. OEMs can leverage the reference design from MindTree for creating their own hybrid DVRs and system integrators can use the ready-to-fit solution accelerators and components to provide more robust and flexible surveillance systems to end customers.

IVSS key components
* Digital Video Recorder (DVR)
* Network Video Recorder (NVR)
* Video Management Solution (VMS)
* Video Analytics Algorithms Suite (VAAS)
* Analog-to-IP Encoders
* Smart IP Cameras

Key features of IVSS system:
* Video analytics with distributed intelligence to trigger specific actions on alerts and alarms.
* Intelligent video mining to extract valuable information from raw feed quickly and efficiently.
* Bandwidth management to reduce IP bandwidth requirements for feed transmission.
* Single management station that is scalable for future requirements.
* Reliable alarm management that is configurable for any event.
* Multi-camera tracking for specific objects through multiple cameras.
* Enhanced security features including watermarking and tamper protection.

TI’s 14-bit ADC unites speed and efficiency


BANGALORE, INDIA: Texas Instruments Inc. (TI) recently introduced a dual, 14-bit analog-to-digital converter (ADC), the ADS62P49, at 250MSPS to deliver a premier combination of wide signal bandwidth, high dynamic performance and low power consumption.

The ADS62P49 achieves 73-dBFS signal-to-noise (S/N) ratio and 85-dBc spurious-free dynamic range (SFDR) at an input frequency of 60 MHz. I was able to catch up with Apoorva Awasthy, Business Development Manager, High Performance Analog, Texas Instruments India, to find out more about this new 14-bit ADC.

Chief features of TI 14-bit ADC
Texas Instruments (TI) has united speed and efficiency with the industry’s fastest dual, 14-bit ADC at 250 MSPS. Key features of this device include:

* It delivers a premier combination of wide signal bandwidth, high dynamic performance and low power consumption;
* Fastest dual, 14-bit ADC at 250MSPS enables multi-channel, wide-bandwidth sampling without sacrificing dynamic performance, for enhanced accuracy in portable test equipment;
* Low power of 625 mW per channel reduces thermal footprint for increased system efficiency in high-density, multi-antenna base station receivers and software defined radios;
* Programmable gain and other user-selectable settings maximizes design flexibility;
* Complete signal chain with comprehensive evaluation tools suite speeds time to market; and
* It is first in a series of four 12- and 14-bit dual channel ADCs with sample rates of 210MSPS and 250MSPS, respectively.

TI also says that the 250-MSPS data converter provides 66 percent greater bandwidth than competing dual ADCs. Has this been based on any on-field performance? Awasthy said that this is the performance specified in the data sheet and was tested in a lab.

Naturally, the key application areas would be interesting to look at! Awasthy said, “The ADS62P49 is suitable for applications such as communications and defense imaging systems, and wide-band test and measurement equipment. The block diagram given here shows an application area.Source: TI

Again, when TI says that the ADS62P49 has the “the industry’s fastest sample rate”, what’s the benchmark? Awasthy said, “We have done comparisons between our device and others in the industry. We are the only one to offer a dual, 14-bit device that achieves 250MSPS.”

Solving customer challenges
What are the main customer challenges solved by the new ADC? Awasthy said: “Communications, defense and test design engineers are constantly challenged to create signal and data acquisition receivers with increasingly wide signal bandwidths that do not compromise overall system performance. Another key feature in demand is the low power capabilities without bargaining on performance.

“TI addresses these challenges with the ADS62P49, which delivers high-performance, compact, power-efficient designs, and enables rapid deployment of 3G and 4G systems, software defined radios and spectrum analyzers.”

What if the competition brings out such a device or a better one soon? TI is not in a position to speculate on what the competition is planning. “The data converter market offers tremendous opportunities to TI. We will continue to offer leading edge data converters that address our customers’ challenges and advance next generation system design,” he added.

This is the first in a series of four 12- and 14-bit dual channel ADCs. Awasthy said that TI expects more of such devices to be released in the second half of this year.

Categories: TI Tags: ,

ST’s 8-bit MCUs make efficient use of technology


STMicroelectronics (ST) recently introduced the new 8-bit microcontroller, the STM8S. This new MCU is said to be robust and reliable, and price competitive with system cost integration. Some other features include
• Performance up to 20MIPs @ 24Mhz;
• Excellent code density;
• Leading edge embedded Flash technology with true embedded E²Data; and
• Embedded debug function with low-cost development tools.

In fact, the company announced the general availability of the STM8S105 and STM8S207 MCUs for industrial and consumer applications. Key features of the new devices include high-performance 8-bit architecture, modular peripherals and pin-compatible packages to raise performance, scalability and value for current 8-bit and 16-bit applications.

The STM8S platform enables new generations of 8-bit MCUs, offering up to 20 MIPS CPU capability and 2.95-5.5V operation to help legacy 8-bit systems transition to lower supply voltages. Its 130nm embedded non-volatile memory is among the most advanced technologies currently in use with 8-bit MCUs, and provides true EEPROM data-write with 300,000-cycle durability.

So, what would be typical applications addressed by ST’s STM8S? These would be — home appliances, HVAC, user interfaces, factory automation, motor control, sensors, lighting, e-bikes, circuit breakers, personal care, rechargeable battery operated devices, toys and game accessories, power supplies and power management, and power tools.

The microcontroller boasts advanced architecture for performance. These include:
• High performance core:
– Advanced Harvard and CISC architecture.
– New arithmetic instructions (yXx,y/x).
– 20MIPs peak @ 24Mhz Fcpu.

• Innovative architecture:
– 128 kB linear address space, no paging.
– 16-bit index registers.
– Internal 32-bit memory interface and three-stage pipeline.
– Advanced clock controller for better power consumption and noise control.

The STM8 is said to deliver high performance with excellent code compactness. ST has efficiently made use of technology to break price barriers. According to the company, technology is driving 8-bit evolution, and breakthrough has been achieved with 130nm lithography. The MCU also makes use of E² non-volatile memory, analog and digital peripherals.

STM8S – software requirements for safety
• Immune against EMS, strong against Latchup or ESD.
• Low noise emission.
• Embedded system supporting IEC 60335 class B compliance
– Self test
– Build-in checks (check-sum, ECC..)
– Illegal op. codes
– Interrupt handling
– Clock failure detection, recovery
– Watchdogs (Time monitoring, program flow)

In summary, the STM8 MCU is a high performance 20 MIPs core. Features include lower system cost, and friendly IDE with free software suite.

As for the touch sensing software suite, ST is offering complete NRE/royalty-free source code solution to enable 8-bit STM8 MCU platforms for capacitive touch sensing capability. You can detect the capacitive human touch by controlling the charge/discharge timing cycle of an RC network formed by a single resistor and the electrode capacitance Cx.

The suite has multi-function capability to combine capacitive sensing function to the traditional MCU features (communication, LED control, beeper, LCD control). It delivers with hardware development platform and diagnostic tools to ease the design process.

I will be speaking with ST even further on how MCUs are shaping the embedded world. Stay tuned!

Staying ahead of clock a habit at Magma!


EDA is a complex industry to be in, what with process geometries changing all the time and EDA firms compelled to keep up with those changes. Magma Design Automation Inc. has been one of those, which has kept ahead of the changes and also managed good growth. In other words, Magma has managed to beat the clock consistently and stayed ahead, and continues to do so.

According to Rajeev Madhavan, chairman and CEO, Magma Design Automation Inc.. Magma has been outperforming the EDA industry by 2x globally. He touched upon the drive toward consumerization. Whle it was driven by PCs during the 1980s, mobile phones and PDAs are now the growth drivers for the common man. The consumer space is driving semiconductor applications as well. These are in form of devices with smaller form factors, where power is an important issue.

As an example, Madhavan highlighted the fact that 75 percent of the chips in the iPhone type of complex cell phone has been done using Magma. “We enable such points to happen. Consumer applications are driving EDA, and we are providing that change.”

According to him, India is a major center for Magma. An entire business line of products are now being driven out of India. The physical verification units – DRC, etc., — are all done here. Magma is consistently developing new products and product lines. Any MNC in India has an opportunity to build relationships with the EDA powerhouse.

EDA is all about integration. With operating margins getting slimmer, most companies have been moving to Fab-Lite. India has great expertise in design knowledge. India should shift its focus on developing the intellectual knowledge side, contended Madhavan. As for fabs, as and when those happen in India, they will definitely create jobs. “Fab-lite is actually good for EDA. It means more design productivity. Leading firms such as TI, NVIDIA, Broadcom, etc., are our customers,” he said.

Magma is now looking at more value addition and faster development. It has covered the entire EDA domain. Magma has a culture of rewriting its software a lot more and also covers all new process geometries. According to Madhavan, Magma is constantly in touch with leading foundries such as TSMC.

It is said that right now, around 75 percent of the chips in 45nm currently use Magma. Magma is also working with a customer in 32nm. Madhavan said: “You have to develop the tools as the processes change. At Magma, we need smart people who can understand electrical engineering and computer science. Growth comes in identifying and building the talent pools.”

As for product lines developed in India, Magma’s Quartz Formal has been developed largely in India. Most of the development work is happening in NOIDA, near Delhi. Work on DRC is being done out of Bangalore. “Every single product from Magma has some footprint in India,” he said. The complexities of chips have been growing and those require more automation.

Magma intends to grow from $178 million to $211 million during 2008. Madhavan felt that as the eco-system units come up in India, the company can move forward. Magma is hopeful that more design companies will be getting into India.

90nm designs major in India
Ricky Bedi, Senior Director, Application Engineering, Magma Design Automation India Pvt Ltd, added that the EDA industry had moved on from being optimizers. India too has to now move forward from being outsourcers to enablers.

He said, “When that happens, India will play a bigger role and offer more services. For example, Wipro, etc., are now doing full turnkey solutions.” Magma India is now working with over 32 universities, regional engineering colleges (RECs), IITs, etc. The intent is to facilitate VLSI programs in all of those places.

However, he agreed that the innovation has not really kicked off in the country. As of now, 90nm designs are in the majority in India, and in comparison, 65nm designs are lesser. Magma has already gone into 45nm, and even into 32nm. Bedi said: “Right now, yield is imperative in 45nm. Innovation will continue in the smaller geometries. Innovation has to focus more on predictability, etc.”

There is another trend worth mentioning — about re-usable IPs. According to Magma, there will be even more of re-usable IPs. As the designs themselves get complex, designers need to achieve those in shorter timeframes as the time-to-market (TTM) is crucial. Replication of blocks is also happening. Implementation of re-usable IPs will go up a notch, added Bedi.

While the EDA tools are now catching up with the advances in semiconductors, it has not been smooth sailing for language. Bedi added: “As far as language is concerned, language itself does not blend so easily. It takes great effort to move from Verilog to VHDL.”

Yatin Trivedi, director, Industry Partnership Program, Design Implementation Business Unit, Magma Design Automation Inc., touched upon the aspect of power. He said: “In the EDA format, it is important that the power format is accepted by as many vendors. The difference should be in the usage, not the format. In any design flow — from RTL to GDS — any design that is implemented must be simulated. Power information is now an integral part of the design. Leakage can destroy a die.”

Cadence: Plan verification to avoid mistakes!


Apurva Kalia

Apurva Kalia

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there’s verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

STMicro intros M24SR dynamic NFC/RFID tag


Amit Sethi

Amit Sethi

STMicroelectronics recently introduced the M24SR dynamic NFC/RFID tag.

Speaking about the USP of the M24SR, Amit Sethi, Product Marketing manager – Memories and RFID, STMicroelectronics India, said: “The unique selling proposition of the M24SR product is its two interfaces, giving users and applications the ability to program or read its memory using either an RF NFC interface or a wired I2C interface, in an affordable and easy-to-use device for a wide range of applications such as consumer/home appliance, OTP card, healthcare/wellness and industrial/smart meter.”

Let us see how the M24SR is beneficial for smartphone or any other audio device.

The M24SR is a dynamic NFC/RFID tag that manages the data exchange between the NFC phone and the microcontroller. The main use cases for data exchange are updating user settings, downloading data logs, and remote programming and servicing. The dynamic tag also enables seamless Bluetooth and Wi-Fi pairing, which is useful in, for example, audio devices.

How is the M24SR different from other products of the same segment?

Sethi said that the key difference is the dual interface: the M24SR memory can be accessed either by a low-power 2C interface or

M24SR

M24SR

by an ISO14443A RF interface operating at 13.56MHz. It also features RF status (MCU wake-up) and RF disable functions to minimize power consumption. In addition, the devices support the NFC data exchange format (NDEF from NFC forum) and 128-bit password protection mechanism.

The M24SR series is available in EEPROM memory densities from 2 Kbit to 64 Kbit and three package types: SO8, TSSOP8, and UFDFPN8.

What are the contributions of M24SR toward the Internet of Things?

Accotding to him, the M24SR dynamic NFC/RFID tag interactive and zero power capability, simplifies complex communications setups and enables data exchange among the home automation, wearable electronics, home appliances, smart meter, wellness, etc.

Especially with the NFC capability, the M24SR is ideal for applications waiting for something, like a ticket or ID to launch an activity.

Relevance for India
Finally, what’s the relevance of the product for the Indian market?

Sethi added: “Mobile and NFC based application are gaining its popularity in India. M24SR is an easy-to-use and an affordable product for the Implementation of NFC-based applications in transportation, entertainment, and lifestyle areas.

As for the go-to-market strategy, the M24SR mass market launch is planned for end of February 2014. Some M24SR samples have been delivered to key customers during Q4 2013 and design/development is ongoing.

2013 in review


The WordPress.com stats helper monkeys prepared a 2013 annual report for this blog. Thanks a lot, WordPress!

Here’s an excerpt:

The Louvre Museum has 8.5 million visitors per year. This blog was viewed about 73,000 times in 2013. If it were an exhibit at the Louvre Museum, it would take about 3 days for that many people to see it.

Click here to see the complete report.

Categories: Blogging, semicon blogs
%d bloggers like this: