Tensilica to expand Cadence IP footprint in SoCs

Chris Rowan.

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.

Tensilica acquisition to broaden Cadence’s IP portfolio

Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash.

With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto infotainment and home applications.

The Tensilica IP also complements industry-standard processor architectures, providing application-optimized subsystems to increase differentiation and get to market faster. Finally, over 200 licensees, including system OEMs and seven of the top 10 semiconductor companies, have shipped over 2 billion Tensilica IP cores.

Pankaj Mayor

Talking about the rationale behind Cadence acquiring Tensilica, Pankaj Mayor, VP and head of Marketing, Cadence, said: “Tensilica fits and furthers our IP strategy – the combination of Tensilica’s DPU and Cadence IP portfolio will broaden our IP portfolio. Tensilica also brings significant engineering and management talent. The combination will allow us to deliver to our customers configurable, differentiated, and application-optimized subsystems that improve time to market.”

It is expected that the Cadence acquisition will also see the Tensilica dataplane IP to complement Cadence and Cosmic Circuits’ IP. Cadence had acquired Cosmic Circuits in February 2013.

What are the possible advantages of DPUs over DSPs? Does it mean a possible end of the road for DSPs?

As per Mayor, DSPs are special purpose processors targeted to address digital signaling. Tensilica’s DPUs are programmable and customizable for a specific function, providing optimal data throughput and processing speed; in other words, the DPUs from Tensilica provide a unique combination of customized processing, plus DSP. Tensilica’s DPUs can outperform traditional DSPs in power and performance.

So, what will happens to the MegaChips design center agreement with Tensilica? Does it still carry on? According to Mayor, right now, Cadence and Tensilica are operating as two independent companies and therefire, Cadence cannot comment until the closing of the acquisition, which is in 30-60 days.

Global semiconductor industry outlook 2013: Jaswinder Ahuja, Cadence

Jaswinder Ahuja, Cadence.

How will 2013 turn out to be for the global semiconductor industry? Will there be growth for the global EDA industry? Importantly, how will the Indian semiconductor industry perform in 2013? I asked Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems India these questions.

Outlook for global semicon industry in 2013
First, how is the outlook for global semiconductor industry in 2013 going to be? Ahuja said: “The long term outlook for the semiconductor industry remains positive, with mobility and cloud computing being the key drivers. The global economy is forecast to grow around 4 percent annually through 2016, according to an April 2012 report from the International Monetary Fund (IMF).

“In its June 2012 report, Gartner predicted growth in electronics and semiconductor industries to outpace that of the world GDP growth, at 5½ percent annually to approach $2 trillion for electronics and 6 percent annually for semiconductors through 2016. So, the semiconductor industry outlook remains very positive overall.

“In the near term, multiple challenges will need to be weathered with respect to the global economic climate, especially in European markets. The JP Morgan/GSA Semiconductor Index of Leading Indicators points to a soft semiconductor industry in 2013. However, there are lot of new products in the mobile and tablet space that are driving demand, such as the iPhone 5, Microsoft Surface, and Samsung Galaxy S III.

“The China semiconductor space is emerging as a key market for semiconductor company revenue, and forecasts predict that it will show rapid annual growth rate. The consolidation and M&A activities that we are seeing in the global semiconductor industry also indicate a positive outlook for the upcoming year.

“In India as well, the semiconductor industry will continue to see growth. The injection of funds and other support outlined in the National Policy on Electronics will provide an impetus to home-grown design and manufacturing, which should start gaining traction in 2013.”

Five trends for 2013
What would be the three or five trends likely to be visible in 2013? Ahuja said Cadence sees five big trends that will drive growth in the near and long term. These are: mobility, application driven design, video, cloud and security.

Probably, the most pervasive change in electronics recently has been mobility. When we talk about mobility, it’s just not about smart phones or tablets, but any kind of device which is mobile. Within the mobile space, software applications help system manufacturers and vendors differentiate themselves and stand apart from the competition. The need to have apps on all kinds of devices is driving rapid growth, as well as placing new demands on EDA companies.

The entertainment industry will be the key driver for video, and as the year progresses, we will continue to see more and more products and solutions introduced to tap into the demand. For the semiconductor industry, video will drive growth both in the end consumer market (mobile platforms) and the enterprise space (networking industry).

In many ways, the backbone to mobility is the cloud. With its network servers and infrastructure, the cloud is what delivers much of the content and value to all of those mobile devices. Statistics show that we need one server for every 600 smart phones and one for every 120 tablets. So there is a big need for data centers which can provide support for all the computing and back-end operations.

Security of data in mobile devices and the cloud will continue to be a challenge in the near future. There will be renewed calls to develop products that can protect critical infrastructure and sensitive information from security breaches.

Cadence Allegro 16.6 accelerates timing closure

Cadence Design Systems Inc. has released the Allegro/OrCAD 16.6 that provides unmatched, scalable design solutions addressing technology challenges.

Allegro is meant for simple to more complex boards, for the geographically dispersed design teams. They also cater to the personal productivity needs for start-ups and small to medium companies. It provides high-speed, power aware SI, HDI managed design environments, that is meant for medium to large enterprises.

Allegro, Sigrity and OrCAD – major themes of Allegro PCB 16.6
The major themes of Allegro PCB 16.6 include the first ECAD collaborative environment for work-in-progress (WiP) PCB design using Microsoft SharePoint. It accelerates the timing closure for high-speed interfaces such as DDRx. There is support for advanced miniaturization techniques that embed passive and active components on inner layers of a PCB.

Cadence Allegro is for simple to more complex boards.

Regarding the percentage of enhanced miniaturization capabilities for embedding dual-sided and vertical components, Hemant Shah, product marketing director, Allegro PCB and FPGA Products, Cadence, said: “Components with dual-sided contacts offer customers the ability to connect to the components pins through the layer above or through the layer below. This provides routing flexibility. It also allows customers who want redundant connections on inner layers.”

There can be accelerated design implementation through flexible PCB team design capability. Leveraging GPUs for faster display, you can pan and zoom on dense PCBs, enabling greater design productivity.

Typical product creation environment includes the best-in-class hardware design environment for implementation, analysis and compliance sign-off. The design team collaboration capability encompasses design-chain partners. Design data can be integrated into corporate systems to manage cost and quality, and provide visibility. It allows on-time release into manufacturing to build products.

Allegro, OrCAD and Sigrity ensure product creation with the best-in-class PCB design environment. Design team collaboration and productivity is integrated at the PCB. Design data integration is done into corporate systems to manage cost and quality. There is on-time release into manufacturing to build products. Allegro, OrCAD and Sigrity are helping create market leading products.

Users can create the first ECAD collaborative environment using Microsoft SharePoint. Design creation and collaboration trends include geographically distributed teams, increase in outsourcing (OEMs-ODMs), product life cycle management tools are not designed/targeted for managing work-in-progress data. For every design engineer, there are 3X-5X collaborators, reviewers, etc.

The Allegro Design workbench integrates seamlessly to SharePoint 2010. The Team Design Authoring cockpit facilitates design data in and out of SharePoint providing WiP design data management. There is block level check-in, check-out, etc. SharePoint is already deployed in many companies. It is scalable from single server to cloud environment. It has rich platform for power users to configure and developers to customize.

By creating the first ECAD collaborative environment, users can reduce the product creation time by up to 40 per cent. Chances of first pass failure are also reduced from 25 per cent to 1 per cent. Users can accelerate the timing closure on high-speed, multi-Gigabit signals.

Cadence releases latest Encounter RTL-to-GDSII flow

Rahul Deokar, product management director, Cadence.

Cadence Design Systems recently introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers.

Rahul Deokar, product management director, said: “We are addressing designer challenges in – high performance design, giga-scale design and advanced node design. The first challenge is the PPA – power performance and area. Next challenge is to handle giga-scale designs with efficient turnaround time. The third key challenge is fast time-to-market on advanced 28nm/20nm design.”

With this latest release, Cadence provides the industry’s best PPA. Second, it is providing 1 billion gates on designer desktops. Third, it provides the fastest path to 20nm digital design. In the new announcement, there are three new technologies – GigaOpt + CCOpt, GigaFlex, and 20nm double patterning.

Cadence has introduced “GigaOpt” – a common optimization engine that unifies physical synthesis and optimization. GigaOpt provides designers globally optimal results across the front-end and back-end of the design flow. And that results in the benefit of the industry’s best PPA for high-performance design. GigaOpt has been designed from scratch to be multi-threaded, which makes it ultra fast and ultra scalable.

Another innovation, CCOpt, is the first and only technology in EDA to unify clock tree synthesis and physical optimization. CCOpt is now an integral part of the Encounter flow accelerating design closure with the best PPA. CCOpt facilitates:
* 10 percent improvement in design performance and total power.
* 30 percent reduction in clock power and area.
* 30 percent reduction in IR drop.

The Encounter flow now allows 1 billion gates to be enabled on the designer’s desktops. This is done with the new GigaFlex abstraction technology. It is the first and only technology in EDA that enables flexible, accurate abstraction adaptable to the flow stage. There is 10X capacity and TAT gains on 100 million+ instance designs. GigaFlex abstraction technology allows accurate, early physical modeling, concurrent top-and-block interface optimization, and concurrent hierarchical closure and late-stage ECO.

Realizing EDA360: Charlie Huang, Cadence

Long-term trends are strong for semiconductor and electronics. According to databeans estimate (Feb. 2011), semiconductor revenue will likely reach $450 billion by 2015 and electronics revenuw will likely reach $2,800 billion by 2015.

Speaking at the CDNLive! 2011 event in Bangalore, India, Charlie Huang, SVP of Worldwide Field Operations, Cadence Design Systems Inc., said that the challenges in the near term are slowdown in Europe and USA. The weakness is driven by increasingly negative views on the global economy, end demand, orders and outlook. Key indicators are also showing that the economy is facing headwinds. The 2011 GDP growth projections have deteriorated since the beginning of the year. The economy has been marred by high unemployment and low consumer confidence.

As of now, innovation has been driving growth. Apps have been driving innovation, followed by video, mobility, cloud and green technology. The impact on the electronics industry is multi-fold. There is a new development paradigm and collaboration has been increasing. The IP is also expanding beyond cores and the EDA is changing.

Source: Cadence.

The new development paradigm for system companies is to differentiate on applications and semiconductor companies must deliver on application-driven hardware-software platforms. IP has now expanded well beyond the core. EDA is also changing, and Cadence is investing to deliver on the EDA360 vision. There are multiple silicon realization challenges. Cadence silicon realization solutions enable fast, deterministic, end-to-end path to silicon success.

As an example, ARM and Cadence have collaborated on the GHz implementation of Cortex-A15. ARM chose ARM Artisan physical IP, evaluated the Cortex-A15 RTL, and supported CPF. Cadence optimized the EDA flow, experienced support at EAC, and provided EDA tool releases and iRM.

ARM, TSMC and Cadence also collaborated on the industry’s first 20nm Cortex-A15. TSMC provided the 20nm process qualification and A15 learnings. ARM handled the 20nm implementation experience, A15 considerations in 20nm and TSMC 20nm readiness milestone. Cadence provided the 20nm research to reality, contributed and grew the A15 expertise and TSMC 20nm readiness milestone.

The end result: the industry’s first 20nm Cortex-A15 tapeout, thanks to a successful three-way vertical collaboration. ARM, Cadence and TSMC engineers worked side-by-side. The project priorities included 20nm DPT implementation schedule and 20nm readiness milestone.

Cadence VLSI certification program (CVCP) aims to deliver ‘industry grade’ graduates

Cadence Design Systems presented a curtain raiser on the Cadence VLSI Certification Program (CVCP) during the CDNLive India University conference. The availability of trained manpower holds the key to sustained growth. Also, the first thing required to build a good product is to have a good design. Hence, the need for good chip designers.

Cadence already has over 300 program participant institutes in India. The company regularly conducts ‘train the trainer’  programs as well. This program has so far witnessed the tapeouts of five chips and includes IPs from 14 colleges.

Cadence has also started additional strategic programs. First, finishing schools — initiatives with some universities and Indian semiconductor houses. These have been established to bridge the skill gap. Cadence has seen some success in Hyderabad and Bangalore. It has also contributed to the industry demand of manpower. Cadence also has the Orcad training program.

Joint development activity has been happening within the industry-academia to provide a consistent quality of curriculum and develop broader penetration.

The enablers/catalysts are industry veterans, who accept their social responsibility of training upcoming engineers. Some of the first movers aer already Cadence’s training partners.

CVCP initiative
Cadence’s CVCP has been launched with objective of delivering graduates that are ‘industry grade’. It will also provide an incremental training approach, leading up from VLSI fundamentals to industry relevant skills.

The industry relevant leading edge course work has been developed and proven through various programs such as the Cadence-Brazil initiative. Graduates will undergo hands-on guided development projects. The CVCP’s duration is of 214 hours spread over six months. It offers the following:
* MTEch in VLSI.
* MTech in digital electronics.
* MTech in embedded systems.
* BE/BTech in ECE, EE, TC.

The course will be running concurrent to the ongoing degree. Cadence owns the course, which is delivered by CCTP with support from CDNS. NIST, Berhampur, in Orissa, is the first participant in the CVCP with a batch of 60 students.

VDAT 2010: Real, but ‘different’ opportunity in emerging markets — Jaswinder Ahuja, Cadence

Guests lighting the lamp at VDAT 2010, Chitkara University, Himachal Pradesh.

The VLSI Design and Test Symposium 2010 (VDAT 2010) was held last week  (July 7-9) at the picturesque Chitkara University Campus, Himachal Pradesh, located 32 kms from Chandigarh.

VDAT is an annual activity of the VLSI Society of India, and was initiated to provide a discussion forum for Indian academicians and industry professionals working in the areas related to VLSI.

Delivering the keynote, Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems India, said: “There is a “real” but “different” opportunity in the emerging markets. One would have to immerse himself/herself to understand the market better. India is also a great proxy for the emerging markets. It has the design expertise as well to address this market.

“The next 10-15 years present a unique window of opportunity to India entrepreneurs to play a leadership role in the global economic growth.”

Elaborating on the “real” but “different” opportunity in emerging markets, he added: “The base of the pyramid opportunity is very real. As per World Resources Institute, there are four billion people in the developing world representing a $5 trillion market opportunity who have real needs and aspirations but are under served.

“At least 700 million of these people are in India and represent a real business opportunity as well as an opportunity to “do good” and help include them into the formal economy and enable India to achieve its aspiration of 9-10 percent “inclusive” GDP growth. This requires business innovation and a different mind-set presenting a transformative opportunity to marry low cost, good quality, sustainability and profitability at the same time.”

India a great proxy for emerging markets!
India is also said to be a great proxy for the emerging markets. Ahuja explained: “India is many markets — urban, semi-urban and rural) in one and presents a broad spectrum of challenges that need to be overcome to be able to reach the 700 million people market opportunity.”

“If we can make something (product or service) work in India, we can make it work pretty much anywhere else in the developing world – whether it is financing, distribution, logistics, operating environment or anything else.”

Opportunity for Indian entrepreneurs to play leadership role
The next 10-15 years present a unique window of opportunity to India entrepreneurs to play a leadership role in the global economic growth.

According to Ahuja: “The markets of the future are in our backyard and we have among the best design talent in the world. If we can immerse ourselves in the market to understand the real needs and opportunities and then leverage our design expertise to build products for this market we will be best positioned to serve the next 4 billion consumers of the world.

“Indian entrepreneurs have an opportunity to play a leadership role in the global economic growth across sectors, but especially in electronics. No other country in the world has this unique convergence of circumstances. This opportunity is once in a lifetime and ours to lose if we do not create the right environment and framework to leverage it.”

EDA360 unplugged with Cadence’s Jaswinder Ahuja

Jaswinder Ahuja, corporate VP & MD, Cadence Design Systems (I) Pvt Ltd.

Following the announcement of the EDA360 last week, I managed to get in touch with Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (I) Pvt Ltd. We discussed a variety of topics such as why the EDA industry is at the crossroads, EDA360 unplugged, the integrators vs. creators concept, the IP stack and the road ahead for EDA360.

First, why is the EDA industry at the crossroads?

According to Ahuja, if you look at the evolution in the electronic design world, systems companies are finding differentiation and value through the creative, innovative applications or “apps” that are being demanded by end consumers. This is true not only in the mobile handset world, where iPhone and Android are obvious examples, but anywhere there’s a processor. Therefore, software is becoming a very important part in the scheme of things.

“Semiconductor companies are being asked by system companies to provide the hardware platform as well as the software that will run on that particular platform. That is the trend that Cadence is seeing today, and that is what is discussed in the EDA360 manifesto,” he added.

EDA is at crossroads because EDA companies can no longer provide the tools only for IP integration and silicon realization like they have been doing all these years. EDA now has to encompass SOC realization (including bare metal software) and then move towards system realization, which includes mechanical/board design, he noted.

EDA360 and its key features

As mentioned earlier, the EDA 360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.

Ahuja said that EDA360 represents System Realization, the development of a complete hardware/software platform ready for applications development; SoC Realization, the creation of a single SoC including hardware-dependent software; and Silicon Realization, which includes complex digital, analog, and mixed-signal designs.

The traditional approach to system development starts with the hardware, and appends the software and the applications later. With application-driven System Realization, designers start by envisioning the applications that will run on the system, define requirements, and then work their way down to hardware and software IP creation and integration. This flow requires some new and expanded capabilities.

Part of system realization is project management. EDA360 reaches beyond engineering teams to help customers meet project and business objectives.

Key features of EDA360 include:

* Outlining how companies can bridge the profitability gap, not just the productivity gap.

* Explaining the shifts to integration and profitability.

* Software aware SoC realization, which includes an integrated, optimized IP stack.

The four chapters of the EDA360 manifesto take a look at:

Chapter 1: EDA Industry Focus Shifts to Integration and Profitability.

Chapter 2: Application-Driven System Realization.

Chapter 3: Software-Aware SoC Realization.

Chapter 4: EDA360 Enables Silicon Realization.

Cadence Virtuoso IC6.1.4 design platform comes with several enhancements

Last week, Cadence Design Systems Inc. introduced the Virtuoso IC6.1.4 — with dramatic improvements to the Virtuoso IC design platform — that reduces overall design time and ensures high-quality production ICs.

These enhancements are said to benefit design teams working along the full spectrum of design complexity, from the most advanced-node, cutting-edge designs to more traditional chips.

This release has been extended to work efficiently at advanced nodes down to 28 nanometers and now supports 64-bit processing for improved capacity and performance. The Virtuoso Space-Based Router has been integrated into the Virtuoso Layout Suite cockpit, making it easier to access.

I got into a conversation with Steven Lewis, marketing director, Cadence, to find out more about this release.

Steven Lewis, marketing director, Cadence Design Systems.

Lewis said: “Virtuoso IC61 was first shipped in October, 2006, over three years ago. IC614 is the latest release of this platform. IC61 is based on OpenAccess as a database with a Qt based GUI. Also, in IC61 a common design constraint system is key to design spanning schematics, layout, routing, circuit optimization, and all other Virtuoso applications.”

The IC 614 has a number of significant areas of enhancements. These include:

1) Significant improvements to analog design environment — A number of key enhancements have gone into ADE to make it even easier to use and to improve performance. Areas like: data presentation, multi-testbench support, analysis and signoff quality validation, data sheet generation, simulation results comparisons, and intelligent selection of sensitivity to statistical variations to dramatically reduce the number of simulations needed.

2) Native integration of the Catena interconnect engine — This enables integration of the Cadence Space-based Router into VLS-GXL, including the common design-constraint system, runtime OA database and OA techfile for design rules. In addition, the Wire Editor, which is based on this technology, is available to every VLS XL Layout Designer.

3) Metric-Driven Productivity — IC 6.1.4 is all about productivity, productivity, productivity. Many users of VLS spend six to eight hours a day in front of this cockpit and incremental improvements have a significant cumulative effect. IC 6.1.4 will:
* Reduce the mouse miles that a layout designer sees.
* Reduce the mouse clicks required for an operation.
* Reduce the menu depth for an operation.

And, how will the IC6.1.4 gain capacity, performance and usability boosts to shrink design cycles?

According to Lewis, there are a number of enhancements to frequently used features, like a new Layer Palette, improved Repeat Copy, enhancements to Via Placement, a new Smart Ruler, and PCell Caching. Additionally, there are improvements to the connectivity, constraint-aware editing and verification, and capacity with the 64-bit port.