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Thrive or survive…going for gold in post-recession recovery: Malcolm Penn @ IEF2010, Dresden


Malcom Penn, chairman and CEO, Future Horizons.

Malcom Penn, chairman and CEO, Future Horizons.

According to Malcom Penn, chairman and CEO, Future Horizons, 2010 — a barnstroming year — will likely see the global semiconductor industry grow by 31+ percent. He was delivering the company’s forecast at the ongoing 19th International Electronics Forum (IEF) 2010 in Dresden, Germany, which ends here tomorrow. He said it would take a disaster of the scale of Lehmann Brothers to derail this now!

Some of the other forecasts made by Malcolm Penn include:
* 2011: +28 percent; based on: peak of the structural cyclical boom (could stretch into 2012).
* 2012: +18 percent; based on: normal cyclical trash cycle starting 2H-2012 (1H-2013?).
* 2013: +3 percent based on: market correction in full flow (could be negative, cap ex overspend and inventory build depending).
* 2014: +12 percent; based on: start of the next cyclical recovery (single digit, if 2013 is negative).

Given the now unavoidable 2010-11 fab shortage, the growth upside for 2010-12 is huge!

The forecast track record of Future Horizons is quite interesting. As per forecasts made during the IFS2010 in Jan.2010, the chip fundamentals was said to be in very good shape. The industry was starting its recovery with shortages. Also, the ASPs had already stopped faling. The inventory levels were at an all-tme low. Finally, the capacity was tight, and spending, weak!

All of this added up to two years of very strong growth in prospect. Penn had said: “It doesn’t get much better than this. But, despite what the numbers say, still no-one believes beyond the next quarter!  “Ah but” is still driving the industry consensus!

Industry fundamentals don’t lie — believe in them or die! The capacity famine was instigated two+ years ago — well before the crasj, today’s shortage was inevitable. The recovery dynamics will continue to strengthen. Future Horizons’ forecast is now +31 percent ~$300 billion. The next trash dynamic has still not yet triggered. It is unlikely to happen before 2011, meaning, 2012 impact. However, the economic uncertainty remains the biggest risk. Also, the global financial system is fundamentally flawed. Read more…

SEMICON Europa 2013: Where does Europe stand in 450mm path?


SEMICON Europa was recently held in Dresden, Germany on Oct. 8-10, 2013. I am extremely grateful to Malcolm Penn, chairman and CEO, Future Horizons for sharing this information with me.

Semicon Europa 2013SEMICON Europa included a supplier exhibition where quite a few 450mm wafers were on display. One highlight was a working 450mm FOUP load/unload mechanism, albeit from a Japanese manufacturer. These exhibits did illustrate though that 450mm is for real and no longer a paper exercise.  There was also a day-long conference dedicated to 450mm in the largest room. This was crowded throughout the time and a large number of papers were given.

Paul Farrar of G450C began with a presentation about Supply Chain Collaboration for 450mm. His key message was there are 25 different tools delivered to G450C of which 15 are installed in the NFN cleanroom. This number will grow to 42 onsite and 19 offsite by Q1 2015.

He stated that Nikon aims to have a working 193i litho machine in 2H 2014 and install one in Albany in 1H 2015. Farrar also reported a great improvement in wafer quality which now exceed the expected M76 specification, and prime wafers to the M1 spec should be available in Q3 2014. There has also been good progress on wafer reclaim and it is hoped some wafers can be reused up to 10 times, although at least three is the target.

Metrology seems to be one of the most advanced areas with eight different machines already operational. The number of 450mm wafers in their inventory now stands at over 10,000 with these moving between the partners more rapidly. It was immediately noticeable from Farrar’s speech that G450C is now recognising the major contribution Europe is making to 450mm and is looking for more collaborations.

Facilities part of F450C
Peter Csatary of M&W then dealt with the facilities part of G450C, known as F450C. This group consists of:
• M&W (co-ordination)
• Edwards
• Swagelok
• Mega Fluid Systems
• Ovivo
• CH2MHILL
• Haws Corp.
• Air Liquide
• Ceres Technlogies
• CS Clean Systems

F450C is seen as streamlining communications with the semiconductor companies and their process tool suppliers. The group will focus on four key areas, namely Environmental Footprint, Facility Interface Requirements, Cost and Duration, and Safety and Sustainability.

One interesting point raised was that 450mm equipment is inherently more massive and one suggestion has been that ceiling mounted cranes will be required to install and remove equipment. This of course means that fab roofs would need to be stronger than previously. This topic was discussed at the latest F450C meeting subsequent to this conference.

Another new concept is that of a few standardised 3D templates and adapter plates to allow fab services to be pre-installed before the equipment is placed. An interesting point made elsewhere by M&W is that the current preference is to place a fab where there are already other fabs in existence so that the infrastructure to transport products, materials and services is already in place, as are basic utilities such as power, natural gas and water supply.

However, the scale of the expected utility demand at 450 mm ups the stakes as for example a large 300 mm facility uses about 4 million gallons of water per day, whereas a 450 mm fab will use almost double that, putting immense strain on a location’s infrastructure should there be other fabs in the region. This could affect future site selections.

An outcome of this phenomenon is that the reduction, reclaim and re-use of materials will no longer be driven only by the desire to be a good corporate citizen, but will also be driven by cost control and to ensure availability of required resources such as power, water, specialty gases and chemicals.
Read more…

EC’s goal: Reach 20 percent share in chip manufacturing by 2020!


The European Commission is said to have a goal: to reach 20 percent world-share in chip manufacturing by 2020! Heinz Kundert, president, SEMI Europe, has even laid out an industrial strategy that will cover three complementary lines, such as:

* Transition to 450mm, expected to primarily benefit equipment and material manufacturers in Europe.
* “More than Moore” on 200mm and 300 mm.
* “More Moore” for ultimate miniaturization on 300mm wafers.

Investment will be focusing on Europe’s clusters of excellence in manufacturing and design — Grenoble, Dresden and Eindhoven-Leuven — and support partnerships and alliances across the value chain in Europe.

The key question of why Europe needs 450mm wafers has been answered by Mike Bryant of Future Horizons. The European semiconductor industry’s vision is to recover a leading position in the world throughout the entire value chain and to reverse the current negative trend of its worldwide competitiveness.

Among the many strategies the EC is planning to adopt include:

* Benefit from a single explicit European semiconductor industry policy.
* Maintain a high level of R&D effort, in a balanced way between the 150/200/300/450mm fields, between “More Moore” and “More than Moore”.
* Strengthen all elements of the value chain, from design to application.
* Develop co-operating programs and synergy initiatives between all semiconductor actors operating in Europe.

Europe has always stressed on stronger co-operation among the other industry segments. Some of these are automotive, energy, healthcare and well-being, security and safety, etc.

E450EDL – European 450mm equipment demo line


Malcolm Penn, chairman and CEO, Future Horizons, sent me the Enable 450 newsletter. The goal of the Enable 450 is: Co-ordination Action to enable an effective European 450 mm Equipment and Materials Network. Here, I am presenting a bit about the E450EDL – European 450mm Equipment demo line.

Malcolm Penn

Malcolm Penn

The aim of the ENIAC E450EDL key enabling technology pilot project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition that started with the ENIAC JU EEMI450 initiative and proceeded with subsequent projects funded with public money, amongst others NGC450, SOI450, EEM450PR.

The demo line resulting from this project will be such that it will enable first critical process module development by combining imec infrastructure with tools remaining at the site of the manufacturers (distributed pilot line). Multi-site processing will allow partners to participate in the world first 450mm integration studies and will be enabled by the controlled exchange of 450mm wafers between different sites.

The consortium comprises 41 members (from 11 different European countries) with many SMEs and research institutes. The project is organized in five technical work packages and a work package on management and co-ordination.

In the work package on integration and wafer processing first critical modules will be developed and will demonstrate the feasibility of processing on 450mm wafers. The main objective in the work package on lithography is to develop a wafer stage test-rig, which
can be implemented into the pilot line system. In the work package on front end equipment several tools will be developed such as a plasma ion implant module, a plasma dry etch module, a RTP system and a single wafer cleaning system.

Furthermore, in the dedicated work package on metrology 450mm metrology tool types will be developed for amongst others dielectric film thickness and composition measurements, defect inspection, defect review and analysis, optical critical dimensions (CD), overlay (mask and wafer) and 3D metrology.

Finally, from the work package on wafer handling and automation a set of equipment will be provided to support the demo line operations, and facilitate the R&D dedicated to process and metrology modules.

The project will last 36 months beginning on 1st of October 2013. The budget has been given at €204.6 million of which the ENIAC JU will fund €30.8 million. This project is still considering new members so if you are interested please contact ASML.
Read more…

IMEC’s 450mm R&D initiative for nanoelectronics ecosystem


Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.

IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&D pilot line will enable full 450mm process capability for advanced nodes by early 2017.

Source: IMEC, Belgium.

Source: IMEC, Belgium.

Scaling
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture.

Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.

IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.

IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.

With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.
Read more…

III-V high mobility semiconductors for advanced CMOS apps


Clement Merckling, IMEC, Belgium, presented on the epitaxial growth and in-situ passivation requirements for III-V high mobility semiconductors for advanced CMOS applications at the Semicon Europa in Dresden, Germany.

The motivations for III-V MOS transistors include higher electron carrier mobility (@ low-field), more efficient source injection, smaller energy bandgap, VDD scaling, band engineering capabilities, lower temperature processing, high-K gate first process possible and 3D compatible architecture.

IMEC III-V EPI.

IMEC III-V EPI.

The International Technology Roadmap for Semiconductors (ITRS) believes in Ge and III-V. IMEC epi + in-situ oxide ‘tool park’ involves MBE (molecular beam epitaxy) and MOVPE (metalorganic vapour phase epitaxy) III-V growth techniques. The III-V EPI is clustered with in-situ oxide capabilities.

The AIXTRON Crius 300mm looks at III-V selective epitaxial growth (III-As and III-P). The AMAT/RIBER III-V logic cluster 300mm looks at the III-V selective epitaxial growth (III-As and III-P), in-situ surface analysis, handled by RIBER ISA 300, and oxide (ALD and MBE) chambers in-situ. The RIBER MBE 49 cluster 200mm looks at the III-V solid source epitaxy (III-As and III-Sb) oxide chamber in-situ.

Main issues and challenges
Main issues for III-V integration include III-V integration on Si platform. There are all sorts of crystalline defects. Next, gate stack formation on MOS. It is much more difficult to passivate interfaces. Smaller bandgap, means, an increased Ioff due to band-to-band-tunneling.

Challenges with III-V heteroepitaxy on Si include Lattice mismatch, anti-phase boundaries (APB), mismatch stress relaxation and related defects such as dislocations at interface, and extended defects (threading arms, SFs). There are other defects caused at isolation interfaces, such as twins, stacking faults, facets, etc. Finally, there is interdiffusion at heterogeneous interfaces.

However, it is possible to achieve high quality heteroepitaxy by direct epitaxy using metamorphic buffer and defect confinement and wafers bonding. Strain relaxed buffer (SRB) is among the options for III-V materials integration at imec.

There can be InGaAs metamorphic buffer, with the MBE growth of low defect density and device quality III-V heterostructure using a suitable metamorphic buffer. Or, there can be III-Sb on Si by SS-MBE, that provides a route to relax III-V.

Defect confinement is possible via ‘necking effect’. The selective area growth (SAG) of III-V compounds via MOVPE (or CBE ?) means the defects are trapped at trench edges. The other way is dislocation trapping in narrow STI trenches for aspect ratio >2. There is low defect density material in the upper part of the trench.

Elimination of APBs for on-axis Si (001), Si recess engineering, is possible either via rounded-Ge surface or V-grooved surface. In the rounded-Ge surface, step creation is done by surface engineering of a Ge seed layer. Double steps on a Ge surface are more stable and easy to form with a lower thermal budget than on Si.

In V-grooved surface, (111) surface is obtained either by KOH or TMAH wet etching. Growth inside a pre-defined Si {111} enclosure promote initial III-V nucleation uniformity.

The ‘necking effect’ approach presents its own challenges. One, perpendicular view, where there is efficient defect necking effect with side wall and parallel view, which allows viewing high defect density.
Read more…

Round-up 2010: Best of semiconductors

December 31, 2010 2 comments

Right then, folks! This is my last post for 2010, on my favorite topic – semiconductors. If 2009 was one of the worst, if not, the worst year ever for semiconductors, 2010 seems to be the best year for this industry, what with the analyst community forecasting that the global semicon industry will surpass the $300 billion mark for the first time in its history!

Well, here’s a look at the good, the bad and the ugly, if available for otherwise what has been an excellent year, which is in its last hours, for semiconductors. Presenting a list of posts on semiconductors that mattered in 2010.

Top semiconductor and EDA trends to watch out for in 2010!

Delivering 10X design improvements: Dr. Walden C. Rhines, Mentor Graphics @ VLSID 2010

Future research directions in EDA: Dr. Prith Banerjee @ VLSID 2010 — This was quite an entertaining presentation!

Global semicon industry on rapid recovery curve: Dr. Wally Rhines

Indian semicon industry: Time for paradigm shift! — When will that shift actually happen?

Qualcomm, AMD head top 25 fabless IC suppliers for 2009; Taiwan firms finish strong!

TSMC leads 2009 foundry rankings; GlobalFoundries top challenger!

ISA Vision Summit 2010: Saankhya Labs, Cosmic Circuits are Indian start-ups to watch at Technovation 2010!

ISA Vision Summit 2010: Karnataka Semicon Policy 2010 unveiled; great opportunity for India to show we mean business! — So far, the Karnataka semicon policy has flattered to deceive! I’m not surprised, though!

Dongbu HiTek comes India calling! Raises hopes for foundry services!!

Indian electronics and semiconductor industries: Time to answer tough questions and find solutions — Reminds me of the popular song from U2 titled — “I still haven’t found what I’m looking for”!

What should the Indian semicon/electronics industry do now? — Seriously, easy to say, difficult to manage (ESDM)! ;)  Read more…

Need to develop robust Indian semicon industry, led by local companies!

December 17, 2010 1 comment

I came across an article titled “Global Semiconductor Companies Turn to India for Growth” published on India Knowledge@Wharton. Isn’t this reason why global semiconductor companies enter a specific market in the first place — to grow their own markets and regions? So, why should it be different with India?

India is very well known globally for its talent, chip design capabilities (especially in the Indian arms of the global semicon firms) and as the world’s embedded bastion!

This particular article is brilliantly written, and kudos the author. The clinching paragraph is tucked away at the end, starting with: “None of the global players, however, is currently looking at setting up a semiconductor fabrication plant, or “fab,” in India.”

What’s happened up until now in the Indian semicon industry? If one were to look at the Special Incentive Package Scheme (SIPS), which was introduced back in Sept. 2007 by the government of India, it was geared toward encouraging investments for setting up semicon fabs, and other micro and nanotechnology manufacturing industries in India!

It also defined the “ecosystem units” as units, other than a fab unit, for manufacture of semiconductors, displays including LCDs, OLEDs, PDPs, any other emerging displays; storage devices; solar cells; photovoltaics; other advanced micro and nanotechnology products; and assembly and test of all the above products.

A Karnataka Semicon Policy was announced in early Feb. 2010, during the India Semiconductor Association’s ( ISA) Vision Summit.

Next, the government of India’s thrust on solar/PV, via the Jawaharlal Nehru National Solar Mission (JN-NSM), has at least ensured the country’s solar/PV future.

What has happened since all of these policies? Really, nothing much, at least from the perspective of the Indian semicon industry. If it has, at least, I am unaware, and my apologies for this ignorance.

Of course, solar/PV seems to be going from strength to strength! Recently, NTPC Vidyut Vyapar Nigam Ltd (NVVN) put out the list of selected solar projects under the JN-NSM Phase 1, Batch 1. But that’s another story!

On this very blog, there are several posts that speak of India’s ability or inability to build a fab. At first, folks said that semicon fabs were on their way in India, and that the story isn’t disappearing. However, somewhere along the line, that particular vision took a beating and fabs simply disappeared from the Indian semicon radar! Read more…

Is the Indian semicon industry losing the plot?


Every time I see a new electronics or related segment being talked about in India — be it medical electronics/healthcare, RFID and smart cards, or for that matter, telecom, why do I get this feeling that the Indian semicon industry is slowly losing the plot? One hopes not!

The Indian technology industry is talking about practically everything, except semiconductors. Yes, I know we have a great pool of designers who work in the MNCs. Also, there are plenty of Indian design services companies doing excellent work (for others?). India’s strength in embedded is folk lore. Despite all of this, we are, where we were a few years ago!

Back in 2007, I’d done a story on how there were very remote chances of having a fab in India. Back then, some industry folks expressed  optimism that the fab story was not dead! However, that story is well and truly dead and buried, as of now! Today, no one wants to talk about a fab — fine, then!

Let’s do a reality check on India’s semiconductor score-card!

So far, India has not even managed to have a small foundry, forget about having a fab! Nor has the Indian industry managed to develop, nurture and build many (or any?) fabless companies of note. Can you tell me how many Indian fabless semicon companies have come up in the past five years? How many globally known Indian semicon product start-ups are there in our country for that matter? Okay, how many Indian semicon product start-ups are there in our country?

For that matter, how many ATMP units have come up in India? I do recall some industry folks mention in the past that there will be some ATMP units happening. Where are they? Okay, who, in India, is even trying to develop IP libraries?

Even if there is some success in building electronic product companes — that is and will be limited success! Neither is there any evidence of cutting-edge R&D being done in India. Please do not mix this up with the work being done by the Indian arms of the various MNCs.

Why, I don’t even think that the industry-academia partnership has developed substantially, leave alone mature!

If medical electronics, or some other related area, were to go on and succeed in the near future, it would be counted as a success for the Indian electronics industry, and not for the Indian semicon industry! Even if this did happen and it was counted as a ‘semicon success, can anyone make a guess as to how many of the chips going into such devices would be actually made in India – by Indian firms?

I had mentioned back in Feb. 2009  that “Can the Indian semicon industry dream big? (And even buy Qimonda?)! To refresh your memory, there was a large 300mm fab up for sale in Dresden, Germany. Well, even that never happened, or well, the Indian industry did not think it to be of much importance!

Back in August 2009, there was news about Texas Instruments (TI) placing a bid of $172.5 million for buying Qimonda’s 300mm production tools from its closed DRAM fab. While this highlighted TI’s focus on building the world’s first 300mm analog fab, I can’t stop wondering: what would have happened had an Indian investor actually bought Qimonda’s fab!

Perhaps, it would be better for the Indian semicon industry to stick to its globally known strengths of providing excellent semiconductor design services and embedded design services. At least, there will be clear direction in these areas.

Of course, there exist huge opportunities in all of the areas (or gaps) that I’ve touched upon.

This downturn was NOT a classic semiconductor bust and boom, ignore industry fundamentals at your peril: Future Horizons


According to Malcolm Penn, chairman and CEO, Future Horizons, May’s semiconductor sales were up 2.6 percent on April, 3.6 percent for ICs, continuing the steady sequential industry growth that started in January 2009, 17 months ago.

May’s results mean Q2-10 will show at least 8.3 percent quarterly growth over Q1-10, increasing the full year growth forecast to 36 percent. Given last year’s growth was minus 9 percent, mathematically this is a classic industry cycle. It is NOT, he insists.

At this point in the ‘recovery’, it is much more important to look at sequential and quarterly growth rates rather that the 12:12 rates, given the high double digit rates they show are just as misleading and irrelevant as the high double digit negative rates from this time last year.  The reality is they net each other out thereby highlighting the real nature of the current cycle.  This downturn was a pause, the recovery a restart, it was NOT a classic semiconductor bust and boom.

Future Horizons has been telling everyone very publicly that the industry recovery started in March 2009, first in the April 2009 edition of its Global Semiconductor Report, substantiated by a very long and detailed analysis at the Geneva IEF2009 Forum last October.

The recovery, together with ever-increasing substantiating data, has been a recurring theme in its  Global Semiconductor Monthly Report ever since, as well as at the Dresden IEF2010 event in May 2010.

Penn added: “At the same time I have been warning that industry was cutting back existing capacity far too much and too fast whilst simultaneously failing to invest in net new capacity. Our clear message always was that these two factors were a recipe for disaster. The disasters are now starting to happen.

“While we obviously do not expect firms to run their business based on what we say, if the market recovery really has taken firms by surprise, executives from the top down either failed to recognise the significance of the data we were drawing their attention to over the past 15 months or they simply made the decision to ignore it. Ignore the industry fundamentals at your peril.”

Recovery not quite classic!
Future Horizons clearly states that this recovery is not a classic recovery. On being quizzed further, Penn said, “it was a dead stop and restart, just like hitting the pause button on your remote, rather than a crash and rebuild.” This is perhaps the same reason why the recession is now being termed as a market interruption.

Future Horizons has also been warning that industry was cutting back on the existing capacity far too much and too fast, while simultaneously failing to invest in net new capacity. Is the semicon industry still on this path?

Penn added: “Spending has now resumed (since Jan. 2010) and cut backs have stopped, but there’s a one-year time delay before these will start to impact. Why? Lack of industry confidence, driven too much by short-term financial performance, risk averse management and shareholders, lemming factor, etc.”

The long-term ramifications, should the industry fail to invest in net new capacity, are loss of sales and market position/leadership to those firms who did invest (e.g. TSMC, Samsung).

Well, it seems the global semiconductor industry has not learned enough from the previous recessions! Read more…

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