FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.
There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.
Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).
Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.
In addressing power/performance challenges, 20SoC is said to be the quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC process is the first 32Gbps transceivers that are operating in 20nm silicon.
Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate
surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.
Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.
Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.
At the ISA CXO Conclave, Matt Grob, SVP, corporate R&D, Qualcomm, said that the company is a world leader in next-generation mobile technologies. It is celebrating 25 years of driving the evolution of wireless communications. It is making wireless more personal, affordable and accessible to people everywhere. Qualcomm is also the world’s largest fabless semiconductor company, #1 in wireless, and #9 in semiconductors.
Qualcomm’s unique business model is to be a technology enabler for the entire mobile value chain. It has continued strategic R&D investments, totalling more than $15.4 billion in 2010.
The 2G to 3G migration is currently taking place, with over 3.1 billion 3G subscriptions likely in 2015. As for the emerging region growth, China leads with 640 percent, followed by Latin America at 465 percent and India at 168 percent, respectively.
Qualcomm is also said to be enabling the mobile broadband in India with 3G and LTE. Besides growing the LTE TDD ecosystem in region, it is building partnerships for long-term strategy and establishing 3G/LTE as best technology path for operators. Qualcomm is also driving the device evolution and growing the market by creating more choices for operators and consumers. It is developing low-cost 3G handsets for emerging markets using 1+ GHz mobile processors and supporting multiple popular OS.
The smartphone industry momentum has ensured that the ecosystem is benefitting from and driving growth. There has been as much as >25 percent YoY data revenue growth from leading operators. OEMs have launched 100+ new smartphones in the first half of CY 2010. The total mobile apps downloads from developers is likely to move up from 7 billion in 2009 to 50 billion by 2012.
As a follow-on to his April 2010 global semiconductor forecast numbers, Mike Cowan constructed (and updated) a table (sourced from the GSA website in order to compare the latest 2010 sales growth forecasts from a large number of leading market researchers to his latest sales growth forecast estimate of 33.4 percent.
Notice that for the thirteen (13) yellow-highlighted market researchers shown in the attached table (including mine), 12 of the market watchers have increased their most recent forecast year-over-year sales growths to a range of 22.6 percent to 33.4 percent with a mean sales growth forecast of 28.7 percent (28.4 percent without Cowan’s forecast number).
As revealed in the table, Cowan’s most recent 2010 sales growth forecast estimate is the most bullish of the bunch (at least for this month; stay tuned for my monthly forecast numbers as the year plays out!).
Also note that the just published (last week – June 8 and 10, respectively), WSTS and SIA Spring 2010 forecast sales growth results for 2010 are included in the table.
This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as:
* Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution.
* No or very low investment in building better verification environments (based on best/new methodologies and best practices); instead maintaining older verification environments.
* Compromising on verification completeness because of tape out pressures and time-to-market considerations.
Would you agree that many companies STILL do not know how to verify a chip?
He said that it could be true for smaller companies or start-ups, but most of the major semiconductor design engineers know about the better approaches/methodologies to verify their chips. However, they may not be investing in implementing the new methodologies for multiple reasons and may instead continue to follow the traditional flows.
One way to address these mistakes would be to set up strong methodology teams to create a better verification infrastructure for future chips. However, few companies are doing this.
Are companies realizing this and building an infrastructure that gets you business advantage? He added that some companies do realize this and are investing in building a better infrastructure (in terms of better methodology and flows) for verification.
When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment? Ghosh said that good verification starts as soon as we start designing and architecting the design. Verification leads should start discussing the verification environment components with the lead architect and also start writing the verification plan.
Are folks mistaking by looking at tools and not at the verification process itself? According to him, tools play a major role in the effectiveness of any verification process, but we still see a lot of scope in methodology improvements beyond the tools.
What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities? Ghosh said that there is no single, full-proof recipe for a ‘right’ verification path. It depends on multiple factors, including whether the design is a new product or derivative, the design application etc. But yes, it is very important to do comprehensive verification planning before starting the verification process.
Synopsys is said to be building a comprehensive, unified and integrated verification environment is required for today’s revolutionary SoCs and would offer a fundamental shift forward in productivity, performance, capacity and functionality. Synopsys’ Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.
Verification Compiler includes:
* Better capacity and compile and runtime performance.
* Next-generation static and formal technology delivering performance improvement and the capacity to analyze a complete SoC (Property checking, LP, CDC, connectivity).
* Comprehensive low power verification solution.
* Verification planning and management.
* Next-generation verification IP and a deep integration between VIP and the simulation engine, which in turn can greatly improve productivity. The constraint engine is tuned for optimal performance with its VIP library. It has integrated debug solutions for VIP so one can do protocol-level analysis and transaction-based analysis with the rest of the testbench.
* Support for industry standard verification methodologies.
* X-propagation simulation with both RTL and low power simulations.
* Common debug platform with better debug technology having new capabilities, tight integrations with simulation, emulation, testbench, transaction debug, power-aware debug , hw/sw debug, formal, VIP and coverage.
Top five recommendations for verification
What would be Synopsys’ top five recommendations for verification?
* Spend a meaningful amount of time and effort on verification planning before execution.
* Continuously invest in building a better verification infrastructure and methodologies across the company for better productivity.
* Collaborate with EDA companies to develop, evaluate and deploy new technologies and flows, which can bring more productivity to verification processes.
* Nurture fresh talent through regular on and off-the-job trainings (on flows, methodologies, tools, technology).
* Conduct regular reviews of the completed verification projects with the goal of trying to improve the verification process after every tapeout through methodology enhancements.
Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry.
Global semicon in sub 20nm era
How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the history of mankind is not for the faint of heart. Keeping up with Moore’s Law has always required significant investment and ingenuity.
“The sub-20nm era brings additional challenges in device structures (namely FinFETs), materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over the revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception.
“Semiconductor companies focused on mobile and the Internet of Things are also thriving as their market quickly expands. Semiconductor companies who dominate their space in such segments as automotive, mil/aero and medical are also doing quite well, while non-leaders find rough waters.”
Performance of FinFETs
Have FinFETs gone to below 20nm? Also, are those looking for power reduction now benefiting?
He added that 20nm was a pivotal point in advanced process development. The 20nm process node’s new set of challenges, including double patterning and very leaky transistors due to short channel effects, negated the benefits of transistor scaling.
To further complicate matters, the migration from 28nm to 20nm lacked the performance and area gains seen with prior generations, making it economically questionable. While planar FET may be nearing the end of its scalable lifespan at 20nm, FinFETs provide a viable alternative for advanced processes at emerging nodes.
The industry’s experience with 20nm paved the way for an easier FinFET transition. FinFET processes are in production today, and many IC design companies are rapidly moving to manufacture their devices on the emerging 16nm and 14nm FinFET-based process geometries due to the compelling power and performance benefits. Numerous test chips have taped out, and results are coming in.
“FinFET is delivering on its promise of power reduction. With 20nm planar FET technologies, leakage current can flow across the channel between the source and the drain, making it very difficult to completely turn the transistor off. FinFETs provide better channel control, allowing very little current to leak when the device is in the “off” state. This enables the use of lower threshold voltages, resulting in better power and performance. FinFET devices also operate at a lower nominal voltage supply, significantly improving dynamic power.”
Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.
Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.
Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.
“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”
When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.
Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.
The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.
Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.
Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.
FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?
Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.
Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.