Intel launches Xeon processor E5-2600 product family

Intel Xeon processor E5-2600 product family.

Following its global launch yesterday, Intel Corp. today announced the record-breaking Intel Xeon processor E5-2600 product family in Bangalore, India. R. Ravichandran, director, Sales & World Ahead Program – Asia, Intel Technology India Pvt Ltd, said that the Xeon processor:
* Allows 80 percent performance gain.
* Uses breakthrough I/O innovation.
* Makes use of Trusted Security.
* Provides best data center performance per watt.

Intel has integrated the I/O, which reduces latency by 30 percent. The Xeon E5-2600 processor also has PCI Express 3.o as well as the Intel Data Direct I/O. Overall, the I/O bandwidth is said to improve 3X over the previous generation.

The new chip’s energy efficiency has also increased by 50 percent.  As for Trusted Security, there is the Intel TXT and the Intel AES-NI. The Xeon processor is meant for server, storage and network.

Xilinx starts shipping Zynq-7000 EPP family!

(L-R): Dave Tokic and Lawrence Getman.

Xilinx Inc. has announced its first Zynq-7000 Extensible Processing Platform (EPP) shipments to customers. It showcased the first public demonstration of a Zynq-7000 EPP at the ARM European Technical Conference, in Paris, France. where attendees saw the device running a Linux-based application. Xilinx has recently started shipping Zynq, to at least three customers.

The Zynq-7000 family is the world’s first EPP. It combines an industry-standard ARM dual-core Cortex-A9 MPCore processing system with Xilinx 28nm unified programmable logic architecture. This processor-centric architecture delivers a complete embedded processing platform that offers developers ASIC levels of performance and power consumption, the flexibility of an FPGA and the ease of programmability of a microprocessor.

Dave Tokic, senior director, partner Ecosystems and Alliances, said the company had made a number of investments. It has adopted a two-pronged approach: focusing on how it developed the ecosystem, and what it could do by itself. ”We need a tool flow applicable across all customers. Our technologies are enabling much more complex designs. We are also raising the bar for the EDA providers. We do provide early access to our tools, etc.”

Tokic added that the company has also invested a lot in training and certification in India. “Our partners are some very good companies. We have 24 members in our program. Eight of those are certified members.” Some of the partner companies include Wipro, TCS, Corel, Mistral, CMC, GDA Technologies (L&T), Mechatronics, etc.

Lawrence Getman, VP of Processing Platforms, added that Xilinx has been seeing how to potentially leverage a cloud. “We are continuing to develop the IP ecosystem. We are also looking to engage expert service needs.”

Commenting on developments, Getman said that Xilinx’s Virtex-7 series FPGAs are based on the high performance low power (HPL) process by TSMC. Xilinx wants to foster more collaborative approach in future for acquiring and working with customers.

SanDisk’s iNAND Extreme family of embedded eMMC storage devices for high-end mobile and tablets

SanDisk Corp.’s embedded storage is in most of all top computing device brands. It recently launched the iNAND Extreme family of embedded eMMC storage devices for high-end mobile and tablets.

Gadi Ben-Gad, product marketing manager, SanDisk.

Gadi Ben-Gad, product marketing manager for SanDisk, said: “This very high performance line of iNAND products joins the existing iNAND and iNAND Ultra lines, which are very successful in the mobile, tablet and consumer electronics markets. The first generation of these products (iNAND Extreme) will be sampling in a few weeks.

“iNAND Extreme products offer up to 50MB/s write and 80MB/s read sequential performance and very high random performance designed for the next generation of high-end mobile and tablet devices. SanDisk continues to monitor market trends and requirements and diversifying the embedded offering in the market, to answer to the different requirements of the different mobile, tablet and consumer electronics segments.”

So, how will SanDisk play a strong role in these areas? According to Ben-Gad, SanDisk works closely with a broad and diverse set of mobile and tablet OEMs. The company also works very closely with the majority of the leading mobile chipset vendors and standardization bodies in the mobile/tablet ecosystem to ensure optimal integration and technological support.

He added: “SanDisk is a fully vertically integrated company with substantial expertise in NAND flash technology, system technology and product design with years of experience in designing embedded and removable mobile storage devices. SanDisk is very well-positioned to understand, develop and support the future storage requirements in mobile, tablet and consumer electronics devices.”

Finally, I must thank Ms. Jody Privette Young, LymanPR, for making this happen.

Xilinx intros Zynq-7000 family of extensible processing platform (EPP)

Xilinx's Zync-7000 series.

Xilinx Inc. has unveiled the Zynq-7000 family, the industry’s first Extensible Processing Platform (EPP). It is supported by an extensive ecosystem of tools and IP providers.

According to Tim Erjavec, senior director, platform soluutions and service marketing, the Zynq-7000 family tightly integrates a complete ARM Cortex-A9 MPCore processor-based system with 28nm, low-power programmable logic for system architects and embedded software developers to extend, customize, optimize, and differentiate their systems.

Back in April 2010, Xilinx had announced a new class of devices featuring an extensible processing platform and a processor-centric solution. Now, in March 2011, the first Xilinx EPP family and brand has been announced.

Embedded designers are said to be asking for more. There will be a combined market of $12,74 billion by 2014, featuring automotive driver assistance, intelligent video surveillance, industrial control, telemetry and guidance, enterprise femtocell, broadcast cameras, multifunction printers, aerospace avionics, etc.

Zynq-7000 device portfolio includes the 7010, 7020, 7030 and 7040. These have faniliar design environments, familiar software programming model, familiar hardware design flow, besides flexible accelerators and IP such as common AXI-4 interface and a broad ecosystem featuring tools, OSs and IPs.

Zynq-7000 family highlights include a complete ARM processing system, featuring a dual ARM Cortex-A9 and ontegrated memory controllers and peripherals. A tightly integrated programmable logic extends the processing system, scalable density and performance and features over 3000 internal interconnects. There is also a flexible array of I/O, featuring a wide range of external multi standard I/O, high performance integrated serial tranceivers, and ADC inputs.

Built with state-of-the-art 7 series programmable logic featuring 430K to 3.5 million equivalent ASIC gates and 30K-235K logic cells. It also enables massive parallel processing with up to 760 DSP engines delivering over 910 GMACs.

The flexible internal I/O includes 54 processor I/Os, 350 multi-standard and high performance I/Os, flexible memory interfaces and high performance untegrated serial tranceivers.

A wide range of Zync-7000 applications are supported, such as driver assistance, factory automation, broadcast camera, smart surveillance systems, consumer equipment, AVB routers, switches and cameras, and military radios and medical imaging.

The Zync-7000 software development environment includes the ARM development environment. ARM ecosystem support and other, vast off-the-shelf software and libraries. The hardware design environment includes the Xilinx ISE Development Suite, plug and play IP portfolio, hardware abstraction layer, and drivers and APIs.

The Zync program status includes the early access program open with over 200 applicants, with the ISE 13.1 Development Suite and the emulation platform. Initial devices are said to be available by 2H 2011. Some of the publically announced Zynq early access customers include Agilent, iVeia, National Instruments, etc.

Lattice intros Platform Manager family

Lattice's Platform Manager.

Lattice Semiconductor Corp. has introduced the Platform Manager family — its third-generation mixed-signal devices.

Lattice’s Platform Manager product family consists of two devices — the LPTM10-1247 and the LPTM10-12107, respectively. The LPTM10-1247 device monitors 12 voltage rails and supports 47 digital I/Os. The LPTM10-12107 device monitors up to 12 voltage rails and supports 107 digital I/Os.

The programmable devices will simplify board management design significantly by integrating programmable analog and logic to support many common functions, such as power management, digital housekeeping and glue logic.

By integrating these support functions, Platform Manager devices reduce the cost of these functions compared to traditional approaches, and improves system reliability. It  provides a high degree of design flexibility that minimizes the risk of circuit board re-spins.

More to follow.

Altera intros 28nm Stratix V FPGA family

Altera Corp. has introduced its next-generation 28nm Stratix V FPGA family, said to be the industry’s highest bandwidth FPGA. Offering up to 1.6 Tbps of serial switching capability, Stratix V FPGAs leverage a myriad of new technologies and a leading-edge 28nm process to reduce the cost and power of high-bandwidth applications.

Gangatharan Gopal, country sales manager and office manager for Altera India, announces the Stratix V FPGAs.

Manufactured on TSMC’s 28nm high-performance (HP) process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18×18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps.

Gangatharan Gopal, country sales manager and office manager for Altera India,  said that the FPGAs are suitable for devices used in next-generation high bandwidth systems. According to Altera, these offer 35 percent higher performance than alternative process options, as well as 30 percent lower total power versus other generations. These also enable the fastest and most power efficient transceivers.

He pointed out that Altera has been delivering innovations from the core to the I/O that provide higher system performance at lower cost and power.

Altera’s 28nm Stratix V FPGAs are said to have broken through the bandwidth barrier. The company is  also said to be dramatically improving the density and I/O performance of the FPGAs, and further strengthening their competitive position versus ASICs and ASSPs.

Altera’s devices incorporate the industry’s highest level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty.

The FPGA family itself includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets. These variants include:

* Stratix V GT FPGA – Industry’s only FPGA with integrated 28-Gbps transceivers targeting 100G systems and beyond.
* Stratix V GX FPGA – Supports a wide range of applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V GS FPGA – Optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V E FPGA – Highest density FPGA ideal for ASIC prototyping, emulation or high-performance computing applications.

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”

Optimizing Ethernet networks for mobile access and cloud service delivery

Uday Mudoi.

Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).

Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.

Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.

ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.

ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.

Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.

The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.

Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure
network for L2 VPN services at 50 percent lower cost than alternative solutions.

Tensilica to expand Cadence IP footprint in SoCs

Chris Rowan.

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.

Now, I’m on Wikipedia! ;) Thanks everyone!! :)

Today is Holi, the festival of colors. Well, it added some more color to my life as I was told that I have been listed on Wikipedia! You can see it here!

I don’t really know who has added me there, or where they are getting all of their information. All I can humbly say is: thanks a lot, very sincerely, to Wikipedia!

Wikipedia has said I’ve been staying at my Delhi residence since 1984! Well, that’s the year my father, late, Pramode Ranjan Chakraborty, bought this house. Later, in 1986, he, along with my mother, late Mrs Bina Chakraborty, moved to this house.

Why this huge gap in our buying the house and moving in? Well, not many folks know that my parents met with a near fatal accident on Jan. 27, 1986 in the early hours of the day at New Delhi. They were going home by an auto-rickshaw to our home at Greater Kailash-II, New Delhi, when an Ambassador car rammed into their auto-rickshaw full on!

That’s also the day my life changed completely! I was still a student, playing cricket with friends, when my aunt called us from Delhi. We rushed to Delhi, to find our parents badly injured! I personally had to say goodbye to cricket, and turned attention to finding work to somehow run the family! I finally moved to Delhi in Nov. 1987, and that’s where my so-called ‘professional’ life started!

It has been a great ride ever since! All the hard work done seems to have paid off. First, I must mention Gratian Vas, who took me in at Holy Faith International back in 1988. My first brush with electronics was at SBP Consultants & Engineers a year later, followed by Electronics For You. However, it was at DiSyCom magazine, under Arun Bhattacharjee, where I learned the ropes.

Later, I was hired by late Ms Rashmi Bhushan to write for electronic components magazine published by Asian Sources Media. That’s when my life changed significantly! Not only did Asian Sources Media, now, Global Sources, hire me as the full-time telecom editor  and take me to Hong Kong, it gave me first-hand view of China and how it grew in the world of electronics! It has been a fascinating journey ever since!

Thereafter, it was at Reed Elsevier, in Singapore, where I had the late Ian Shelley, Michael Tan, Paul Beh and Swee Heng Tan for company. Everywhere, I learned a lot! That’s what I continue to do even today!

The world can give me as many awards and folks can call me anything, but I shall always remain, yours truly!