Following its global launch yesterday, Intel Corp. today announced the record-breaking Intel Xeon processor E5-2600 product family in Bangalore, India. R. Ravichandran, director, Sales & World Ahead Program – Asia, Intel Technology India Pvt Ltd, said that the Xeon processor:
* Allows 80 percent performance gain.
* Uses breakthrough I/O innovation.
* Makes use of Trusted Security.
* Provides best data center performance per watt.
Intel has integrated the I/O, which reduces latency by 30 percent. The Xeon E5-2600 processor also has PCI Express 3.o as well as the Intel Data Direct I/O. Overall, the I/O bandwidth is said to improve 3X over the previous generation.
The new chip’s energy efficiency has also increased by 50 percent. As for Trusted Security, there is the Intel TXT and the Intel AES-NI. The Xeon processor is meant for server, storage and network.
Xilinx Inc. has announced its first Zynq-7000 Extensible Processing Platform (EPP) shipments to customers. It showcased the first public demonstration of a Zynq-7000 EPP at the ARM European Technical Conference, in Paris, France. where attendees saw the device running a Linux-based application. Xilinx has recently started shipping Zynq, to at least three customers.
The Zynq-7000 family is the world’s first EPP. It combines an industry-standard ARM dual-core Cortex-A9 MPCore processing system with Xilinx 28nm unified programmable logic architecture. This processor-centric architecture delivers a complete embedded processing platform that offers developers ASIC levels of performance and power consumption, the flexibility of an FPGA and the ease of programmability of a microprocessor.
Dave Tokic, senior director, partner Ecosystems and Alliances, said the company had made a number of investments. It has adopted a two-pronged approach: focusing on how it developed the ecosystem, and what it could do by itself. ”We need a tool flow applicable across all customers. Our technologies are enabling much more complex designs. We are also raising the bar for the EDA providers. We do provide early access to our tools, etc.”
Tokic added that the company has also invested a lot in training and certification in India. “Our partners are some very good companies. We have 24 members in our program. Eight of those are certified members.” Some of the partner companies include Wipro, TCS, Corel, Mistral, CMC, GDA Technologies (L&T), Mechatronics, etc.
Lawrence Getman, VP of Processing Platforms, added that Xilinx has been seeing how to potentially leverage a cloud. “We are continuing to develop the IP ecosystem. We are also looking to engage expert service needs.”
Commenting on developments, Getman said that Xilinx’s Virtex-7 series FPGAs are based on the high performance low power (HPL) process by TSMC. Xilinx wants to foster more collaborative approach in future for acquiring and working with customers.
Lattice Semiconductor Corp. has introduced the Platform Manager family — its third-generation mixed-signal devices.
Lattice’s Platform Manager product family consists of two devices — the LPTM10-1247 and the LPTM10-12107, respectively. The LPTM10-1247 device monitors 12 voltage rails and supports 47 digital I/Os. The LPTM10-12107 device monitors up to 12 voltage rails and supports 107 digital I/Os.
The programmable devices will simplify board management design significantly by integrating programmable analog and logic to support many common functions, such as power management, digital housekeeping and glue logic.
By integrating these support functions, Platform Manager devices reduce the cost of these functions compared to traditional approaches, and improves system reliability. It provides a high degree of design flexibility that minimizes the risk of circuit board re-spins.
More to follow.
Manufactured on TSMC’s 28nm high-performance (HP) process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18×18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps.
Gangatharan Gopal, country sales manager and office manager for Altera India, said that the FPGAs are suitable for devices used in next-generation high bandwidth systems. According to Altera, these offer 35 percent higher performance than alternative process options, as well as 30 percent lower total power versus other generations. These also enable the fastest and most power efficient transceivers.
He pointed out that Altera has been delivering innovations from the core to the I/O that provide higher system performance at lower cost and power.
Altera’s 28nm Stratix V FPGAs are said to have broken through the bandwidth barrier. The company is also said to be dramatically improving the density and I/O performance of the FPGAs, and further strengthening their competitive position versus ASICs and ASSPs.
Altera’s devices incorporate the industry’s highest level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty.
The FPGA family itself includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets. These variants include:
* Stratix V GT FPGA – Industry’s only FPGA with integrated 28-Gbps transceivers targeting 100G systems and beyond.
* Stratix V GX FPGA – Supports a wide range of applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V GS FPGA – Optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V E FPGA – Highest density FPGA ideal for ASIC prototyping, emulation or high-performance computing applications. Read more…
NXP Semiconductors N.V. recently released the LPC1500 microcontroller series, optimized for fast, easy, and high-precision motor control.
So, what’s unique about the new LPC family? First, the LPC1500 was designed to simplify motor control for the masses. It has the flexibility to drive various types of motors, such as ACIM, PMSM, BLDC, etc. The LPC1500 can also drive multiple motors simultaneously.
These aren’t all! The hardware interconnection between the SCTimer/PWM, ADCs and comparators allow the motor to be driven with little CPU intervention. It has free LPCXpresso IDE and free FOC firmware for sensored and sensorless motors that reduces cost and improves time to market.
Looking at the unique features and benefits, the Switch Matrix allows any function to be routed out to any pin making schematic capture and board layout simpler and faster. The SCTimer/PWM block is unique to NXP.
Benefits are, it can run independently of the CPU and generate extremely precise PWM waveforms for quiet, smooth, efficient motor drive. The 2x 2Msps 12b,12ch ADCs can measure simultaneous phase currents to determine precise motor position and speed. There are four comparators for fast system shutdown upon fault detection.
The LPC1500 is suitable for large appliances, HVAC, building automation, factory automation, industrial pumps and generators, digital power, remote sensing, etc.
How will the LPC1500 aid embedded engineers? According to NXP, it saves time to market using the free FOC firmware and GUI tuning tool. It also saves system cost by using only one system MCU, e.g., HVAC typically has one MCU for fan control and one MCU for the compressor. LPC1500 can control both.
The LPC1500 feature set makes it ideal for sensorless motor control removing the need for sensored motors and allowing customers to switch to cheaper sensorless motors. As the SCTimer/PWM can run independently of the CPU, the freed up CPU bandwidth can be used to control other parts of the system for example the LPC1500 can be used for both the control and motor board in a washing machine.
NXP is currently working with customers to understand their future requirements and developing the roadmap to match their needs.
Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.
Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.
“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”
Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.
* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.
* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.
KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.
There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.
Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”
The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.
There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite.
UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.
Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.
Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.
“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”
The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.
UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.
Texas Instruments has been a leader in DLP or digital light processing, a type of projector technology that uses a digital micromirror device. Kent Novak, senior VP, DLP Products, Texas Instruments (TI) mentioned that DLP became the no. 1 supplier of MEMS technology in 2004.
The DLP pico projectors business started in 2009. Now, pico is going into gaming systems, etc. In 2011, it went into the cinema industry. In India, out of 10,000 screens, close to 7,000 are now digital. In 2012, new DLP development kit was launched allowing developers to embed the DLP chip into non-traditional applications in new markets. In 2013, TI started working on DLP automotive chips.
He said: “DLP is an array of millions of digital micromirrors. We ship around 45 million devices. We see India as a growth opportunity for cimemas. In DLP front projection business, we have 60 percent share in India. Only 5 percent of Indian classrooms have projectors, making room for growth.”
In low power pico projection, TI has 95 percent market share in India for standalone pico projection. A phone with pico projection was launched in India with iBall at 35 lumen.
DLP technology is available in India in:
Industrial: Machine vision can improve quality control in the Indian manufacturing sector.
Medical: Intelligent illumination systems for cost effective blood analysis.
Safety: Cost effective, accurate chemical analysis of food and industrial.
Automotive: Infotainment and safety solution being qualified.
DLP in automotive displays has several applications, such as wide field of view head up display (HUD) – app available by 2016, free shape interactive active console – app available by 2017, and smart headlights. Some other features include:
* High image quality: consistent contrast, brightness over lamp.
* Full, deep, accurate cover over lifetime.
* Easily enlarges larger display areas.
* High power efficiency.
* DLP technology automatically reduces reflection.
New market opportunities
There are said to be several new opportunities for DLP. These are in:
Industrial: Machine vision, spectroscopy, interactive display, 3D printing, intelligent lighting, digital light exposure.
Infotainment: Mobile phones, tablets, camcorders, laptops, mobile projection, ultra slim TVs.
Gaming: Dual console gaming, interactive gaming, near eye display.
Digital signage: Interactive surface, storefront interactive, retail engagement.
Automotive: Head up display, interactive display, intelligent lighting.
Medical: Spectroscopy, 3D printing, intelligent lighting.
TI has DLP LightCrafter family of evaluation modules. It enables faster development cycles for end equipment requiring smalll form factor, lower cost and intelligent, high-speed pattern display. The DLP LightCrafter 4500 features the 0.45 WXGA chipset. The DLP chip can enable new and innovative intelligent display apps. If your solution uses, programs or senses light, DLP could be a fit.
DLP catalog offers programmable, ultra-high speed pattern. “DLP is light source agnostic. We use whatever’s most efficient for brightness,” he added.
The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:
Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.
Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.
Now, this is excellent news for everyone interested in the Indian semiconductor industry.
One look at the numbers above tell me – NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let’s examine!
As you can probably see, both the projects have placed 22nm right at the very last phase! That’s very interesting!
Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel’s Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!
For discussion’s sake, let’s say, a fab in India comes up by say, early 2015. Let’s assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn’t it? Where will the rest of the global industry be by then?
You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members. What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE’s Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY’s College of Nanoscale Science and Engineering!
So, what does all of this tell me?
One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space! Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!
Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop!
Perhaps, these product lines will be good for India and serve well, for now, but not for long!