Following its global launch yesterday, Intel Corp. today announced the record-breaking Intel Xeon processor E5-2600 product family in Bangalore, India. R. Ravichandran, director, Sales & World Ahead Program – Asia, Intel Technology India Pvt Ltd, said that the Xeon processor:
* Allows 80 percent performance gain.
* Uses breakthrough I/O innovation.
* Makes use of Trusted Security.
* Provides best data center performance per watt.
Intel has integrated the I/O, which reduces latency by 30 percent. The Xeon E5-2600 processor also has PCI Express 3.o as well as the Intel Data Direct I/O. Overall, the I/O bandwidth is said to improve 3X over the previous generation.
The new chip’s energy efficiency has also increased by 50 percent. As for Trusted Security, there is the Intel TXT and the Intel AES-NI. The Xeon processor is meant for server, storage and network.
Xilinx Inc. has announced its first Zynq-7000 Extensible Processing Platform (EPP) shipments to customers. It showcased the first public demonstration of a Zynq-7000 EPP at the ARM European Technical Conference, in Paris, France. where attendees saw the device running a Linux-based application. Xilinx has recently started shipping Zynq, to at least three customers.
The Zynq-7000 family is the world’s first EPP. It combines an industry-standard ARM dual-core Cortex-A9 MPCore processing system with Xilinx 28nm unified programmable logic architecture. This processor-centric architecture delivers a complete embedded processing platform that offers developers ASIC levels of performance and power consumption, the flexibility of an FPGA and the ease of programmability of a microprocessor.
Dave Tokic, senior director, partner Ecosystems and Alliances, said the company had made a number of investments. It has adopted a two-pronged approach: focusing on how it developed the ecosystem, and what it could do by itself. ”We need a tool flow applicable across all customers. Our technologies are enabling much more complex designs. We are also raising the bar for the EDA providers. We do provide early access to our tools, etc.”
Tokic added that the company has also invested a lot in training and certification in India. “Our partners are some very good companies. We have 24 members in our program. Eight of those are certified members.” Some of the partner companies include Wipro, TCS, Corel, Mistral, CMC, GDA Technologies (L&T), Mechatronics, etc.
Lawrence Getman, VP of Processing Platforms, added that Xilinx has been seeing how to potentially leverage a cloud. “We are continuing to develop the IP ecosystem. We are also looking to engage expert service needs.”
Commenting on developments, Getman said that Xilinx’s Virtex-7 series FPGAs are based on the high performance low power (HPL) process by TSMC. Xilinx wants to foster more collaborative approach in future for acquiring and working with customers.
Lattice Semiconductor Corp. has introduced the Platform Manager family — its third-generation mixed-signal devices.
Lattice’s Platform Manager product family consists of two devices — the LPTM10-1247 and the LPTM10-12107, respectively. The LPTM10-1247 device monitors 12 voltage rails and supports 47 digital I/Os. The LPTM10-12107 device monitors up to 12 voltage rails and supports 107 digital I/Os.
The programmable devices will simplify board management design significantly by integrating programmable analog and logic to support many common functions, such as power management, digital housekeeping and glue logic.
By integrating these support functions, Platform Manager devices reduce the cost of these functions compared to traditional approaches, and improves system reliability. It provides a high degree of design flexibility that minimizes the risk of circuit board re-spins.
More to follow.
Manufactured on TSMC’s 28nm high-performance (HP) process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18×18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps.
Gangatharan Gopal, country sales manager and office manager for Altera India, said that the FPGAs are suitable for devices used in next-generation high bandwidth systems. According to Altera, these offer 35 percent higher performance than alternative process options, as well as 30 percent lower total power versus other generations. These also enable the fastest and most power efficient transceivers.
He pointed out that Altera has been delivering innovations from the core to the I/O that provide higher system performance at lower cost and power.
Altera’s 28nm Stratix V FPGAs are said to have broken through the bandwidth barrier. The company is also said to be dramatically improving the density and I/O performance of the FPGAs, and further strengthening their competitive position versus ASICs and ASSPs.
Altera’s devices incorporate the industry’s highest level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty.
The FPGA family itself includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets. These variants include:
* Stratix V GT FPGA – Industry’s only FPGA with integrated 28-Gbps transceivers targeting 100G systems and beyond.
* Stratix V GX FPGA – Supports a wide range of applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V GS FPGA – Optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V E FPGA – Highest density FPGA ideal for ASIC prototyping, emulation or high-performance computing applications. Read more…
Texas Instruments has been a leader in DLP or digital light processing, a type of projector technology that uses a digital micromirror device. Kent Novak, senior VP, DLP Products, Texas Instruments (TI) mentioned that DLP became the no. 1 supplier of MEMS technology in 2004.
The DLP pico projectors business started in 2009. Now, pico is going into gaming systems, etc. In 2011, it went into the cinema industry. In India, out of 10,000 screens, close to 7,000 are now digital. In 2012, new DLP development kit was launched allowing developers to embed the DLP chip into non-traditional applications in new markets. In 2013, TI started working on DLP automotive chips.
He said: “DLP is an array of millions of digital micromirrors. We ship around 45 million devices. We see India as a growth opportunity for cimemas. In DLP front projection business, we have 60 percent share in India. Only 5 percent of Indian classrooms have projectors, making room for growth.”
In low power pico projection, TI has 95 percent market share in India for standalone pico projection. A phone with pico projection was launched in India with iBall at 35 lumen.
DLP technology is available in India in:
Industrial: Machine vision can improve quality control in the Indian manufacturing sector.
Medical: Intelligent illumination systems for cost effective blood analysis.
Safety: Cost effective, accurate chemical analysis of food and industrial.
Automotive: Infotainment and safety solution being qualified.
DLP in automotive displays has several applications, such as wide field of view head up display (HUD) – app available by 2016, free shape interactive active console – app available by 2017, and smart headlights. Some other features include:
* High image quality: consistent contrast, brightness over lamp.
* Full, deep, accurate cover over lifetime.
* Easily enlarges larger display areas.
* High power efficiency.
* DLP technology automatically reduces reflection.
New market opportunities
There are said to be several new opportunities for DLP. These are in:
Industrial: Machine vision, spectroscopy, interactive display, 3D printing, intelligent lighting, digital light exposure.
Infotainment: Mobile phones, tablets, camcorders, laptops, mobile projection, ultra slim TVs.
Gaming: Dual console gaming, interactive gaming, near eye display.
Digital signage: Interactive surface, storefront interactive, retail engagement.
Automotive: Head up display, interactive display, intelligent lighting.
Medical: Spectroscopy, 3D printing, intelligent lighting.
TI has DLP LightCrafter family of evaluation modules. It enables faster development cycles for end equipment requiring smalll form factor, lower cost and intelligent, high-speed pattern display. The DLP LightCrafter 4500 features the 0.45 WXGA chipset. The DLP chip can enable new and innovative intelligent display apps. If your solution uses, programs or senses light, DLP could be a fit.
DLP catalog offers programmable, ultra-high speed pattern. “DLP is light source agnostic. We use whatever’s most efficient for brightness,” he added.
The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:
Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.
Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.
Now, this is excellent news for everyone interested in the Indian semiconductor industry.
One look at the numbers above tell me – NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let’s examine!
As you can probably see, both the projects have placed 22nm right at the very last phase! That’s very interesting!
Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel’s Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!
For discussion’s sake, let’s say, a fab in India comes up by say, early 2015. Let’s assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn’t it? Where will the rest of the global industry be by then?
You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members. What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE’s Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY’s College of Nanoscale Science and Engineering!
So, what does all of this tell me?
One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space! Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!
Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop!
Perhaps, these product lines will be good for India and serve well, for now, but not for long!
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).
Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.
Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.
ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.
ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.
Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.
The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.
Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure
network for L2 VPN services at 50 percent lower cost than alternative solutions.