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India’s evolving importance to future of fabless: Dr. Wally Rhines

February 3, 2014 2 comments

Dr. Wally RhinesIf I correctly remember, sometime in Oct. 2008, S. Janakiraman, then chairman of the India Semiconductor Association, had proclaimed that despite not having fabs, the ‘fabless India” had been shining brightly! Later, in August 2011, I had written an article on whether India was keen on going the fabless way! Today, at the IESA Vision Summit in Bangalore, Dr, Wally Rhines repeated nearly the same lines!

While the number of new fabless startups has declined substantially in the West during the past decade, they are growing in India, said Dr. Walden C. Rhines, chairman and CEO, during his presentation “Next Steps for the Indian Semiconductor Industry” at the ongoing IESA Vision Summit 2014.

India has key capabilities to stimulate growth of semiconductor companies, which include design services companies, design engineering expertise and innovation, returning entrepreneurs, and educational system. Direct interaction with equipment/systems companies will complete the product development process.

Off the top 50 semicon companies in 2012, 13 are fabless and four are foundries. The global fabless IC market is likely to grow 29 percent in 2013. The fabless IC revenue also continues to grow, reaching about $78.1 billion in 2013.  The fabless revenue is highly concentrated with the top 10 companies likely to account for 64 percent revenue in 2013. As of 2012, the GSA estimates that there aere 1,011 fabless companies.

The semiconductor IP (SIP) market has also been growing and is likely to reach $4,774 million by 2020, growing at a CAGR of 10 percent. The top 10 SIP companies account for 87 percent of the global revenue. Tape-outs at advanced nodes have been growing. However, there are still large large opportunities in older technologies.

IoT will transform industry
It is expected that the Internet of Things (IoT) will transform the semiconductor industry. It is said that in the next 10 years, as many as 100 billion objects could be tied together to form a “central nervous system” for the planet and support highly intelligent web-based systems. As of 2013, 1 trillion devices are connected to the network.

Product differentiation alone makes switching analog/mixed-signal suppliers difficult. Change in strategy toward differentiation gradually raises GPM percentage.

India’s evolving importance to future of fabless
Now, India ranks among the top five semiconductor design locations worldwide. US leads with 507, China with 472, Taiwan with 256, Israel with 150, and India with 120. Some prominent Indian companies are Ineda, Saankhya Labs, Orca Systems and Signal Chip (all fabless) and DXCorr and SilabTech (all SIP).

India is already a leading source of SIP, accounting for 5.3 percent, globally, after USA 43 percent and China 17.3 percent, respectively. It now seems that India has been evolving from design services to fabless powerhouse. India has built a foundation for a fabless future. It now has worldwide leadership with the most influential design teams in the world.

Presently, there are 1,031 MNC R&D centers in India. Next, 18 of the top 20 US semiconductor companies have design centers in India. And, 20 European corporations set up engineering R&D centers in India last year. India also has the richest pool of creative engineering resources and educational institutions in the world. The experience level of Indian engineers has been increasing, but it is still a young and creative workforce. There is also a growing pool of angel investors in India, and also in the West, with strong connections to India.

So, what are the key ingredients to generate a thriving infrastructure? It is involvement and expertise with end equipment. Superb product definition requires the elimination of functional barriers. He gave some examples of foreign “flagged” Indian companies that produced early successes. When users and tool developers work in close proximity, “out-of-the-Box” architectural innovations revolutionize design verification.

On-chip networks: Future of SoC design


Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.

John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage – saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.

Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.

For the record, there are several SoC integration challenges that need to be addressed, such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.

SGN exceeds requirements
SGN met the tablet performance requirement with fabric frequency of 1066MHz. It has an efficient gate count of 508K gates. There are Sonicsfeatures such as an advanced system partitioning, security and I/O coherency. There is support for system concurrency as well as advanced power management.

Sonics offers system IP solutions such as SGN, a router based NoC solution, with flexible partitioning and VC (Virtual Channel) support. The frequency is optimized with credit based flow control.

SSX/SLX is message based crossbar/ShareLink solutions based on interleaved multi-channel technology. It has target based QoS with three arbitration levels. The SonicsExpress is for power centric clock domain crossing. There is sub-system re-use and decoupling. The MemMax manages and optimizes the DRAM efficiency while maintaining system QoS. There is run-time programmability for all traffic types. The SonicsConnect is a non-blocking peripheral interconnect.

Metal MEMS provides future of cell phone radio


Dennis Yost.

Dennis Yost.

Cavendish Kinetics is well known for its combined experience in MEMS, RF system design and CMOS design. Since 2008, it has focused on developing digital variable capacitors to improve wireless connectivity and data rates for mobile phones.

According to Dennis Yost, president & CEO, Cavendish Kinetics, 4G/LTE mobile devices are not yet achieving their potential. Antenna frequency tuning is an essential technology. Only metal MEMS technology has the size and performance. He was speaking at the ongoing Globalpress Electronics Summit 2013 in Santa Cruz, USA.

Cavendish claims to have the team, proven technology and real demonstrated performance. There is IP and patent protection for customers. Cavendish also owns the process.

The future of cell phone radio is needed in order to meet the performance gap. In future, you will see adaptive power amplifiers.

Antenna frequency tuning used in traditional RF applications. How do you ensure there is no loss in the component? Only MEMS has the performance and size for cell phones. Metal MEMS has almost no series resistance. No switches are required.

Previous designs required switches and different loads. Mechanical capacitors change capacitance value by moving plates – changing the area or plate distance changes the capacitance. MEMS capacitors do the same at the micrometer level.

Successful MEMS
Users can control design and manufacturing process of devices. How a MEMS is built is just as important as what you build. Success requires MEMS design expertise, MEMS process expertise and MEMS volume production expertise.

Cavendish has MEMS experts in all areas. It developed and owned MEMS manufacturing process. It uses all standard CMOS foundry technology. Innovations have so far yielded over 100 patents in manufacturing process and MEMS design.

By using the NanoMech technology performance, Cavendish Kinectics has demonstrated excellent performance in a small chip.

Next wave of design challenges, and future growth of EDA: Dr. Wally Rhines

December 15, 2012 1 comment

Dr. Wally Rhines.

Dr. Wally Rhines.

Today, EDA requires specialization. Elaborating on EDA over the past decade, Dr. Walden (Wally) C. Rhines, chairman and CEO, of Mentor Graphics, and vice chairman of the EDA Consortium, USA, said that PCB design has been flat despite growth in analysis, DFM and new emerging markets. Front end design has seen growth from RF/analog design and simulation, and analysis As design methodologies mature, EDA expenditures stop growing. He was speaking at Mentor Graphics’ U2U (User2User) conference in Bangalore, India.

Most of the EDA revenue growth comes from major new design methodologies, such as ESL, DFM, analog-mixed signal and RF. PCB design trend continues to be flat, and includes license and maintenance. The IC layout verification market is pointing to a 2.1 percent CAGR at the end of 2011. The RTL simulation market has been growing at 1.3 percent CAGR for the last decade. The IC physical implementation market has been growing at 3,4 percent CAGR for the last decade.

Growth areas in EDA from 2000-2011 include DFM at 28 percent CAGR, formal verification at 12 percent, ESL at 11 pecent, and IC/ASIC analysis at 9 percent, respectively.

What will generate the next wave of electronic product design challenges, and the future growth of EDA? This would involve solving new problems that are not part of the traditional EDA, and ‘do what others don’t do!

Methodology changes that may change EDA
There are five factors that can make this happen. These are:
* Low power design beyond RTL (and even ESL).
* Functional verification beyond simulation.
* Physical verification beyond design for manufacturability.
* Design for test beyond compression.
* System design beyond PCBs

Low power design at higher levels
Power affects every design stage. Sometimes, designing for low power at system level is required. System level optimization has the biggest impact on power/performance. And, embedded software is a major point of leverage.

Embedded software has an increasing share of the design effort. Here, Mentor’s Nucleus power management framework is key. It has an unique API for power management, enables software engineers to optimize power consumption, and reduces lines of application code. Also, power aware design optimizes code efficiency.

Functional verification beyond RTL simulation
The Verification methodology standards war is over. UVM is expected to grow by 286 percent in the next 12 months. Mentor Graphics Questa inFact is the industry’s most advanced testbench automation solution. It enables Testbench re-use and accelerates time-to-coverage. Intelligent test bench facilitates linear transition to multi-processing.

Questa accelerates the hardware/software verification environment. In-circuit emulation has been evolving to virtual hardware acceleration and embedded software development. Offline debug increases development productivity. A four-hour on-emulator software debug session drops to 30 minutes batch run. The offline debug allows 150 software designers to jumpstart debug process on source code. Virtual stimulus increases the flexibility of the emulator. As an example, Veloce is 700x more efficient than large simulation farms.

Physical verification beyond design for manufacturability
The Calibre PERC is a new approach to circuit verification. The Calibre 3DSTACK is the verification flow for 3D.
Read more…

Future material and devices for power electronics

December 15, 2011 1 comment

Alexandre Avron, market analyst in power electronics, Yole Développement, provided a briefing on semiconductor material’s potential through an analysis of devices and systems for power electronics.

According to him,  there is still a bright future for silicon. It will keep good market share until at least 2016 and even further, being cost competitive and very standard. On the other side, SiC is more applied to higher voltages. These are the smallest markets, but probably the one requiring SiC properties the most. PV inverters and EV/HEV are at intermediary voltage levels, they could both be targeted by SiC and GaN, this makes the predictions very difficult.

No technical aspects helps in knowing which material will be more used. They have their advantages and drawbacks, and both deserve their place. Prediction must be based on developments advancements.

The points to watch about SiC and GaN devices include: samples availability is a main point for future integration, reliability is also a main concern, especially for SiC devices, voltage capability seems to keep GaN at smaller power, and cost: GaN appears to be potentially cheaper, as it is based on Si wafers and can be CMOS compatible. Read more…

Game changers: New paradigms for future of electronic product realization


The Cadence Executive Forum, titled, ‘Game Changers: New Paradigms for the Future of Electronic Product Realization’, was held this evening in Bangalore, India. The speakers were Lip-Bu Tan, president and CEO, Cadence, and Bhaskar Pramanik, chairman of Microsoft India.

In the opening address, Tan remarked that there is likely to be challenging next 12 months in the USA and Europe. It may also impact the Asia Pacific region. However, from an EDA perspective, there will be new design, as companies would be involved in designing next-generation products and killer applications. There will also be more consolidation, which will continue. Another trend is that the number of start-ups has dropped.

There are two main drivers — technology and market. The cloud is starting to present a big opportunity. Other key areas include green technology and power management. Video will be driving a lot of traffic. The impact on the electronics industry will be new product development, with the IP having expanded beyond processor cores, an increase in collaborations and a changing EDA landscape — Cadence is investing on its decision to deliver the on the EDA360 vision.

Some of the recent highlights include Cadence’s new software development suite that addresses the hardware-software design gap, expansion of the Palladium XP, and releasing the industry’s first DDR4 solution, which includes controller, soft and hard PHY, drivers, verfication IP (VIP) memory models and signal integrity reference designs.

He spoke about horizontal collaborations such as app programing interface, and  vertical collaborations, which creates differentiation in the end markets. It also engages foundries in EDA, IP, etc. As an example, Tan spoke of Spreadtrum achieving one-pass silicon realization for the first 40nm product. Some other examples include Samsung designing and implementing 20nm product, ARM and Cadence collaborating on GHz implementation of Cortex-A15, and ARM, TSMC and Cadence collaborating on the industry’s first 20nm Cortex-A15.

Speaking on ‘Consumerization of IT’, Bhaskar Pramanik touched upon consumer trends driving IT. These trends include the economic system of computers, natural interaction, data explosion, social computing, pervasive displays, ubiquitous connectivity, and cloud computing.

According to him, computers will adapt to us. They will enable computing interfaces that are far more easier to use. The key business requirement is to balance the user expectations with the enterprise requirements.

Semiconductor supply chain dynamics: Future Horizons @ IEF2011


The last decade heralded a dramatic transformation in supply chain dynamics, driven by the complexity challenge of staying on the More Moore curve. On the demand side, the high cost of fabs persuaded almost all integrated device manufacturers (IDMs) to use foundries for their leading-edge wafer supply.

The ever-increasing process complexity and its negative impact on manufacturing yields forced the adoption of sophisticated foundry-specific design-for manufacturing (DFM) techniques, effectively committing new chip designs to a single foundry and process.

At the same time, the industry adopted a much more cautious lagging rather than leading demand approach to new capacity expansion, resulting in under-supply and shortages in leading-edge wafer fab capacity. To make matters worse, the traditional oxide-based planar transistor started to misbehave at the 130nm node, as manifested by low yields and higher than anticipated power dissipation, especially when the transistors were supposed to be off, with no increase in performance, heralding the introduction of new process techniques (e.g., high-k metal gates).

Even before these structural changes have been fully digested, supply chain dynamics have been further disrupted by the prospective transition to 450mm wafer processing, to extreme ultra violet (EUV) lithography, and from planar to vertical transistor design.

Transistor design
Since the start of the industry, adding more IC functionality while simultaneously decreasing power consumption and increasing switching speed—a technique fundamentally known as Moore’s Law—has been achieved by simply making the transistor structure smaller. This worked virtually faultlessly down to the 130nm node when quite unexpectedly things did not work as planned. Power went up, speed did not improve and process yields collapsed. Simple scaling no longer worked, and new IC design techniques were needed.

While every attempt was made to prolong the life of the classic planar transistor structure, out went the polysilicon/silicon dioxide gate; although this transition was far from plain sailing, in came high-k metal gates spanning 65nm-28nm nodes. Just as the high-k metal gate structure gained industry-wide consensus at 28nm, it too ran out of steam at the 22nm-16nm nodes, forcing the introduction of more complex vertical versus planar transistor design and making the IC design even more process-dependent (i.e., foundry-dependent). Dual foundry sourcing, already impractical for the majority of semiconductor firms, will only get worse as line widths continue to shrink. Read more…

Need to work toward sustainable future: imec

September 5, 2011 2 comments

Luc Van den hove, president and CEO, imec.

Luc Van den hove, president and CEO, imec.

At an ISA CXO Conclave, Luc Van den hove, president and CEO, imec, said that we need to work toward a sustainable future. Started in 1984, Leuven, Belgium-based imec performs world leading research in nanoelectronics. He touched upon some research programs currently undertaken by imec.

Green radio is for low-power wireless communications. Technologies would be 1000K energy efficient. He added: “We are also developing low cost, low-power reconfigurable radios. Further, we feel that videos will dominate mobile phones.”

Another innovation, E-Nose, can be used for air quality, safety, food and well being. Human++ BAN life sciences, is yet another innovation. Now, the cost of healthcare is said to be exploding. By 2030, over 1 billion people will be over 65+ years. imec is developing body area network. According to imec, wearable wireless sensors can grow to over $400 million by 2014.

imec is working on technologies ranging from bio sensors to lab-on-chip. “We are also working on implantable devices such as microprobes,” said Van den hove. imec is also working on the NVision technology. According to estimates, there will likely be 78.1 million 3D TVs by 2012. Van den hove said, “we are developing holographic visualization.”

On energy, he said that renewable energy was growing in importance. “We are working on solar, storage, switching, etc. As an example, we have replaced Ag (silver) with Cu (copper) metallization.” Organic solar cells is yet another technology imec’s working on.”

In power electronics, imec is working on GaN power devices. “We also have a program for boosting chip performance and system functionality,” he added. “We are also exploring the third dimension — DRAM on logic.”

CMORE, is said to be more than CMOS, as well as MEMS, sensors, photonics, SiGe based metals/devices. In organic electronics, imec and Holst have developed the first plastic microprocessor, which was introduced in 2011. imec has research programs for full ecosystems as well.

Van den hove noted: “We also celebrate the launch of imec India. We want to develop sustainable nanoelectronic solutions. For example, rural India drives the mobile phone growth. India is also driving e-health.” In Arise Labs, imec has provided the nanoelectronic platform, technology and design expertise, application programming and strong industry network.

Maxim well positioned for future success!


A view of Maxim's Analyst Day 2011.

A view of Maxim's Analyst Day 2011.

According to Tunç Doluca, CEO, Maxim Integrated Products, the analog market is changing. Maxim is the analog integration pioneer. Integration accelerating in growth markets. The company has been executing its strategy via innovation, integration and balance. It is well positioned for success in the future. Doluca was speaking at the Analyst Day 2011 event held recently.

Speaking about the evolution of analog, Doluca touched upon analog integration, system solution and building blocks. Six areas act as market growth drivers — automotive electronics, HD video infrastructure, energy, mobility, security and healtcare.

Key market trends in automotive electronics include electronic content increasing, infotainment now becoming standard, and hybrid and electric vehicles. Maxim’s product investments include lighting and body electronics, infotainment solutions, automotive connectivity and battery management. The analog TAM is said to be $10 billion as per IC Insights. Automotive electronics is likely to grow at 9.2 percent CAGR through 2014, according to DQ 2010.

Key trends in HD infrastructure include infrastructure for HD video, smart TVs – Skype TV, and wireless HD in the home. Maxim’s product investments include the optical transceivers, video SoCs including so]ware and wireless HD 1080p chipset. The Internet traffic is likely to grow 13x times from 2006 to 2014.

Key trends in energy include energy measurement everywhere, which requires communication. Maxim’s product investments include energy metering and measuring, smart grid communications and low-power product focus. As per Frost & Sullivan, 2011 should see 116 million meter installations.

Key trends in mobile devices include richer features and smaller devices, emergence of tablets and touchscreen displays. Maxim’s product investments include Power SoC — analog integration, sensing — proximity and imaging, ModelGauge technology, TacTouch controllers and Flexsound audio. Year 2011 should see 1.6 billion cell phones, including 428 million smartphones, as per Oppenheimer, and also 220 million laptops and 55 million tablets, as per MS Research.

Key trends in security include rise of electronic transactions, stringent security requirements and digital surveillance. Maxim’s product investments include key acquisitions for secure SoCs, H.264 SoCs — IP cameras and DVRs, and end-to-end silicon solutions. Financial terminals should grow 6.3 percent CAGR over the next five years, as per BCC Research.

Key trends in healthcare include diagnostics closer to patients, home-based care and enabling healthier lifestyles. Maxim’s product investments have been in areas such as integration for miniaturization, low-power for portability and high-performance analog. Medical electronics is said to grow at 10 percent CAGR over the next five years, as per Databeans.

Maxim has been executing its strategy based on three key areas — innovation, integration and balance. Maxim is doing innovation in areas: 0.18 micron process on 300mm wafers, 10 touch capacitive touchscreen controllers, mobile power SoCs that integrate analog functions, and energy metering SoCs that are said to replace seven discrete ICs and reduce costs up to 40 percent. The integration trend has been progressing across all markets.

In five years, Maxim should be a leader in integrated analog solutions, have the industry’s fastest growing rate, have high profitability and be one of best companies to work for. A new world headquarters is under construction in San Jose. Relocation is scheduled for 2012.

 

Boom turned to bust? Chip industry’s future!


Malcolm Penn, Future Horizons.

Malcolm Penn, Future Horizons.

Malcolm Penn, chairman and CEO, Future Horizons, asked the question at the SEMI ISS2011 Europe event at Grenoble, France, early this week: Whether this is the time to rethink the industry assumptions?

For instance, fabs have no strategic value, until you haven’t got one and lost control of your business. ASPs will keep on falling, just like house prices kept on rising? The semicon industry growth rate has slowed to ’7 percent per annum, which is only possible if ASPs keep falling 4 percent given an 11 percent unit growth.

Foundry wafers will always be cheap and freely available, just like cheap debt, right? Multiple sources will keep the foundries ‘honest’, since it is assumed that multi-sourcing at 20/22nm is going to be ‘interesting‘. It is also OK to focus on more than Moore competence, as today’s ‘More Moore’ is tomorrow’s ‘More Than Moore’.

Industry fundamental #1 – Economy: This was NOT a recession, someone turned off the lightsPre-Lehman, the chip industry was in very good shape. There was strong unit demand, and no excess inventory.There was limited wafer fab capacity, and no overspend/cutting back. Next, the ASPs were recovering, although, structurally driven. However, the strong global world economy was being deliberately slowed. The money really stopped moving in the post-Lehmann crash!

The economic coupling Is statistically weak. The economy is just one part of the equation. The chip industry marches to its own drum as well.

Industry fundamental #2: Unit demand: The Moore’s Law giveth and taketh away! Long-term average ICs/wafers grow only very slowly. There are more complex ICs counter balance die shrinks (1-2 percent productivity gain). Besides, 9-10 percent new capacity is needed to match the 11 percent average IC unit growth.

Industrial fundamental #3: Fab capacity: Let’s look at the IC manufacturing fundamentals — four quarter minimum lag from decision to impact.
* Total equipment capex = 85 percent of the total capex
* Wafer fab capex = 70 percent total equipment capex
* Order today = Wafer fab capex one quarter later* Wafer fab capex = Additional capacity two quarters later
* Additional capacity = IC units out one quarter later.

Pig cycles and cobwebs will keep happening due to long supply-side lead times (4 Months – production / 2 Years – fabs / 5+ years – design).

The fab capacity is still seriously tight. The Q4-10 status is still down 7.5 percent vs. Q3-08 peak. Also, the first relief happened in Q4-10 (from Q3/Q4-09’s spend) following six flat quarters.

The IC wafer fab capacity for Q3/Q4-09 spend, was equal to +80k ws/w In Q4-10. The 2010 spend was equal to ~400k ws/w additional by Q4-11? The wafer fab capex is still running ‘fab tight!’ Here are some more pointers:
* Not yet overheating, despite 140 percent 2010 growth.
* 2010 spend same as 2006; 10 percent lower than 2007 and 80 percent of 2000’s all time peak.
* Q1-11 book to bill <1; slowing Q2-11 sales.
* 2011 up between 5-15 percent, still within ‘safe haven’ region.
* TSMC thunders on with capex up 30 percent sales up 22 percent; the leadership gap up. Read more…

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