“Bangalore should become the hardware capital of India,” according to Ananth Kumar, MP and former Union minister of Urban Development. Bangalore should not only be known as the software capital and silicon valley of India. “That should be the main aim of Electronica India 2010 expo.”
“India also needs hardware parks, besides software parks,” he added. India needs hardware parks that should be more like multiplexes. He mentioned that taxation regime in Karnataka was also blocking development of electronics hardware. Hardware should also enjoy the taxation benefits that hardware enjoys, he stressed. “We should be the major exporters of hardware.”
There are several highlights from day one of Electronica India 2010. I hope you get a chance to pick up the show daily being produced by yours truly on behalf of the Global SMT & Packaging magazine, thanks to my good friend and ex-colleague Debashish Chowdhury.
Some of the highlights are:
I also met a supplier who has an e-bike. Need to catch up with him sometime soon!
It was also great to catch up with Bhupinder Singh and Sunali Agarwaal of MMI India, Anil Kumar of IPCA, as well as Ranga Prasad of Aqtronics, and several other folks, who, up until now, were merely friends over email or telephone.
More later, time permitting!
I had mixed feelings on reading a press release on the recommendations from the Task Force set up by the Ministry of Communications & IT, Government of India in August 2009 to suggest measures to stimulate the growth of IT, ITeS and electronics hardware manufacturing in the country. However, I was quite surprised to see a news suggesting an amendment of the Indian semiconductor policy!
First, the Task Force’s recommendations. I’ll only focus on the electronics manufacturing bit! For electronics system design and manufacturing — it suggests the following:
* Establishing a ‘National Electronics Mission’ -– a nodal agency for the electronics Industry within DIT and with direct interface to the Prime Minister’s Office (PMO). The nodal agency would help in the synchronized functioning of the Industry through effective coordination across Ministries and Government Departments in the Centre and the States and would enhance the ease of doing business.
* Nurturing established electronics manufacturing clusters and develop them into centres of excellence, while encouraging new ones.
Isn’t this old wine in new bottles? Also, have we really done enough in the past to even boost electronics hardware manufacturing in the country? If yes, then where are the mini Hsinchus and Shenzhens within India? Even N. Vittal had said something similar (such as developing mini Hong Kongs and Singapores) some years ago!
India already has an Electronics Hardware Technology Park (EHTP) scheme. The business of establishing key electronics manufacturing clusters and developing them into centres of excellence — while encouraging new ones — should have been taken care of much, much earlier! By much. much earlier — at least 10-15 years ago!
By the time the Task Force’s recommendations are acted upon, a year or two more would have easily passed! That stretches the manufacturing gap even further!
Let me ask one question: how well is India known globally for its local telecom manufacturing companies, or, even hardware manufacturing companies? Why am I asking this question? Well, when the National Telecom Policy was announced back in 1994. Many would recall there were a lot of astronomical bids — especially the ones from Himachal Futuristic. What many overlook is the fact that the period actually presented a brilliant opportunity before India to become a leader in telecom and electronics hardware manufacturing! However, that hasn’t and never quite happened!
The Indian electronic components story is more or less the same! India’s electronic components and accessories ecosystem industry is currently moderate. It used to be 15 percent and has now grown to 35 percent. This should be grown even further! Are we backing the electronic components segment enough?
What sort of guidance or hand holding will be provided to those firms who look to develop India-based product companies? For that matter, how many great software products have been conceptualized, designed and developed in India that are worth mentioning?
Further, an interesting fact brought up time and again within the Indian industry is the requirement of a robust entrepreneurial spirit, and the need for much more sources of funding for semiconductor product companies. Who all are helping the Indian semicon startups?
And then, there’s this news that suggests amending the existing Indian semiconductor policy! It is sheer bad luck that silicon IC fabs haven’t happened in India, as yet! Although HSMC and SemIndia started off with good intentions, things got sidetracked due to various reasons. Now, solar PV has attracted several players. It was also part of the semicon policy, isn’t it? So, where is the question of amending the policy?
Yes, there is definitely a need to develop strong entrepreneurial spirit within the country and encourage local product development, rather than remain contented with a services-oriented mindset and industry.
Last July, during the ISA Excite, there was an announcement that Karnataka would have its semicon policy soon. It hasn’t happened yet, but I hope it will!
Nevertheless, here’s what I wrote last year on what India brings to the semicon world (and Japan), as I attempted to answer this question from a friend:
What are India’s strengths?
The clear strengths of the Indian semiconductor industry are embedded and design services! We are NOT YET into product development, but one sincerely hopes that it gathers pace.
The market drivers in India are mobile phone services, IT services/BPO, automobiles and IT hardware. India is also very strong in design tools, system architecture and VLSI design, has quite strong IP protection laws, and is reasonably strong in concept/innovation in semiconductors.
Testing and packaging are in a nascent stage. India will certainly have more of ATMP facilities. Nearly every single semicon giant has an India presence! That should indicate the amount of interest the outside world has on India. In fact, I am told, some key decisions are now made out of the Bangalore based outfits!
I had also suggested a 10-point program for the Karnataka semicon policy — in another blog post — on June 29, 2008. The points were:
1. A long-term semiconductor policy running 20-25 years or so.
2. Core team of top Indian leaders from Indian firms and MNCs, as well as technology institutes in Karnataka to oversee policy implementation.
3. Incentives such as government support, including stake in investments, and tax holidays.
4. Strong infrastructure availability and management.
5. Focus on having solar/PV fabs in the state.
6. Consider having 150/180/200mm fabs that tackle local problems via indigenous applications.
7. Develop companies in the assembly testing, verification and packaging (ATMP) space.
8. Attract companies in fields such as RFID, to address local problems and develop local applications.
9. Pursue companies in PDP, OLED/LED space to set up manufacturing units.
10. Promote and set up more fabless units.
There should be some steps to create specific zones for setting up such units — for fabs, fabless, ATMP, manufacturing, etc., all spread equally across the state.
Well, can’t all of this be extended across the country, rather than Karnataka alone? It sure can! What wasn’t done earlier, should be done now. Better late than never!
There’s also a lack of funding for certain semicon and hardware manufacturing areas/projects. This is another aspect that needs to be looked into.
As I’ve mentioned time and again to some friends within the Indian semiconductor industry and solar /PV industry — the semicon policy (earlier), and the National Solar Mission (now), are meant to help you guys! It is up to you — the industry folks — to make things happen! If you don’t, who will?
I am sure that the Task Force’s recommendations are very well thought out and quite robust. I don’t have the luxury of reading a copy, barring the release, and so there’s nothing for me to add. Best wishes to the Indian electronics hardware manufacturing industry and may it succeed greatly in future.
Following the success of India’s semiconductor policy, the government of India is well on its way to announce a new hardware manufacturing policy, hopefully sometime this month.
According to M. Madhavan Nambiar, Additional Secretary, Ministry of Communications & Information Technology, Department of Information Technology, the hardware policy should be coming shortly, where, the government is looking to address infrastructure related issues.
Speaking with him on the sidelines of the Thought Leader Series organized by the India Semiconductor Association (ISA), he said the hardware policy would still take some time. “As a part of it, we are looking at IT investment regions.” These would be set up in 40km areas, and each region would be an entire ecosystem in itself.
Nambiar added: “We are also looking at very good public-private partnerships. We have to develop the manpower.” The Department is working with the Labour Ministry and other organizations in order to set up skill development units. It is necessary for skiils to keep pace with technology.
The to-be-announced hardware policy will also be looking at taxes, etc. “It is a recommendation that we are making,” he said. “For India to be able to attract investments, we nust ensure that we are the best in class.”
Touching upon the semiconductor policy, he said it was important that this policy was pro-active and friendly. “We need to see how best to provide comfort levels to those investing,” Nambiar said.
It was necessary to have a strong semiconductor industry in India, as all leading countries, such as the USA, China, Taiwan and Japan had equally strong semiconductor industries. There has since been lot of interest in fabs and ecosystem units, and some of those were in the process of being set up.
Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;) I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.
Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.
In that case, why are some companies STILL not knowing how to verify a chip?
He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.
“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”
How are companies trying to address the challenges?
Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.
* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.
* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.
* Verification environment re-use helps to cut down the time required to develop verification environments.
* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.
Cadence has the widest portfolio of tools to help companies meet verification challenges, including:
Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;
The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;
Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and
Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.
Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.
When should good verification start?
Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”
Are folks mistaking by looking at tools and not at the verification process itself?
He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.
Finally, there’s verification planning! What should be the ‘right’ verification path?
Verification planning needs to include:
* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.
It seems to be the season of verification. The Universal Verification Methodology (UVM 1.2) is being discussed across conferences. Dennis Brophy, director of Strategic Business Development, Mentor Graphics, says that UVM 1.2 release is imminent, and UVM remains a topic of great interest.
Biggest verification mistakes
Before I add Dennis Brophy’s take on UVM 1.2, I discussed with Dr. Wally Rhines, chairman and CEO, Mentor Graphics Corp. the intricacies regarding verification. First, I asked him regarding the biggest verification mistakes today.
Dr. Rhines said: “The biggest verification mistake made today is poor or incomplete verification planning. This generally results in underestimating the scope of the required verification effort. Furthermore, without proper verification planning, some teams fail to identify which verification technologies and tools are appropriate for their specific design problem.”
Would you agree that many companies STILL do not know how to verify a chip?
Dr. Rhines added: “I would agree that many companies could improve their verification process. But let’s first look at the data. Today, we are seeing that about 1/3 of the industry is able to achieve first silicon success. But what is interesting is that silicon success within our industry has remained constant over the past ten years (that is, the percentage hasn’t become any worse).
“It appears that, while design complexity has increased substantially during this period, the industry is at least keeping up with this added complexity through the adoption of advanced functional verification techniques.
“Many excellent companies view verification strategically (and as an advantage over their competition). These companies have invested in maturing both their verification processes and teams and are quite productive and effective. On the other hand, some companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.”
How are companies trying to address those?
According to him, the recent Wilson Research Group Functional Verification Study revealed that the industry is maturing its verification processes through the adoption of various advanced functional verification techniques (such as assertion-based verification, constrained-random simulation, coverage-driven techniques, and formal verification). Complexity is generally forcing these companies to take a hard look at their existing processes and improve them.
Getting business advantage
Are companies realizing this and building an infrastructure that gets you business advantage?
He added that in general, there are many excellent companies out there that view verification strategically and as an advantage over their competition, and they have invested in maturing both their verification processes and teams. On the other hand, some other companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.
When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment?
Dr. Rhines noted: “Just like the design team is often involved in discussion during the architecture and micro-architecture planning phase, the verification team should be an integral part of this process. The verification team can help identify architectural aspects of the design that are going to be difficult to verify, which ultimately can impact architectural decisions.”
Are folks mistaken by looking at tools and not at the verification process itself? What can be done to reverse this?
He said: “Tools are important! However, to get the most out of the tools and ensure that the verification solution is an efficient and repeatable process is important. At Mentor Graphics, we recognize the importance of both. That is why we created the Verification Academy, which focuses on developing skills and maturing an organization’s functional verification processes.”
What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities?
Dr. Rhines said: “During verification planning, too many organizations focus first on the “how” aspect of verification versus the “what.” How a team plans to verify its designs is certainly important, but first you must identify exactly what needs to be verified. Otherwise, something is likely to slip through.
“In addition, once you have clearly identified what needs to be verified, it’s an easy task to map the functional verification solutions that will be required to productively accomplish your verification goals. This also identifies what skill sets will need to be developed or acquired to effectively take advantage of the verification solutions that you have identified as necessary for your specific problem.”
How is Mentor addressing this situation?
Mentor Graphics’ Verification Academy was created to help organizations mature their functional verification processes—and verification planning is one of the many excellent courses we offer.
In addition, Mentor Graphics’ Consulting provides customized solutions to technical challenges on real projects with real schedules. By helping customers successfully integrate advanced functional verification technologies and methodologies into their work flows, we help ensure they meet their design and business objectives.
Five recommendations for verification
Finally, I asked him, what would be your top five recommendations for verification?
Here are the five recommendations for verification from Dr. Rhines:
* Ensure your organization has implemented an effective verification planning process.
* Understand which verification solutions and technologies are appropriate (and not appropriate) for various classes of designs.
* Develop or acquire the appropriate skills within your organization to take advantage of the verification solutions that are required for your class of design.
* For the SoC class of designs, don’t underestimate the effort required to verify the hardware/software interactions, and ensure you have the appropriate resources to do so.
* For any verification processes you have adopted, make sure you have appropriate metrics in place to help you identify the effectiveness of your process—and identify opportunities for process improvements in terms of efficiency and productivity.
In 2013, the global semiconductor industry had touched $306 billion or so. Sales had doubled from $100 billion to $200 billion in six years — from 1994 to 2000. It was enterprise sales that was driving this. It has taken 14 years to move past $300 billion, said Anil Gupta, managing director, Applied Micro Circuits India Pvt Ltd, at the UVM 1.2 day.
This time, consumption of semiconductors is not only around enterprise, but social networks as well. Out of the $306 billion, logic was approximately $86 billion, memory was $67 billion, and micro was $58 billion. We, as consumers, are starting to play a huge role.
However, the number of large players seem to be shrinking. Mid-size firms, like Applied Micro, are said to be struggling. Technology is playing an interesting role. There is a very significant investment in FinFETs. It may only get difficult for all of us. Irrespective, all of this is a huge barrier to the mid- to small-companies. Acquisitions are probably the only route, unless you are in software.
In India, we have been worried for a while, whether the situation will be a passing phase. We definitely will have a role to play. From an expertise perspective, thanks to our background, we have been a poor nation. For us, the job is the primary goal. We need to think: how do we deliver value? We have to try and keep creating value for as long as possible.
As more and more devices actually happen, many other things are also happening. An example for devices is power. We still have a fair number of years ahead where there will be opportunities to deliver value.
What’s happening between hardware and software? The latter is in demand. Clearly, there is a trend to make the hardware a commodity. However, hardware s not going away! Therefore, the opportunity for us to deliver value is huge.
Taking the tools to make something, is critical. UVM tools are critical. But, somewhere along the way, we seem to stop at that. We definitely need to add value. UVM’s aim is to make things re-usable.
Don’t loose your focus while doing verification. Think about the block, the subsystem and the top. You need to and will discover and realize how valuable it is to find a bug, before the tape out of the chip.
NXP Semiconductors N.V. recently released the LPC1500 microcontroller series, optimized for fast, easy, and high-precision motor control.
So, what’s unique about the new LPC family? First, the LPC1500 was designed to simplify motor control for the masses. It has the flexibility to drive various types of motors, such as ACIM, PMSM, BLDC, etc. The LPC1500 can also drive multiple motors simultaneously.
These aren’t all! The hardware interconnection between the SCTimer/PWM, ADCs and comparators allow the motor to be driven with little CPU intervention. It has free LPCXpresso IDE and free FOC firmware for sensored and sensorless motors that reduces cost and improves time to market.
Looking at the unique features and benefits, the Switch Matrix allows any function to be routed out to any pin making schematic capture and board layout simpler and faster. The SCTimer/PWM block is unique to NXP.
Benefits are, it can run independently of the CPU and generate extremely precise PWM waveforms for quiet, smooth, efficient motor drive. The 2x 2Msps 12b,12ch ADCs can measure simultaneous phase currents to determine precise motor position and speed. There are four comparators for fast system shutdown upon fault detection.
The LPC1500 is suitable for large appliances, HVAC, building automation, factory automation, industrial pumps and generators, digital power, remote sensing, etc.
How will the LPC1500 aid embedded engineers? According to NXP, it saves time to market using the free FOC firmware and GUI tuning tool. It also saves system cost by using only one system MCU, e.g., HVAC typically has one MCU for fan control and one MCU for the compressor. LPC1500 can control both.
The LPC1500 feature set makes it ideal for sensorless motor control removing the need for sensored motors and allowing customers to switch to cheaper sensorless motors. As the SCTimer/PWM can run independently of the CPU, the freed up CPU bandwidth can be used to control other parts of the system for example the LPC1500 can be used for both the control and motor board in a washing machine.
NXP is currently working with customers to understand their future requirements and developing the roadmap to match their needs.