“Bangalore should become the hardware capital of India,” according to Ananth Kumar, MP and former Union minister of Urban Development. Bangalore should not only be known as the software capital and silicon valley of India. “That should be the main aim of Electronica India 2010 expo.”
“India also needs hardware parks, besides software parks,” he added. India needs hardware parks that should be more like multiplexes. He mentioned that taxation regime in Karnataka was also blocking development of electronics hardware. Hardware should also enjoy the taxation benefits that hardware enjoys, he stressed. “We should be the major exporters of hardware.”
There are several highlights from day one of Electronica India 2010. I hope you get a chance to pick up the show daily being produced by yours truly on behalf of the Global SMT & Packaging magazine, thanks to my good friend and ex-colleague Debashish Chowdhury.
Some of the highlights are:
I also met a supplier who has an e-bike. Need to catch up with him sometime soon!
It was also great to catch up with Bhupinder Singh and Sunali Agarwaal of MMI India, Anil Kumar of IPCA, as well as Ranga Prasad of Aqtronics, and several other folks, who, up until now, were merely friends over email or telephone.
More later, time permitting!
I had mixed feelings on reading a press release on the recommendations from the Task Force set up by the Ministry of Communications & IT, Government of India in August 2009 to suggest measures to stimulate the growth of IT, ITeS and electronics hardware manufacturing in the country. However, I was quite surprised to see a news suggesting an amendment of the Indian semiconductor policy!
First, the Task Force’s recommendations. I’ll only focus on the electronics manufacturing bit! For electronics system design and manufacturing — it suggests the following:
* Establishing a ‘National Electronics Mission’ -– a nodal agency for the electronics Industry within DIT and with direct interface to the Prime Minister’s Office (PMO). The nodal agency would help in the synchronized functioning of the Industry through effective coordination across Ministries and Government Departments in the Centre and the States and would enhance the ease of doing business.
* Nurturing established electronics manufacturing clusters and develop them into centres of excellence, while encouraging new ones.
Isn’t this old wine in new bottles? Also, have we really done enough in the past to even boost electronics hardware manufacturing in the country? If yes, then where are the mini Hsinchus and Shenzhens within India? Even N. Vittal had said something similar (such as developing mini Hong Kongs and Singapores) some years ago!
India already has an Electronics Hardware Technology Park (EHTP) scheme. The business of establishing key electronics manufacturing clusters and developing them into centres of excellence — while encouraging new ones — should have been taken care of much, much earlier! By much. much earlier — at least 10-15 years ago!
By the time the Task Force’s recommendations are acted upon, a year or two more would have easily passed! That stretches the manufacturing gap even further!
Let me ask one question: how well is India known globally for its local telecom manufacturing companies, or, even hardware manufacturing companies? Why am I asking this question? Well, when the National Telecom Policy was announced back in 1994. Many would recall there were a lot of astronomical bids — especially the ones from Himachal Futuristic. What many overlook is the fact that the period actually presented a brilliant opportunity before India to become a leader in telecom and electronics hardware manufacturing! However, that hasn’t and never quite happened!
The Indian electronic components story is more or less the same! India’s electronic components and accessories ecosystem industry is currently moderate. It used to be 15 percent and has now grown to 35 percent. This should be grown even further! Are we backing the electronic components segment enough?
What sort of guidance or hand holding will be provided to those firms who look to develop India-based product companies? For that matter, how many great software products have been conceptualized, designed and developed in India that are worth mentioning?
Further, an interesting fact brought up time and again within the Indian industry is the requirement of a robust entrepreneurial spirit, and the need for much more sources of funding for semiconductor product companies. Who all are helping the Indian semicon startups?
And then, there’s this news that suggests amending the existing Indian semiconductor policy! It is sheer bad luck that silicon IC fabs haven’t happened in India, as yet! Although HSMC and SemIndia started off with good intentions, things got sidetracked due to various reasons. Now, solar PV has attracted several players. It was also part of the semicon policy, isn’t it? So, where is the question of amending the policy?
Yes, there is definitely a need to develop strong entrepreneurial spirit within the country and encourage local product development, rather than remain contented with a services-oriented mindset and industry.
Last July, during the ISA Excite, there was an announcement that Karnataka would have its semicon policy soon. It hasn’t happened yet, but I hope it will!
Nevertheless, here’s what I wrote last year on what India brings to the semicon world (and Japan), as I attempted to answer this question from a friend:
What are India’s strengths?
The clear strengths of the Indian semiconductor industry are embedded and design services! We are NOT YET into product development, but one sincerely hopes that it gathers pace.
The market drivers in India are mobile phone services, IT services/BPO, automobiles and IT hardware. India is also very strong in design tools, system architecture and VLSI design, has quite strong IP protection laws, and is reasonably strong in concept/innovation in semiconductors.
Testing and packaging are in a nascent stage. India will certainly have more of ATMP facilities. Nearly every single semicon giant has an India presence! That should indicate the amount of interest the outside world has on India. In fact, I am told, some key decisions are now made out of the Bangalore based outfits!
I had also suggested a 10-point program for the Karnataka semicon policy — in another blog post — on June 29, 2008. The points were:
1. A long-term semiconductor policy running 20-25 years or so.
2. Core team of top Indian leaders from Indian firms and MNCs, as well as technology institutes in Karnataka to oversee policy implementation.
3. Incentives such as government support, including stake in investments, and tax holidays.
4. Strong infrastructure availability and management.
5. Focus on having solar/PV fabs in the state.
6. Consider having 150/180/200mm fabs that tackle local problems via indigenous applications.
7. Develop companies in the assembly testing, verification and packaging (ATMP) space.
8. Attract companies in fields such as RFID, to address local problems and develop local applications.
9. Pursue companies in PDP, OLED/LED space to set up manufacturing units.
10. Promote and set up more fabless units.
There should be some steps to create specific zones for setting up such units — for fabs, fabless, ATMP, manufacturing, etc., all spread equally across the state.
Well, can’t all of this be extended across the country, rather than Karnataka alone? It sure can! What wasn’t done earlier, should be done now. Better late than never!
There’s also a lack of funding for certain semicon and hardware manufacturing areas/projects. This is another aspect that needs to be looked into.
As I’ve mentioned time and again to some friends within the Indian semiconductor industry and solar /PV industry — the semicon policy (earlier), and the National Solar Mission (now), are meant to help you guys! It is up to you — the industry folks — to make things happen! If you don’t, who will?
I am sure that the Task Force’s recommendations are very well thought out and quite robust. I don’t have the luxury of reading a copy, barring the release, and so there’s nothing for me to add. Best wishes to the Indian electronics hardware manufacturing industry and may it succeed greatly in future.
Following the success of India’s semiconductor policy, the government of India is well on its way to announce a new hardware manufacturing policy, hopefully sometime this month.
According to M. Madhavan Nambiar, Additional Secretary, Ministry of Communications & Information Technology, Department of Information Technology, the hardware policy should be coming shortly, where, the government is looking to address infrastructure related issues.
Speaking with him on the sidelines of the Thought Leader Series organized by the India Semiconductor Association (ISA), he said the hardware policy would still take some time. “As a part of it, we are looking at IT investment regions.” These would be set up in 40km areas, and each region would be an entire ecosystem in itself.
Nambiar added: “We are also looking at very good public-private partnerships. We have to develop the manpower.” The Department is working with the Labour Ministry and other organizations in order to set up skill development units. It is necessary for skiils to keep pace with technology.
The to-be-announced hardware policy will also be looking at taxes, etc. “It is a recommendation that we are making,” he said. “For India to be able to attract investments, we nust ensure that we are the best in class.”
Touching upon the semiconductor policy, he said it was important that this policy was pro-active and friendly. “We need to see how best to provide comfort levels to those investing,” Nambiar said.
It was necessary to have a strong semiconductor industry in India, as all leading countries, such as the USA, China, Taiwan and Japan had equally strong semiconductor industries. There has since been lot of interest in fabs and ecosystem units, and some of those were in the process of being set up.
San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.
I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”
There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.
Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.
How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.
“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”
How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.
On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.
Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth. Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry. At a macro level, the consumer sector will drive a lot of the growth ahead. For EDA, the higher levels of abstraction is where the growth will be.”
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).
Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.
Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.
ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.
ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.
Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.
The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.
Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure
network for L2 VPN services at 50 percent lower cost than alternative solutions.
Algorithm-to-chips is Algotochip’s mission. It turns algorithms into chips by converting your behavioral algorithm C-code into architecture C-code into RTL into GDS-II.
Speaking about architecture evolution at the 13th Global Electronics Summit at Santa Cruz, USA, Satish Padmanabhan, CTO and founder, Algotochip, said that the interconnect between CPU and all the HA blocks needs to be determined.
The market approach includes building an ecosystem with leading IP providers in targeted markets. Some areas Algotochip is looking at are LTE and smart grid markets.
Nitto Denko is committed to support Algotochip moving forward. Year 2013 will see significant investment increases in terms of engineering resources, as well as sales and marketing organization to cover USA, China and Japan.
Algotochip is showing that its technology is sound in improving system hardware and software partitioning and first time right design. The LTE turbo decoder performances in terms of throughput, power and gates count is showing the benefits of Algotochip BlueBox. The company is now building an ecosystem around its technology.
ARM Holdings and Tensilica are the first of the few partners that Algotochip wants to collaborate with to improve the overall time-to-market of digital design of the SoC, ASIC and FPGA, etc.