Here are some links you can use.
Consumer Electronics Association — http://www.ce.org
FPGA Central — http://www.fpgacentral.com
Global Sources — http://www.globalsources.com
GlobalSpec — http://www.globalspec.com
Hong Kong Trade Development Council — http://www.hktdc.com
India Semiconductor Association — http://www.isaonline.org
International Telecommunication Union — http://www.itu.int
iSuppli — http://www.isuppli.com
Photonics — http://www.photonics.com
SEMI — http://www.semi.org
Taiwan External Trade Development Council (TAITRA) — http://www.taitra.com.tw
Following a host of forecasts for 2014, it is now the turn of Applied Materials with its forecast for the year. First, I asked Om Nalamasu, senior VP, CTO, Applied Materials regarding the outlook for the global semicon industry in 2014.
Semicon outlook 2014
He said that Gartner expects the semiconductor industry to grow in mid-single digits to over $330 billion in 2014.
“In our industry – the semiconductor wafer fab equipment sector – we are at the beginning of major technology transitions, driven by FinFET and 3D NAND, and based a wide range of analyst projections, wafer fab equipment investment is expected to be up 10-20 percent in 2014. We expect to see a year-over-year increase in foundry, NAND, and DRAM investment, with logic and other spending flat to down.”
Five trends for 2014
Next, what are the top five trends likely to rule the industry in 2014?
Nalamasu said that the key trends continuing to drive technology in 2014 and beyond include 3D transistors, 3D NAND, and 3D packaging. 3D remains a central theme. In logic, foundries will ramp to 20nm production and begin early transition stages to3D finFET transistors.
With respect to 3D NAND, some products will be commercially available, but most memory manufacturers plan to crossover from planar NAND to vertical NAND starting this year. In wafer level packaging, critical mechanical and electrical characterization work is bringing the manufacturability of 3D-integrated stacked chips closer to reality.
These device architecture inflections require significant advances in precision materials engineering. This spans such critical steps as precision film deposition, precision materials removal, materials modification and interface engineering. Smaller features and atomic-level thin films also make interface engineering and process integration more critical than ever.
Driving technology innovations are mobility applications which need high performance, low power semiconductors. Smartphones, smart watches, tablets and wearable gadgets continue to propel industry growth. Our customers are engaged in a fierce battle for mobility leadership as they race to be the first to market with new products that improve the performance, battery-life, form-factor and user experience of mobile devices.
How is the global semiconductor industry managing the move to the sub 20nm era?
He said that extensive R&D work is underway to move the industry into the sub-20nm realm. For the 1x nodes, more complex architectures and structures as well as new higher performance materials will be required.
Some specific areas where changes and technology innovations are needed include new hard mask and channel materials, selective material deposition and removal, patterning, inspection, and advanced interface engineering. For the memory space, different memory architectures like MRAM are being explored.
FinFETs in 20nm!
By the way, have FinFETs gone to 20nm? Are those looking for power reduction now benefiting?
FinFET transistors are in production in the most advanced 2x designs by a leading IDM, while the foundries are in limited R&D production. In addition to the disruptive 3D architecture, finFET transistors in corporate new materials such as high-k metal gate (HKMG) that help to drastically reduce power leakage.
Based on public statements, HKMG FinFET designs are expected to deliver more than a 20 percent improvement in speed and a 30 percent reduction in power consumption compared to28nm devices. These are significant advantages for mobile applications.
Status of 3D ICs
Finally, what’s the status with 3D ICs? How is Applied helping with true 3D stacking integration?
Nalamasu replied that vertically stacked 3D ICs are expected to enter into production first for niche applications. This is due primarily to the higher cost associated with building 3D wafer-level-packaged (WLP) devices. While such applications are limited today, Applied Materials expects greater utilization and demand to grow in the future.
Applied is an industry leader in WLP, having spear-headed the industry’s development of through silicon via (TSV) technology. Applied offers a suite of systems that enable customers to implement a variety of packaging techniques, from bumping to redistribution layer (RDL) to TSV. Because of work in this area, Applied is strongly positioned to support customers as they begin to adopt this technology.
To manufacture a robust integrated 3D stack, several fundamental innovations are needed. These include improving defect density and developing new materials such as low warpage laminates and less hygroscopic dielectrics.
Another essential requirement is supporting finer copper line/spacing. Important considerations here are maintaining good adhesion while watching out for corrosion. Finally, for creating the necessary smaller vias, the industry needs high quality laser etching to replace mechanical drilling techniques.
The year 2014 is expected to be a major year for the global semiconductor industry. The industry will and continue to innovate!
Apparently, there are huge expectations from certain segments such as the so-called Internet of Things (IoT) and wearable electronics. There will likely be focus on the connected car. Executives have been stating there could be third parties writing apps that can help cars. Intel expects that technology will be inspiring optimism for healthcare in future. As per a survey, 57 percent of people believe traditional hospitals will be obsolete in the future.
Some other entries from 2013 include Qualcomm, who introduced the Snapdragon 410 chipset with integrated 4G LTE world mode for high-volume smartphones. STMicroelectronics joined ARM mbed project that will enable developers to create smart products with ARM-based industry-leading STM32 microcontrollers and accelerate the Internet of Things.
A look at the industry itself is interesting! The World Semiconductor Trade Statistics Inc. (WSTS) is forecasting the global semiconductor market to be $304 billion in 2013, up 4.4 percent from 2012. The market is expected to recover throughout 2013, driven mainly by double digit growth of Memory product category. By region, all regions except Japan will grow from 2012. Japan market is forecasted to decline from 2012 in US dollar basis due to steep Japanese Yen depreciation compared to 2012.
WSTS estimates that the worldwide semiconductor market is predicted to grow further in 2014 and 2015. According to WSTS, the global semiconductor market is forecasted to be up 4.1 percent to $317 billion in 2014, surpassing historical high of $300 billion registered in 2011. For 2015, it is forecasted to be $328 billion, up 3.4 percent.
All product categories and regions are forecasted to grow positively in each year, with the assumption of macro economy recovery throughout the forecast period. By end market, wireless and automotive are expected to grow faster than total market, while consumer and computer are assumed to remain stagnant.
Now, all of this remains to be seen!
Earlier, while speaking with Dr. Wally Rhines of Mentor, and Jaswinder Ahuja of Cadence, both emphasized the industry’s move to 14/16nm. Xilinx estimates that 28nm will have a very long life. It also shipped the 20nm device in early Nov. 2013.
In a 2013 survey, carried out by KPMG, applications markets identified as most important by at least 55 percent of the respondents were: Mobile technology – 69 percent; Consumer – 66 percent; Computing – 63 percent; Alternative/Renewal Energy – 63 percent; Industrial – 62 percent; Automotive – 60 percent; Medical – 55 percent; Wireline Communications – 55 percent.
Do understand that there is always a line between hope and forecasts, and what the end result actually turns out to be! In the meantime, all of us continue to live with the hope that the global semiconductor will carry on flourishing in the years to come. As Brian Fuller, Cadence, says, ‘the future’s in our hands; let’s not blow it!’
Its been warm and sunny in Dubai, UAE, host to the Gitex Technology Week 2013, at the Dubai World Trade Center. Opening today, the show is literally the live wire for the Middle East technology roadmap.
Well, it seems that this show is all about the Big Data and cloud. On Oct. 21st, there is the Cloud Confex, where enterprises can learn how they can achieve the benefits of transformation. Are the CIOs and the businesses really prepared for Big Data? You can find that out by attending the session on Big Data on Oct. 22nd. There is the digital strategies day as well, on Oct. 23rd, where enterprises can find out more about how to integrate mobile and social media into their business models. This session should help you understand what customers or users do online, and more importantly, why they do that!
There are said to be 1,500 or so exhibitors at Gitex 2013. My attention was drawn to the gsmExchange, said to be the global trading platform for mobile phone wholesale since 2000. You can buy or sell mobiles phones as well as refurbished mobile phones at this portal. You can also buy and sell mobile phone accessories as well. Kaspersky Lab has a large booth, catering to the Internet security and mobile security products. Cisco is showcasing its intelligent network products portfolio.
Elsewhere, there’s news about Datawind, and its low-cost phablet for the Indian market at Rs. 6,999 (taxes extra). Cyberoam is showcasing the next generation firewall (NGFW) and its enterprise security offerings. TP-LINK has launched its flagship 802.11ac wireless router, which is providing up to 1750Mbps of wireless bandwidth and set to change the way we look at home networking.
Olivetti is presenting innovative solutions and products whose features will be of particular interest to banks and post offices, such as the revolutionary MB-2 ADF, an all-in-one product for bank front offices that combines specialised printer functions with those of an A4 scanner, a cheque reader and allows the automatic multi-page documents feed thanks to the ADF. It is also displaying the Oliscan A600, a duplex colour scanner, the M206 and M210 multiservice terminals, and so on.
I saw a booth from Dubai Silicon Oasis Authority (DSOA), which is showcasing the park’s hi-tech ecosystem. Five years ago, when I was in Dubai, the director had informed me that the DSOA was large enough to fit in eight wafer fabs! Where are those fabs, dear sirs? Does it seem that the focus has shifted from fabs to providing incentives and state-of-the-art infrastructure to technology companies looking to set up shop in Dubai? We will try and find out, time permitting.
There is a strong presence of the local government, with large booths showcasing their wares. The Dubai Smart Government has introduced several new applications, such as the mobile gateway app – mDubai, mPay app, HR self-service app, MyID and iProc mobile app, and the suggestions and complaints app. Great work!
There are large booths mostly, especially from Etisalat, the Middle East’s leading telecommunications operator and one of the largest corporations in the six Arab countries of the Gulf Co-operation Council, Intel, which is showcasing its enterprise solutions, and Huawei, which is targeting the data centers, as well as enterprises.
There will be more updates tomorrow, as I’ve to rush for a meeting.
Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.
The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.
I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.
I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.
The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.
To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.
To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.
This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.
Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.
This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.
What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.
It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.
Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.
New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.
The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.
At Cadence, the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.
What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.
On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.
Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI).
Complexity is growing exponentially and signoff is the bottleneck. There is an increasing design complexity. Low power is important across markets — from smartphones to datacenters. Time to market remains critical as well. Feature-rich devices are growing the design size.
Timing closure schedule and complexity have been increasing. In fact, up until now, timing closure solutions are said to have not kept pace with design complexity. The number of timing views are increasing with each new process node. The increased margins make timing closure very difficult. Exponential growth in design size and complexity are stretching the analysis capacity. Time in signoff closure has been increasing up to 40 percent of the design flow at 20nm.
The Tempus timing signoff solution is big on performance, accuracy and closure. For performance, it facilitates massively parallelized computation, is scalable to 100s of CPUs and there are optimized data structures. It allows up to 10X faster path-based analysis (PBA) and advanced process modeling for accuracy. Finally, for closure, it provides up to 10X reduction in closure time, is placement and routing aware and offers unlimited MMMC capacity.
Tempus offers an unprecedented performance, and handles 100s of millions of cells flat! It has an innovative hierarchical/incremental analysis. For design closure, the multi-mode, multi-corner (MMMC) is distributed or concurrent. There is physically aware optimization, such as graph- or path-based. The PBA is a detailed view of timing based on slew propagation.
With Tempus, Cadence is solving the design complexity challenge by eliminating the signoff bottleneck and enabling customers to meet power, performance and time-to-market goals.
We are now entering the sub-20nm era. So, will it be business as usual or is it going to be different this time? With DAC 2013 around the corner, I met up with John Chilton, senior VP, Marketing and Strategic Development for Synopsys to find out more regarding the impact of new transistor structures on design and manufacturing, 450mm wafers and the impact of transistor variability.
Impact of new transistor structures on design and manufacturing
First, let us understand what will be the impact of new transistor structures on design and manufacturing.
Chilton said: “Most of the impact is really on the manufacturing end since they are effectively 3D transistors. Traditional lithography methods would not work for manufacturing the tall and thin fins where self-aligned double patterning steps are now required.
“Our broad, production-proven products have all been updated to handle the complexity of FinFETs from both the manufacturing and the designer’s end.
“From the design implementation perspective, the foundries’ and Synopsys’ goal is to provide a transparent adoption process where the methodology (from Metal 1 and above) remains essentially the same as that of previous nodes where products have been updated to handle the process complexity.”
Given the scenario, will it be possible to introduce 450mm wafer handling and new lithography successfully?
According to Chilton: “This is a question best asked of the semiconductor manufacturers and equipment vendors. Our opinion is ‘very likely’.” The semiconductor manufacturers, equipment vendors, and the EDA tool providers have a long history of introducing new technology successfully when the economics of deploying the technology is favorable.
The 300nm wafer deployment was quite complex, but was completed, for example. The introduction of double patterning at 20nm is another recent example in which manufacturers, equipment vendors and EDA companies work together to deploy a new technology.
Impact of transistor variability and other physics issues
Finally, what will be the impact of transistor variability and other physics issues?
Chilton said that as transistor scaling progresses into FinFET technologies and beyond, the variability of device behavior becomes more prominent. There are several sources of device variability.
Random doping fluctuations (RDF) are a result of the statistical nature of the position and the discreteness of the electrical charge of the dopant atoms. Whereas in past technologies the effect of the dopant atoms could be treated as a continuum of charge, FinFETs are so small that the charge distribution of the dopant atoms becomes ‘lumpy’ and variable from one transistor to the next.
With the introduction of metal gates in the advanced CMOS processes, random work function fluctuations arising from the formation of finite-sized metal grains with different lattice orientations have also become important. In this effect, each metal grain in the gate, whose crystalline orientation is random, interacts with the underlying gate dielectric and silicon in a different way, with the consequence that the channel electrons no longer see a uniform gate potential.
The other key sources of variability are due to the random location of traps and the etching and lithography processes which produce slightly different dimensions in critical shapes such as fin width and gate length.
“The impact of these variability sources is evident in the output characteristics of FinFETs and circuits, and the systematic analysis of these effects has become a priority for technology development and IP design teams alike,” he added.
SEMI, USA recently hosted the seminar on ‘Convergence of PV Materials, Test and Reliability: What Really Matters?
Reliability in growing PV industry
Speaking on the importance of reliability to a growing PV industry, Sarah Kurtz, principal scientist, Reliability group manager, NREL, said that confidence in long-term performance is a necessity in the PV industry. Current failure rates are low. There is need to demonstrate confidence so that failure rates will stay low. There has been exponential growth of the PV industry so far. PV is a significant fraction of new installations. It now represents a significant fraction of new electricity generating installations of all kinds.
How does one predict the lifetime of PV modules? There has been a qualification test evolution for JPL block buys. Most studies of c-Si modules show module failures are small. Internal electrical current issues often dominate.
The vast majority of installations show very low PV module failure rates (often less than 0.1 percent). There has been evidence that PV is low risk compared to other investments. To sustain the current installation rate, we need to demonstrate confidence that justifies the annual investment of $100 million or so.
Critical factors in economic viability of PV
DuPont has broad capabilities under one roof. It offers materials, solar cell design, and processes integrated with panel engineering. Speaking about Critical factors in economic viability of PV – materials matter – Conrad Burke, global marketing director, DuPont PV Solutions, said that material suppliers have a distinct advantage to view trends. The industry can expect consolidation among large PV module producers and large materials suppliers.
There is an increasing dependence on materials suppliers for processes, tech support and roadmap. There is renewed attention to long-term reliability and quality of materials in PV products.
There is a race for survival among panel producers. There are dropping prices for solar panels, and quality is getting compromised. There are reduced incentives in established markets. The market will continue to grow. Key factors that determine investment return for PV include lifetime, efficiency and cost.
When materials fail, the consequences are dire. There are failures such as encapsulant discoloration, backsheet failure, glass delamination, etc. Average defect rates in new-build modules has been increasing. Significant number of PV installations do not deliver the projected RoI. The system lifetime is as important as cost and incentives.
Solar cell power continues to improve. There have been improvements from metal pastes and processes. Performance loss impacts the RoI. The US Department of Energy hired JPL to develop 30-year PV modules. Recent cost pressures have led to the dramatic changes in module materials and a lack of transparency.
Analyzing modules from the recent service environments show performance issues. Certification does not mitigate risk. Tests do not predict the actual field performance. He showed tier-1 solar panel manufacturing problems from China, Japan and the USA. Backsheet is critical to protect solar panels. Few materials have lengthy field experience. We will continue to see drop in prices for solar panels and opening of new markets. Focus for PV module makers will remain efficiency, etc.