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Set up strong methodology teams to create better verification infrastructure: Synopsys


Arindam Ghosh

Arindam Ghosh

This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as:

* Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution.
* No or very low investment in building better verification environments (based on best/new methodologies and best practices); instead maintaining older verification environments.
* Compromising on verification completeness because of tape out pressures and time-to-market considerations.

Would you agree that many companies STILL do not know how to verify a chip?

He said that it could be true for smaller companies or start-ups, but most of the major semiconductor design engineers know about the better approaches/methodologies to verify their chips. However, they may not be investing in implementing the new methodologies for multiple reasons and may instead continue to follow the traditional flows.

One way to address these mistakes would be to set up strong methodology teams to create a better verification infrastructure for future chips. However, few companies are doing this.

Are companies realizing this and building an infrastructure that gets you business advantage? He added that some companies do realize this and are investing in building a better infrastructure (in terms of better methodology and flows) for verification.

When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment? Ghosh said that good verification starts as soon as we start designing and architecting the design. Verification leads should start discussing the verification environment components with the lead architect and also start writing the verification plan.

Are folks mistaking by looking at tools and not at the verification process itself? According to him, tools play a major role in the effectiveness of any verification process, but we still see a lot of scope in methodology improvements beyond the tools.

What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities? Ghosh said that there is no single, full-proof recipe for a ‘right’ verification path. It depends on multiple factors, including whether the design is a new product or derivative, the design application etc. But yes, it is very important to do comprehensive verification planning before starting the verification process.

Synopsys is said to be building a comprehensive, unified and integrated verification environment is required for today’s revolutionary SoCs and would offer a fundamental shift forward in productivity, performance, capacity and functionality.  Synopsys’ Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.

Verification Compiler includes:
* Better capacity and compile and runtime performance.
* Next-generation static and formal technology delivering performance improvement and the capacity to analyze a complete SoC (Property checking, LP, CDC, connectivity).
* Comprehensive low power verification solution.
* Verification planning and management.
* Next-generation verification IP and a deep integration between VIP and the simulation engine, which in turn can greatly improve productivity.  The constraint engine is tuned for optimal performance with its VIP library. It has integrated debug solutions for VIP so one can do protocol-level analysis and transaction-based analysis with the rest of the testbench.
* Support for industry standard verification methodologies.
* X-propagation simulation with both RTL and low power simulations.
* Common debug platform with better debug technology having new capabilities, tight integrations with simulation, emulation, testbench, transaction debug, power-aware debug , hw/sw debug, formal, VIP and coverage.

Top five recommendations for verification
What would be Synopsys’ top five recommendations for verification?

* Spend a meaningful amount of time and effort on verification planning before execution.
* Continuously invest in building a better verification infrastructure and methodologies across the company for better productivity.
* Collaborate with EDA companies to develop, evaluate and deploy new technologies and flows, which can bring more productivity to verification processes.
* Nurture fresh talent through regular on and off-the-job trainings (on flows, methodologies, tools, technology).
* Conduct regular reviews of the completed verification projects with the goal of trying to improve the verification process after every tapeout through methodology enhancements.

Categories: Semiconductors

Cadence: Plan verification to avoid mistakes!


Apurva Kalia

Apurva Kalia

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there’s verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

3D remains central theme for Applied in 2014!


Om Nalamasu

Om Nalamasu

Following a host of forecasts for 2014, it is now the turn of Applied Materials with its forecast for the year. First, I asked Om Nalamasu, senior VP, CTO, Applied Materials regarding the outlook for the global semicon industry in 2014.

Semicon outlook 2014
He said that Gartner expects the semiconductor industry to grow in mid-single digits to over $330 billion in 2014.

“In our industry – the semiconductor wafer fab equipment sector – we are at the beginning of major technology transitions, driven by FinFET and 3D NAND, and based a wide range of analyst projections, wafer fab equipment investment is expected to be up 10-20 percent in 2014. We expect to see a year-over-year increase in foundry, NAND, and DRAM investment, with logic and other spending flat to down.”

Five trends for 2014
Next, what are the top five trends likely to rule the industry in 2014?

Nalamasu said that the key trends continuing to drive technology in 2014 and beyond include 3D transistors, 3D NAND, and 3D packaging. 3D remains a central theme. In logic, foundries will ramp to 20nm production and begin early transition stages to3D finFET transistors.

With respect to 3D NAND, some products will be commercially available, but most memory manufacturers plan to crossover from planar NAND to vertical NAND starting this year. In wafer level packaging, critical mechanical and electrical characterization work is bringing the manufacturability of 3D-integrated stacked chips closer to reality.

These device architecture inflections require significant advances in precision materials engineering. This spans such critical steps as precision film deposition, precision materials removal, materials modification and interface engineering. Smaller features and atomic-level thin films also make interface engineering and process integration more critical than ever.

Driving technology innovations are mobility applications which need high performance, low power semiconductors. Smartphones, smart watches, tablets and wearable gadgets continue to propel industry growth. Our customers are engaged in a fierce battle for mobility leadership as they race to be the first to market with new products that improve the performance, battery-life, form-factor and user experience of mobile devices.

How is the global semiconductor industry managing the move to the sub 20nm era?

He said that extensive R&D work is underway to move the industry into the sub-20nm realm. For the 1x nodes, more complex architectures and structures as well as new higher performance materials will be required.

Some specific areas where changes and technology innovations are needed include new hard mask and channel materials, selective material deposition and removal, patterning, inspection, and advanced interface engineering. For the memory space, different memory architectures like MRAM are being explored.

FinFETs in 20nm!
By the way, have FinFETs gone to 20nm? Are those looking for power reduction now benefiting?

FinFET transistors are in production in the most advanced 2x designs by a leading IDM, while the foundries are in limited R&D production. In addition to the disruptive 3D architecture, finFET transistors in corporate new materials such as high-k metal gate (HKMG) that help to drastically reduce power leakage.

Based on public statements, HKMG FinFET designs are expected to deliver more than a 20 percent improvement in speed and a 30 percent reduction in power consumption compared to28nm devices. These are significant advantages for mobile applications.

Status of 3D ICs
Finally, what’s the status with 3D ICs? How is Applied helping with true 3D stacking integration?

Nalamasu replied that vertically stacked 3D ICs are expected to enter into production first for niche applications. This is due primarily to the higher cost associated with building 3D wafer-level-packaged (WLP) devices. While such applications are limited today, Applied Materials expects greater utilization and demand to grow in the future.

Applied is an industry leader in WLP, having spear-headed the industry’s development of through silicon via (TSV) technology. Applied offers a suite of systems that enable customers to implement a variety of packaging techniques, from bumping to redistribution layer (RDL) to TSV. Because of work in this area, Applied is strongly positioned to support customers as they begin to adopt this technology.

To manufacture a robust integrated 3D stack, several fundamental innovations are needed. These include improving defect density and developing new materials such as low warpage laminates and less hygroscopic dielectrics.

Another essential requirement is supporting finer copper line/spacing. Important considerations here are maintaining good adhesion while watching out for corrosion. Finally, for creating the necessary smaller vias, the industry needs high quality laser etching to replace mechanical drilling techniques.

India’s evolving importance to future of fabless: Dr. Wally Rhines

February 3, 2014 2 comments

Dr. Wally RhinesIf I correctly remember, sometime in Oct. 2008, S. Janakiraman, then chairman of the India Semiconductor Association, had proclaimed that despite not having fabs, the ‘fabless India” had been shining brightly! Later, in August 2011, I had written an article on whether India was keen on going the fabless way! Today, at the IESA Vision Summit in Bangalore, Dr, Wally Rhines repeated nearly the same lines!

While the number of new fabless startups has declined substantially in the West during the past decade, they are growing in India, said Dr. Walden C. Rhines, chairman and CEO, during his presentation “Next Steps for the Indian Semiconductor Industry” at the ongoing IESA Vision Summit 2014.

India has key capabilities to stimulate growth of semiconductor companies, which include design services companies, design engineering expertise and innovation, returning entrepreneurs, and educational system. Direct interaction with equipment/systems companies will complete the product development process.

Off the top 50 semicon companies in 2012, 13 are fabless and four are foundries. The global fabless IC market is likely to grow 29 percent in 2013. The fabless IC revenue also continues to grow, reaching about $78.1 billion in 2013.  The fabless revenue is highly concentrated with the top 10 companies likely to account for 64 percent revenue in 2013. As of 2012, the GSA estimates that there aere 1,011 fabless companies.

The semiconductor IP (SIP) market has also been growing and is likely to reach $4,774 million by 2020, growing at a CAGR of 10 percent. The top 10 SIP companies account for 87 percent of the global revenue. Tape-outs at advanced nodes have been growing. However, there are still large large opportunities in older technologies.

IoT will transform industry
It is expected that the Internet of Things (IoT) will transform the semiconductor industry. It is said that in the next 10 years, as many as 100 billion objects could be tied together to form a “central nervous system” for the planet and support highly intelligent web-based systems. As of 2013, 1 trillion devices are connected to the network.

Product differentiation alone makes switching analog/mixed-signal suppliers difficult. Change in strategy toward differentiation gradually raises GPM percentage.

India’s evolving importance to future of fabless
Now, India ranks among the top five semiconductor design locations worldwide. US leads with 507, China with 472, Taiwan with 256, Israel with 150, and India with 120. Some prominent Indian companies are Ineda, Saankhya Labs, Orca Systems and Signal Chip (all fabless) and DXCorr and SilabTech (all SIP).

India is already a leading source of SIP, accounting for 5.3 percent, globally, after USA 43 percent and China 17.3 percent, respectively. It now seems that India has been evolving from design services to fabless powerhouse. India has built a foundation for a fabless future. It now has worldwide leadership with the most influential design teams in the world.

Presently, there are 1,031 MNC R&D centers in India. Next, 18 of the top 20 US semiconductor companies have design centers in India. And, 20 European corporations set up engineering R&D centers in India last year. India also has the richest pool of creative engineering resources and educational institutions in the world. The experience level of Indian engineers has been increasing, but it is still a young and creative workforce. There is also a growing pool of angel investors in India, and also in the West, with strong connections to India.

So, what are the key ingredients to generate a thriving infrastructure? It is involvement and expertise with end equipment. Superb product definition requires the elimination of functional barriers. He gave some examples of foreign “flagged” Indian companies that produced early successes. When users and tool developers work in close proximity, “out-of-the-Box” architectural innovations revolutionize design verification.

FinFETs delivering on promise of power reduction: Synopsys


Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry.

Rich Goldman

Rich Goldman

Global semicon in sub 20nm era
How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the history of mankind is not for the faint of heart. Keeping up with Moore’s Law has always required significant investment and ingenuity.

“The sub-20nm era brings additional challenges in device structures (namely FinFETs), materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over the revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception.

“Semiconductor companies focused on mobile and the Internet of Things are also thriving as their market quickly expands. Semiconductor companies who dominate their space in such segments as automotive, mil/aero and medical are also doing quite well, while non-leaders find rough waters.”

Performance of FinFETs
Have FinFETs gone to below 20nm? Also, are those looking for power reduction now benefiting?

He added that 20nm was a pivotal point in advanced process development. The 20nm process node’s new set of challenges, including double patterning and very leaky transistors due to short channel effects, negated the benefits of transistor scaling.

To further complicate matters, the migration from 28nm to 20nm lacked the performance and area gains seen with prior generations, making it economically questionable. While planar FET may be nearing the end of its scalable lifespan at 20nm, FinFETs provide a viable alternative for advanced processes at emerging nodes.

The industry’s experience with 20nm paved the way for an easier FinFET transition. FinFET processes are in production today, and many IC design companies are rapidly moving to manufacture their devices on the emerging 16nm and 14nm FinFET-based process geometries due to the compelling power and performance benefits. Numerous test chips have taped out, and results are coming in.

“FinFET is delivering on its promise of power reduction. With 20nm planar FET technologies, leakage current can flow across the channel between the source and the drain, making it very difficult to completely turn the transistor off. FinFETs provide better channel control, allowing very little current to leak when the device is in the “off” state. This enables the use of lower threshold voltages, resulting in better power and performance. FinFET devices also operate at a lower nominal voltage supply, significantly improving dynamic power.”
Read more…

Can 2014 be a major year for global semicon industry?


The year 2014 is expected to be a major year for the global semiconductor industry. The industry will and continue to innovate!

Apparently, there are huge expectations from certain segments such as the so-called Internet of Things (IoT) and wearable electronics. There will likely be focus on the connected car. Executives have been stating there could be third parties writing apps that can help cars. Intel expects that technology will be inspiring optimism for healthcare in future. As per a survey, 57 percent of people believe traditional hospitals will be obsolete in the future.

Some other entries from 2013 include Qualcomm, who introduced the Snapdragon 410 chipset with integrated 4G LTE world mode for high-volume smartphones. STMicroelectronics joined ARM mbed project that will enable developers to create smart products with ARM-based industry-leading STM32 microcontrollers and accelerate the Internet of Things.

A look at the industry itself is interesting! The World Semiconductor Trade Statistics Inc. (WSTS) is forecasting the global semiconductor market to be $304 billion in 2013, up 4.4 percent from 2012. The market is expected to recover throughout 2013, driven mainly by double digit growth of Memory product category. By region, all regions except Japan will grow from 2012. Japan market is forecasted to decline from 2012 in US dollar basis due to steep Japanese Yen depreciation compared to 2012.

WSTS estimates that the worldwide semiconductor market is predicted to grow further in 2014 and 2015. According to WSTS, the global semiconductor market is forecasted to be up 4.1 percent to $317 billion in 2014, surpassing historical high of $300 billion registered in 2011. For 2015, it is forecasted to be $328 billion, up 3.4 percent.

All product categories and regions are forecasted to grow positively in each year, with the assumption of macro economy recovery throughout the forecast period. By end market, wireless and automotive are expected to grow faster than total market, while consumer and computer are assumed to remain stagnant.

Now, all of this remains to be seen!

Earlier, while speaking with Dr. Wally Rhines of Mentor, and Jaswinder Ahuja of Cadence, both emphasized the industry’s move to 14/16nm. Xilinx estimates that 28nm will have a very long life. It also shipped the 20nm device in early Nov. 2013.

In a 2013 survey, carried out by KPMG, applications markets identified as most important by at least 55 percent of the respondents were: Mobile technology – 69 percent; Consumer – 66 percent; Computing – 63 percent; Alternative/Renewal Energy – 63 percent; Industrial – 62 percent; Automotive – 60 percent; Medical – 55 percent; Wireline Communications – 55 percent.

Do understand that there is always a line between hope and forecasts, and what the end result actually turns out to be! In the meantime, all of us continue to live with the hope that the global semiconductor will carry on flourishing in the years to come. As Brian Fuller, Cadence, says, ‘the future’s in our hands; let’s not blow it!’

What does it take to create Silicon Valley!

December 29, 2013 1 comment

I was pointed out to a piece of news on TV, where a ruling chief minister of an Indian state apparently announced that he could make a particular state of India another Silicon Valley! Interesting!!

First, what’s the secret behind Silicon Valley? Well, I am not even qualified enough to state that! However, all I can say is: it is probably a desire to do something very different, and to make the world a better place – that’s possibly the biggest driver in all the entrepreneurs that have come to and out of Silicon Valley in the USA.

If you looked up Wikipedia, it says that the term Silicon Valley originally referred to the region’s large number of silicon chip innovators and manufacturers, but eventually, came to refer to all high-tech businesses in the area, and is now generally used as a metonym for the American high-technology sector.

So, where exactly is India’s high-tech sector? How many Indian state governments have even tried to foster such a sector? Ok, even if the state governments tried to foster, where are the entrepreneurs? Ok, an even easier one: how many school dropouts from India or even smal-time entrepreneurs have even made a foray into high-tech?

Right, so where are the silicon chip innovators from India? Sorry, I dd not even hear a word that you said? Can you speak out a little louder? It seems there are none! Rather, there has been very little to no development in India, barring the work that is done by the MNCs. Correct?
hsinchuOne friend told me that Bangalore is a place that can be Silicon Valley. Really? How?? With the presence of MNCs, he said! Well, Silicon Valley in the US does not have MNCs from other countries, are there? Let’s see! Some companies with bases in Silicon Valley, listed on Wikipedia, include Adobe, AMD, Apple, Applied Materials, Cisco, Facebook, Google, HP, Intel, Juniper, KLA-Tencor, LSI, Marvell, Maxim, Nvidia, SanDisk, Xilinx, etc.

Now, most of these firms have setups in Bangalore, but isn’t that part of the companies’ expansion plans? Also, I have emails and requests from a whole lot of youngsters asking me: ‘Sir, please advice me which company should I join?’ Very, very few have asked me: ‘Sir, I have this idea. Is it worth exploring?’

Let’s face the truth. We, as a nation, so far, have not been one to take up challenges and do something new. The ones who do, or are inclined to do so, are working in one of the many MNCs – either in India or overseas.

So, how many budding entrepreneurs are there in India, who are willing to take the risk and plunge into serious R&D?

It really takes a lot to even conceive a Silicon Valley. It takes people of great vision to build something of a Silicon Valley, and not the presence of MNCs.

Just look at Hsinchu, in Taiwan, or even Shenzhen, in China. Specifically, look up Shenzhen Hi-Tech Industrial Park and the Hsinchu Science Park to get some ideas.

How’s global semicon industry performing in sub-20nm era?


Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.

Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.

Jaswinder Ahuja

Jaswinder Ahuja

Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.

“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”

When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.

Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.

The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.

Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.

Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.

FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?

Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.

Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.
Read more…

Xilinx announces 20nm All Programmable UltraSCALE portfolio


Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.

Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.

“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”

Virtex UltraScale device.

Virtex UltraScale device.

Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.

* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.

* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.

KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.

There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.

Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”

The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.

There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite.
UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.

Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.

Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.

“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”

The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.

UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.

Outlook 2014: Xilinx bets big on 28nm


Neeraj Varma

Neeraj Varma

We are in December, and its time for outlook 2014! First, I met up with Neeraj Varma, director-Sales, India, Xilinx. He said: “We expect the 28nm to do really well. From Apr. 13-Mar. 14, we expect revenues worth $250 milion from the 28nm line.

“We are now looking at the embedded market – and expect about $2 billion serviceable available market (SAM). We are looking at $8 billion SAM at the ASIC/ASSP displacement market, and of course $6 billion SAM for core PLD.” After a long time, Xilinx has been seeing positive capex. “We are entering a growth cycle for service providers and enterprises,” he added.

A macro view of capex equipment spend is driven by LTE 27.2 percent at 2011-16, and optical networks 15.9 percent. The other areas include data center, enterprise switching and routing, and service provider switching and routing. Next, 3D ICs will enable Nx100G OTN, 400G OTN, MuxSAR, as well as top of the rack switch, I/O virtualization.

Earlier, there were less than 50 ASICs start in communications in the top 10 OEMs. There were less than 20 28nm ASIC starts in at top 10 OEMs. As of 2012, less than 50 percent of the top 16 ASSPs vendors were losing money. Customer needs are diverse now. Companies end up over designing a chip. People end up paying for what trey are not using.

Xilinx is offering the SMARTCORE IP for smarter networks and data centers. “40 percent of our wins have been achieved by integrating or displacing ASICs and ASSPs,” he said. “We have 25 percent total wins across a broad set of apps/portfolio.”

Some other gains for Xilinx:
* Xilinx gained 3 percent increase in PLDs.
* In wired and data centers, it has 12-percent CAGR from 2013-16.
* In wireless, it has 10-12 percent CAGR.
* In automotive smarter vision, it has 20 percent CAGR growth.
* In industrial, scientific and medical (ISM), it has 12 percent CAGR growth.
* In FY13E-FY16E, Xilinx expects to grow 8-12 percent, and has plans to increase the R&D revenue to 8.6 percent.

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