Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”

SEP 2 IP-based energy management for home

What exactly is smart energy profile (SEP 2) IP-based energy management for the home? Introducing the SEP 2, Tobin Richardson, chairman and CEO, ZigBee Alliance said ZigBee smart energy is the standard of choice for home area networks (HANs).

About 40+ million ZigBee electric meters are being deployed. ZigBee smart energy is being enhanced by network/communications options, support for forward-looking developments, etc. SEP 2 is a joint effort with the HomePlug Alliance. There is a vision of MAC/PHY agnostic SmartEnergy profile.

Robby Simpson, SEP 2 Technical Working Group Chair, system architect, GE Digital Energy, provided the features and benefits of Smart Energy. Features include price communication, demand response and load control, energy usage information/metering data, prepayment metering, text messaging, plug-in electric vehicles, distributed energy resources, billing communication, etc.

Example applications are many, such as smartphones, ESI in the sky, tablets, TVs, plug-in electric vehicles, PCs, solar inverters, thermostats, energy management systems, smart meters, building management systems, smart appliances, etc. There is support for a variety of architectures. The use of IP eases convergence and architecture changes. A consortium for SEP 2 interoperability (CSEP) has been established.

Skip Ashton, ZigBee Arch. review committee chair, senior apps director,  Silicon Labs said implementations of SEP 2 are available from a number of companies and across several MAC/PHYs. All standard documents are available for review.

Jeff Gooding, Southern California Edison (SCE), spoke about creating SEP 2 energy ecosysyems. SEP 2 can bridge multi-platform customer technologies to create a rich ecosystem. SEP 2 customer focused solutions can allow the utilities and energy service providers to use any customer communication channel. SEP 2 pilots at SCE include a gateway pilot and a smart charging pilot. Both are separate pilots.

Convergence of PV materials, test and reliability: What really matters?

SEMI, USA recently hosted the seminar on ‘Convergence of PV Materials, Test and Reliability: What Really Matters?

Reliability in growing PV industry
Speaking on the importance of reliability to a growing PV industry, Sarah Kurtz, principal scientist, Reliability group manager, NREL, said that confidence in long-term performance is a necessity in the PV industry. Current failure rates are low. There is need to demonstrate confidence so that failure rates will stay low. There has been exponential growth of the PV industry so far. PV is a significant fraction of new installations. It now represents a significant fraction of new electricity generating installations of all kinds.

How does one predict the lifetime of PV modules? There has been a qualification test evolution for JPL block buys. Most studies of c-Si modules show module failures are small. Internal electrical current issues often dominate.

The vast majority of installations show very low PV module failure rates (often less than 0.1 percent). There has been evidence that PV is low risk compared to other investments. To sustain the current installation rate, we need to demonstrate confidence that justifies the annual investment of $100 million or so.

Critical factors in economic viability of PV
DuPont has broad capabilities under one roof. It offers materials, solar cell design, and processes integrated with panel engineering. Speaking about Critical factors in economic viability of PV – materials matter – Conrad Burke, global marketing director, DuPont PV Solutions, said that material suppliers have a distinct advantage to view trends. The industry can expect consolidation among large PV module producers and large materials suppliers.

There is an increasing dependence on materials suppliers for processes, tech support and roadmap. There is renewed attention to long-term reliability and quality of materials in PV products.

There is a race for survival among panel producers. There are dropping prices for solar panels, and quality is getting compromised. There are reduced incentives in established markets. The market will continue to grow. Key factors that determine investment return for PV include lifetime, efficiency and cost.

When materials fail, the consequences are dire. There are failures such as encapsulant discoloration, backsheet failure, glass delamination, etc. Average defect rates in new-build modules has been increasing. Significant number of PV installations do not deliver the projected RoI. The system lifetime is as important as cost and incentives.

Solar cell power continues to improve. There have been improvements from metal pastes and processes. Performance loss impacts the RoI. The US Department of Energy hired JPL to develop 30-year PV modules. Recent cost pressures have led to the dramatic changes in module materials and a lack of transparency.

Analyzing modules from the recent service environments show performance issues. Certification does not mitigate risk. Tests do not predict the actual field performance. He showed tier-1 solar panel manufacturing problems from China, Japan and the USA. Backsheet is critical to protect solar panels. Few materials have lengthy field experience. We will continue to see drop in prices for solar panels and opening of new markets. Focus for PV module makers will remain efficiency, etc.

Coto announces MEMS based magnetically operated switch

Stephen Day.

According to Stephen Day, VP of Technology, Coto Technology has the number 1 share in reed relays and relay products. The Coto brand is associated with the broadest portfolio, best in class quality, dedicated technical support, and a provider of innovative solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Coto has announced the RedRock, a new MEMS based magnetically operated switch. The RS-A-2515 is the world’s smallest wafer level packaged magnetically operated reed switch. It consumes zero power, measures 2mm3 in footprint and switches at less than 0.3W. It delivers high reliability and surface mount package.

The small footprint means use of less PCB real estate, no operate power means a longer battery life. The low switching power leads to higher reliability. The high directionality leads to resistance to stray fields. Hot switchable feature leads to higher reliability.

Together, Coto has managed to combine the best of two worlds — traditional reed switches with MEMS processing. There is high aspect ratio microfabrication (HARM). This is the first commercially available switch. It produces structures that generate strong contact closure forces. The forces are many times greater than the previous MEMS based magnetic switches. It also enables hot switching up to several hundred milliwatts.

HARM is the key to making it all possible. The benefits are many, from temperature rise vs. carry current, to RedRock contact life test, 1V 1 mA hot-switched load. RedRock allows for small size, zero power consumption and high power switching.

At the moment, Coto is leveraging RedRock into high growth applications. In the future, Coto will integrate sensor solution as well. RedRock’s unique combination of features include reed — no power and high current, and MEMS — no power and small size, as well as GMR/Hall — small size and high current — to deliver the RedRock, which features no power, small size and high current.

Dr. Wally Rhines on global semiconductor industry trends for 2013

It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.

Status of global EDA industry

Dr. Wally Rhines.

First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”

For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.

Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.

In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.

DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.

Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”

According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”

“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.

Tensilica to expand Cadence IP footprint in SoCs

Chris Rowan.

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.

Algotochip building ecosystem with IP providers in targeted markets

Satish Padmanabhan.

Algorithm-to-chips is Algotochip’s mission. It turns algorithms into chips by converting your behavioral algorithm C-code into architecture C-code into RTL into GDS-II.

Speaking about architecture evolution at the 13th Global Electronics Summit at Santa Cruz, USA, Satish Padmanabhan, CTO and founder, Algotochip, said that the interconnect between CPU and all the HA blocks needs to be determined.

The market approach includes building an ecosystem with leading IP providers in targeted markets. Some areas Algotochip is looking at are LTE and smart grid markets.

Nitto Denko is committed to support Algotochip moving forward. Year 2013 will see significant investment increases in terms of engineering resources, as well as sales and marketing organization to cover USA, China and Japan.

Algotochip is showing that its technology is sound in improving system hardware and software partitioning and first time right design. The LTE turbo decoder performances in terms of throughput, power and gates count is showing the benefits of Algotochip BlueBox. The company is now building an ecosystem around its technology.

ARM Holdings and Tensilica are the first of the few partners that Algotochip wants to collaborate with to improve the overall time-to-market of digital design of the SoC, ASIC and FPGA, etc.

CSSPs — custom to catalog solutions from Quicklogic

Andy Pease.

QuickLogic is a Silicon Valley-based fabless semiconductor company. It is an innovator of CSSPs or customer-specific standard products. It is focused on high-growth mobile markets such as consumer,  enterprise and mobile enterprise.

Speaking at the ongoing 13th Global Electronics Summit in Santa Cruz, USA, Andy Pease president and CEO, QuickLogic, said it does all the drivers that actually need to be inside all the application processors. It is trying to solve the OEM dilemma for mobile market. There are the Android + ARM camp and the Windows + x86 camp, respectively. One way to solve the problem is to do software overlay to Android/Windows.

CSSPs enables the OEM hardware differentiation. It allows fastest time-to-market for custom silicon. It also extends the battery life. The reference designs showcases proven system blocks and capabilities. It is a known good starting point for CSSP development.

The application development dilemma includes optimizing for the specific vertical vs. horizontal markets. When does the integration happen for new standards? Also, how long does a company need to keep mature standards?

QuickLogic has inrtroduced catalog CSSPs. These are ready-to-integrate solutions. They are architectured, developed and verified with application processor vendors.

Platform diversity enables solutions 100 percent programmable for ultimate flexibility. Hybrid programmable/ASIC is provided for common applications requiring some customization. The go-to-market strategy includes complete solutions. It includes software drivers, firmware and application reference codes. It is a collaborative customer model.

A partner challenge could be to re-position its existing AP in new, adjacent markets and applications. QuickLogic’s solution is to provide custom design and software drivers to bridge the AP with camera interface to different types of image capture devices.

Another example is in SD memory. The premier challenge is to adapt the existing baseband processor to emerging market requirements. QuickLogic’s solution is to develop multiple custom designs and software drivers to bridge the baseband with SD memory.

Catalog CSSPs emable the OEM engineers expanded functionality beyond the application processor’s native capability. They expand the served available market of application/embedded processor companies. It scales QuickLogic’s resources across multiple end markets, applications and customers.

Xilinx stays a generation ahead!

Tom Feist.

Today, the challenge is all about abstraction and putting automation around it. Productivity is automation and abstraction. Tom Feist, senior marketing director, Design Methodology Marketing, Xilinx said that the company’s strategy has been about All Programmable abstractions. He was speaking at the ongoing 13th Global Electronics Summit being held in Santa Cruz, USA.

Today’s hardware design abstractions include accelerated time to integration, abstracting hardware. For IP abstractions, Xilinx has introduced the IP integrator. It enables IP re-use and time to integration. The Vivado uses multiple plug-and-play IP. Vivado IP integrator is co-optimized for platforms and for silicon, respectively.

Vivado IP integrator has features such as correct-by-construction and automated IP systems. Vivado high-level synthesis allows C/C++ abstractions. Xilinx introduced the OpenCV library, accelerating smarter vision. It supports frame-level processing library for PS. It also supports pixel processing interfaces and basic functions for analytics.

Mathworks has model based abstraction. The automatic C and HDL code generation is supported from the same algorithmic level.

Hardware/software partitioning is supported for Zynq-7000 AP SoCs.  There are comprehensive video, motor control and signal processing IP libraries. There are automated workflows targeting Xilinx platforms.

Xilinx is also working with National Instruments. The automated C and HDL code generation is from the same graphical syntax in the LabVIEW IDE. It automatically generates a hardware implementation to meet requirements, abstracting Xilinx tool flow. There is a comprehensive software, hardware and I/O platform for creating control and monitoring systems.

Abstraction evolution has evolved to system level abstraction. It is abstracting all hardware through an increasing layer of automation.

All Programmable realization empowers software and systems engineers. There is a common compilation environment for heterogenous systems. It consumes C, C++ or OpenCL and libraries with user directives. There is automated flow — the user determines the program modules that run on various components.

The Vivado Design Suite 2013 abstractions with IP based design, C, C++, SystemC and OpenCV is new. Mathworks and National Instruments system level design abstractions with new levels of automation is emerging. Xilinx’s vision has been to empower the software and systems engineers by extending abstractions and automation.

Exar serving high-growth areas with innovative value-added solutions

Louis DiNardo.

Exar Corp., established 1971, is headquartered in Fremont, USA, and has design centers in Silicon Valley and Hangzhou, China. Louis DiNardo, president and CEO, Exar, said that the company’s strategic model is to serve high-growth markets with innovative value-added solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Exar offers solutions that includes high performance analog-mixed signal as well as data management solutions. Its current market focus is on networking and storage, industrial and embedded systems, and communications infrastructure. It is focusing on power management products, connectivity products and data management solutions.

Power management products include those for analog power management such as switching regulators, switching controllers, linear regulators, supervisory controllers, etc, For programmable power, Exar focuses on multiple output synchronous buck controllers.

Some of the products include POWER, the Exar Programmable PowerSuite 5.0. Recently, Calceda has been powering servers with the PowerXR technology.

For data compression and security, Exar is offering hardware acceleration and software solutions meant for compression and decompression, acceleration, encryption and decryption. There are high growth markets supporting social networking, industrial Internet and financial technology as well.

Exar’s Panther I is a first generation compression/security engine with the PCIe interface. The Panther II is a second generation compression and security engine with PCIe and FPGA interface.