Cadence Design Systems recently introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers.
Rahul Deokar, product management director, said: “We are addressing designer challenges in – high performance design, giga-scale design and advanced node design. The first challenge is the PPA – power performance and area. Next challenge is to handle giga-scale designs with efficient turnaround time. The third key challenge is fast time-to-market on advanced 28nm/20nm design.”
With this latest release, Cadence provides the industry’s best PPA. Second, it is providing 1 billion gates on designer desktops. Third, it provides the fastest path to 20nm digital design. In the new announcement, there are three new technologies – GigaOpt + CCOpt, GigaFlex, and 20nm double patterning.
Cadence has introduced “GigaOpt” – a common optimization engine that unifies physical synthesis and optimization. GigaOpt provides designers globally optimal results across the front-end and back-end of the design flow. And that results in the benefit of the industry’s best PPA for high-performance design. GigaOpt has been designed from scratch to be multi-threaded, which makes it ultra fast and ultra scalable.
Another innovation, CCOpt, is the first and only technology in EDA to unify clock tree synthesis and physical optimization. CCOpt is now an integral part of the Encounter flow accelerating design closure with the best PPA. CCOpt facilitates:
* 10 percent improvement in design performance and total power.
* 30 percent reduction in clock power and area.
* 30 percent reduction in IR drop.
The Encounter flow now allows 1 billion gates to be enabled on the designer’s desktops. This is done with the new GigaFlex abstraction technology. It is the first and only technology in EDA that enables flexible, accurate abstraction adaptable to the flow stage. There is 10X capacity and TAT gains on 100 million+ instance designs. GigaFlex abstraction technology allows accurate, early physical modeling, concurrent top-and-block interface optimization, and concurrent hierarchical closure and late-stage ECO. Read more…
This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.
The latest Cowan LRA model parameter update incorporates 2011’s monthly sales results, thereby incorporating 28 years of historical, global actual monthly semiconductor sales as gathered, tracked and published by the WSTS.
Cowan has carried out the necessary mathematical computations in order to update the complete set of linear regression parameters embedded in the Cowan LRA forecast model. This update to the model’s parameters thus reflects 28 years (1984 to 2011) of historical global semiconductor sales numbers.
Therefore, the table given here has provided summarizes the latest model’s 2012 sales and sales growth expectations as a function of the model’s range (low, expected and high) for January 2012’s sales forecast estimates as put out by the updated model.
Note that the Cowan LRA Model’s expected 2012 sales growth (of 3.3 percent) relative to 2011 sales is slightly less bullish than the WSTS’s adjusted autumn 2011 sales growth forecast of 3.6 percent versus WSTS’s autumn 2011’s forecasted sales growth of 2.6 percent.
Symantec presented its latest Intelligence Report with the following highlights:
* Spam – 74.8 percent in September (a decrease of 1.1 percentage points since August 2011).
* Phishing – One in 447.9 emails identified as phishing (a decrease of 0.26 percentage points since August 2011).
* Malware – One in 188.7 emails in September contained malware (an increase of 0.04 percentage points since August 2011).
* Malicious Web sites – 3,474 Web sites blocked per day (an increase of 1 percent since August 2011).
* 44.6 percent of all malicious domains blocked were new in September (an increase of 10.0 percentage points since August 2011).
* 14.5 percent of all Web-based malware blocked was new in September (a decrease of 2.9 percentage points since August 2011).
* Malicious emails masquerade as office printer messages.
* Spammers exploit WordPress vulnerability to promote pharmaceutical spam Web sites Fake Offers with Fake Trust Seals. (One hopes WordPress is aware of this and taking remedial action!)
The spam rate was 74.8 percent, as against last month’s 75.9 percent. The top five geographies are Saudi Arabia 84 percent, Russian Federation 79.9 percent, Malaysia 79.8 percent, Luxembourg 79.1 percent and Italy 78.6 percent. The top five verticals targeted are automotive 77.8 percent, education 77.2 percent, marketing/media 76.4 percent, non-profit 76.4 percent and manufacturing 76.2 percent.
As for spam sources, US leads with 47.5 percent of spam originating from there. India at 9.6 percent, UK at 8.1 percent, Brazil at 7.6 percent, Russian Federation at 6.7 percent, China at 5,4 percent, Germany at 4.3 percent, Vietnam at 3.8 percent, Japan at 3.8 percent and Canada at 3 percent, make up the top 10 countries.
As for virus, 72 of email-borne malware was associated with variants of generic polymorphic malware, including Bredolab, Sasfis, SpyEye and Zeus variants.
New malware and spyware sites are appearing per day. Around 44.6 percent of all malicious domains blocked were new in September; an increase of 10 percentage points compared with August. Also, 14.5 percent of all Web-based malware blocked was new in September; a decrease of 2.9 percentage points since August.
Next, 20.8 percent of the most frequently blocked malware last month was identified and blocked using generic detection.
August 2010’s ‘actual’ global semiconductor sales numbers are scheduled to be released by the WSTS, namely the August HBR (Historical Billings Report) on or about October 4.
In anticipation of the WSTS release Cowan has shared an analysis feature of the Cowan LRA Model for forecasting worldwide semiconductor sales; namely, the ability to provide a ‘look ahead’ scenario analysis for 2010’s global semiconductor sales forecast as a function of next month’s (in this case August’s) actual global semi sales estimate.
The specifics of the scenario analysis are presented in the following paragraphs and detailed in the scenario analysis matrix table provided here.
In order to demonstrate this capability, Cowan has selected a range in possible August 2010 sales; in this particular scenario analysis, a sales range from $23.95 billion to $26.95 billion in increments of $0.5 billion was chosen as listed in the first column of the table.
This estimated range of actual sales is ‘centered around’ the actual August sales forecast estimate of $25.448 billion as determined by last month’s (July) run of the model. The corresponding August 3MMA sales forecast estimate that the model put forth is $25.723 billion.
The overall year 2010 sales forecast estimate for each assumed estimated August sales number over the selected range of August actual sales estimates is calculated by the model, and is shown in the second column of the table.
The third column reveals the resulting yr-o-yr sales growth estimates compared to year 2009’s actual sales (of $226.3 billion).
The fourth and fifth columns show the corresponding three Month Moving Average (3MMA) sales estimate and the associated year-on-year sales growth relative to August 2009’s 3MMA sales (of $19.381 billion), respectively.
Finally, the sixth column lists the associated Momentum Indicator (MI), which is defined and discussed below.
The MI is defined as the percent difference between the actual sales for a given month — in this case July 2010’s just published actual global sales of $24.568 billion and the forecasted sales estimate for July 2010, that is, $23.388 billion, which was calculated and published last month.
The MI can be either positive or negative and is a measure of the percent deviation of the actual monthly sales number from the previous month’s prediction derived by the model’s linear regression analysis of the past 26 years of historical, actual monthly global “sales experience” as gathered and published, each month, by the WSTS.
Note: August 2010’s sales forecast estimate is projected to be $25.448 billion. Read more…
I’ve just returned from Mentor Graphics’ EDA Tech Forum 2010, titled: Delivering the latest in 10X design improvements. The opening keynote by Pravin Madhani, GM, Place and Route Division, Mentor, could have been better — well, Dr. Walden C. Rhines, chairman and CEO, Mentor, had also delivered a similar lecture at this year’s VLSID 2010 conference.
However, the other two keynotes — by Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, and Manjunath Hebbar, VP & Head – Strategic Services, HCL Technologies Ltd, lived up to their billing.
The photomask industry is between the proverbial hard rock and the hard place. For instance, at 32nm, the mask cost works out to be $2 million today. In his keynote, Madhani said that the manufacturing industry would surely figure out a way to control mask costs.
Even fab costs are pretty high today — estimated at $50 billion in 2010, that is ~10 percent of the annual market. The global fab industry continues to figure out how to decrease costs. While design costs are projected to grow logarithmically, cost per function will continue to decline long after Moore’s Law is obsolete.
So, will we have any use for so many transistors? Down the years, growth in unit volumes has always distinguished the semiconductor industry. The semicon industry has been growing at 13 percent (10-year CAGR), while transistors have grown at 49 percent. These sit very well, as compared to say, computers – 9.3 percent, steel — 5.3 percent, and automobiles — 0.1 percent. The 49 percent transistor growth drives the semicon industry.
Madhani said that the note/netbook market seems to have several years of growth ahead. The Apple iPad has also created a new segment. Cell phone adoption has been in high-growth mode in the emerging markets. Smartphones are changing the video dynamics.
So, will applications require 10K more transistors by 2018? And, do we have the necessary design tools? Well, there will likely be a ~10K increase in transistors over the next eight years, going up to 40 billion transistors by 2018. Therefore, the industry will require tools ready now in order to design for 2018.
Four principal areas will require 10X improvements in design methodologies — system level design, verification, embedded software development, and back-end physical design and test. A 10X increase in the number of transistors will also require 1000X increase in verification.
In summary, reduction in costs per functionality will continue on a predictable learning curve long after Moore’s law is obsolete. The industry will also witness ~10X increase in transistors over the next eight years, leading up to 40 billion transistors by 2018.
Here are the latest forecast results for 2010 global semicon sales estimates associated with the forecasting model — the Cowan LRA model for predicting worldwide semicon sales.
The table provided below summarizes the latest updated global semiconductor sales forecast estimates derived from the Cowan LRA Model and is based upon the just published (by the WSTS) February 2010 actual sales results.
The updated sales forecast estimate for 2010 (of $298.88 billion) shows a large drop from last month’s forecast estimate (of $316.20 billion).
This corresponds to a decrease in the year-over-year sales growth estimate of 7.6 percentage points, namely from 39.7 percent to 32.1 percent.
It should be noted — the latest WSTS actual monthly sales numbers for Feb. reveal a (strong) downward revision to last month’s Jan sales (down $0.530 billion) as summarized here.
The Cowan LRA Model, however, “turns” this lagging monthly sales number into a “leading indicator” by virtue of its near-term forecasting capability looking out over the next five quarters.
This is the “beauty” of the model and, therefore, makes it dynamic in the sense that it can be run each month utilizing the most recent actual global S/C sales number published by the WSTS. Thus it allows “rigorous tracking” of the near-term sales forecast outlook for the global semiconductor industry on an “almost” real-time basis.
Consequently, the model’s monthly sales forecasts do not “sit still” but “evolve” with each month’s latest sales number. Since conditions change rapidly and unexpectedly in the semiconductor industry, market forecasters are hard pressed to keep up with these changes.
Intersolar North America successfully concluded its seventh annual show in the heart of the United States’ largest solar market, California. More than 17,000 visitors from 74 countries visited 530 exhibitors.
The show had the latest innovations in the photovoltaic, energy storage, balance of systems, mounting and tracking systems, and solar heating and cooling market sectors.
It just shows how the USA has evolved as a leading market for solar PV over the years. One could feel USA creeping up on China! Which brings me to the other significant news.
Recently, there was news regarding the USA-China solar dispute. USA has won huge anti-dumping tariffs in the US-China solar panel trade case. A preliminary decision by the US Department of Commerce has imposed significant tariffs on Chinese solar modules in the anti-dumping portion of the case.
The decision has also closed SolarWorld’s “loophole,” which is said to have allowed Chinese module manufacturers to use Taiwanese cells in their modules, circumventing US trade duties.
Will this affect the Chinese PV module suppliers? Perhaps, not that much. Why so? China itself has a very huge domestic market for solar PV. They can continue to do well in China itself. It can also sell solar PV modules in India, as well, besides other regions in the Asia Pacific.
That brings me back to Intersolar North America 2014. Why was there such a low presence of Indian companies? The exhibitor list for the show reads only two — Lanco Solar Pvt Ltd and Vikram Solar Pvt Ltd. Where are the others?
If one looks at the Ministry for New and Renewable Energy (MNRE) website, there is a notification stating that a National Solar Mission (NSM) is being implemented to give a boost to solar power generation in the country. It has a long-term goal of adding 20,000 MWp of grid-connected solar power by 2022, to be achieved in three phases (first phase up to 2012-13, second phase from 2013 to 2017 and the third phase from 2017 to 2022).
Well, the MNRE has also put up a release stating complaints received about the non-function of the systems installed by channel partners. Without getting into details, why can’t Indian suppliers get to the ground and work up solidly? Some of the complaints are actually not even so serious. System not working. Channel partner not attending complaint! And, plant not working due to inverter (PPS) burnt down. These should be attended to quickly, unless, there is some monetary or other issue, which, at least, I am not aware of!
The CNA Corp.s Energy, Water, & Climate division released two studies earlier this week, which found that cost-effective options that power plants can use to cut water use can also help plants reduce CO2 emissions.
The first report, Capturing Synergies Between Water Conservation and Carbon Dioxide Emissions in the Power Sector, focuses on strategy recommendations based on analyses of water use and CO2 emissions in four case studies, which are detailed in the second report, A Clash of Competing Necessities: Water Adequacy and Electric Reliability in China, India, France, and Texas.
CNA’s Energy, Water, & Climate division released two studies, which found that cost-effective options that power plants can use to cut water use can also help plants reduce CO2 emissions.
“It’s a very important issue,” said lead study author Paul Faeth, director of Energy, Water, & Climate at CNA. “Water used to cool power plants is the largest source of water withdrawals in the United States and France, and a large source in China and India.”
“The recommendations in these reports can serve as a starting point for leaders in these countries, and for leaders around the world, to take the steps needed to ensure the reliability of current generating plants and begin planning for how to meet future demands for electric power.”
India needs to learn from the Intersolar North America show. It also needs to look carefully at CNA’s reports. It is always great and good work that attracts global attention. India has all of the requred capabilities to do so!
Thanks to the Enable450 newsletter, sent out by Malcolm Penn, CEO, Future Horizons, here is a piece on the Metro450 Conference 2014, held earlier this year in Israel.
Metro450 is an Israel-based consortium with the goal of helping the metrology companies advance in their fields. The consortium’s members include metrology and related companies, as well as academics who support these companies by performing basic research.
The conference was sponsored by the Israeli Chief Scientist Office, by Applied Materials Israel and by Intel. There were several goals for the conference: to provide an opportunity for industry leaders as well as academicians to meet and discuss the latest developments in the world of metrology, to present these advances to audiences which would normally not be privy to such information, and to learn more about the international effort in 450mm wafer technology.
Over 200 people attended this conference from Israeli companies and academia, as well as from Europe and the United States. Israeli companies included Applied Materials, Jordan Valley, Nova, KLA, Zeiss Israel, and others. Academic members included researchers from the leading Israeli universities, including the Technion, Tel-Aviv U. and Haifa U. European companies were represented by ENIAC, as well as large corporations such as ASML as well SME-based companies. The G450C consortium, based in Albany, N.Y. was also well represented at this conference.
Some of the highlights of the conference included scientific discussions of different metrology methods, and their adjunct requirements, such as improved rapid wafer movement, improved sampling methods and fast computing. Presentations also included an overview of the advances necessary to move the industry forward, optical CD metrology, x-ray metrology, and novel piezo-based wafer movement.
A panel discussed various broad industry trends, including the timeline of 450mm wafers, European programs and the Israeli programs. International speakers discussed the European technology model, risk mitigation of 450 through collaborations, 450 collaborative projects under ENIAC, 450mm wafer movement challenges and metrology challenges beyond 14nm.
This second annual Metro450 conference took place this January at the Technion, Israel.
Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.
Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.
Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.
“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”
When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.
Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.
The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.
Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.
Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.
FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?
Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.
Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.