Cadence Design Systems recently introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers.
Rahul Deokar, product management director, said: “We are addressing designer challenges in – high performance design, giga-scale design and advanced node design. The first challenge is the PPA – power performance and area. Next challenge is to handle giga-scale designs with efficient turnaround time. The third key challenge is fast time-to-market on advanced 28nm/20nm design.”
With this latest release, Cadence provides the industry’s best PPA. Second, it is providing 1 billion gates on designer desktops. Third, it provides the fastest path to 20nm digital design. In the new announcement, there are three new technologies – GigaOpt + CCOpt, GigaFlex, and 20nm double patterning.
Cadence has introduced “GigaOpt” – a common optimization engine that unifies physical synthesis and optimization. GigaOpt provides designers globally optimal results across the front-end and back-end of the design flow. And that results in the benefit of the industry’s best PPA for high-performance design. GigaOpt has been designed from scratch to be multi-threaded, which makes it ultra fast and ultra scalable.
Another innovation, CCOpt, is the first and only technology in EDA to unify clock tree synthesis and physical optimization. CCOpt is now an integral part of the Encounter flow accelerating design closure with the best PPA. CCOpt facilitates:
* 10 percent improvement in design performance and total power.
* 30 percent reduction in clock power and area.
* 30 percent reduction in IR drop.
The Encounter flow now allows 1 billion gates to be enabled on the designer’s desktops. This is done with the new GigaFlex abstraction technology. It is the first and only technology in EDA that enables flexible, accurate abstraction adaptable to the flow stage. There is 10X capacity and TAT gains on 100 million+ instance designs. GigaFlex abstraction technology allows accurate, early physical modeling, concurrent top-and-block interface optimization, and concurrent hierarchical closure and late-stage ECO. Read more…
This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.
The latest Cowan LRA model parameter update incorporates 2011′s monthly sales results, thereby incorporating 28 years of historical, global actual monthly semiconductor sales as gathered, tracked and published by the WSTS.
Cowan has carried out the necessary mathematical computations in order to update the complete set of linear regression parameters embedded in the Cowan LRA forecast model. This update to the model’s parameters thus reflects 28 years (1984 to 2011) of historical global semiconductor sales numbers.
Therefore, the table given here has provided summarizes the latest model’s 2012 sales and sales growth expectations as a function of the model’s range (low, expected and high) for January 2012′s sales forecast estimates as put out by the updated model.
Note that the Cowan LRA Model’s expected 2012 sales growth (of 3.3 percent) relative to 2011 sales is slightly less bullish than the WSTS’s adjusted autumn 2011 sales growth forecast of 3.6 percent versus WSTS’s autumn 2011′s forecasted sales growth of 2.6 percent.
Symantec presented its latest Intelligence Report with the following highlights:
* Spam – 74.8 percent in September (a decrease of 1.1 percentage points since August 2011).
* Phishing – One in 447.9 emails identified as phishing (a decrease of 0.26 percentage points since August 2011).
* Malware – One in 188.7 emails in September contained malware (an increase of 0.04 percentage points since August 2011).
* Malicious Web sites – 3,474 Web sites blocked per day (an increase of 1 percent since August 2011).
* 44.6 percent of all malicious domains blocked were new in September (an increase of 10.0 percentage points since August 2011).
* 14.5 percent of all Web-based malware blocked was new in September (a decrease of 2.9 percentage points since August 2011).
* Malicious emails masquerade as office printer messages.
* Spammers exploit WordPress vulnerability to promote pharmaceutical spam Web sites Fake Offers with Fake Trust Seals. (One hopes WordPress is aware of this and taking remedial action!)
The spam rate was 74.8 percent, as against last month’s 75.9 percent. The top five geographies are Saudi Arabia 84 percent, Russian Federation 79.9 percent, Malaysia 79.8 percent, Luxembourg 79.1 percent and Italy 78.6 percent. The top five verticals targeted are automotive 77.8 percent, education 77.2 percent, marketing/media 76.4 percent, non-profit 76.4 percent and manufacturing 76.2 percent.
As for spam sources, US leads with 47.5 percent of spam originating from there. India at 9.6 percent, UK at 8.1 percent, Brazil at 7.6 percent, Russian Federation at 6.7 percent, China at 5,4 percent, Germany at 4.3 percent, Vietnam at 3.8 percent, Japan at 3.8 percent and Canada at 3 percent, make up the top 10 countries.
As for virus, 72 of email-borne malware was associated with variants of generic polymorphic malware, including Bredolab, Sasfis, SpyEye and Zeus variants.
New malware and spyware sites are appearing per day. Around 44.6 percent of all malicious domains blocked were new in September; an increase of 10 percentage points compared with August. Also, 14.5 percent of all Web-based malware blocked was new in September; a decrease of 2.9 percentage points since August.
Next, 20.8 percent of the most frequently blocked malware last month was identified and blocked using generic detection.
August 2010′s ‘actual’ global semiconductor sales numbers are scheduled to be released by the WSTS, namely the August HBR (Historical Billings Report) on or about October 4.
In anticipation of the WSTS release Cowan has shared an analysis feature of the Cowan LRA Model for forecasting worldwide semiconductor sales; namely, the ability to provide a ‘look ahead’ scenario analysis for 2010′s global semiconductor sales forecast as a function of next month’s (in this case August’s) actual global semi sales estimate.
The specifics of the scenario analysis are presented in the following paragraphs and detailed in the scenario analysis matrix table provided here.
In order to demonstrate this capability, Cowan has selected a range in possible August 2010 sales; in this particular scenario analysis, a sales range from $23.95 billion to $26.95 billion in increments of $0.5 billion was chosen as listed in the first column of the table.
This estimated range of actual sales is ‘centered around’ the actual August sales forecast estimate of $25.448 billion as determined by last month’s (July) run of the model. The corresponding August 3MMA sales forecast estimate that the model put forth is $25.723 billion.
The overall year 2010 sales forecast estimate for each assumed estimated August sales number over the selected range of August actual sales estimates is calculated by the model, and is shown in the second column of the table.
The third column reveals the resulting yr-o-yr sales growth estimates compared to year 2009′s actual sales (of $226.3 billion).
The fourth and fifth columns show the corresponding three Month Moving Average (3MMA) sales estimate and the associated year-on-year sales growth relative to August 2009′s 3MMA sales (of $19.381 billion), respectively.
Finally, the sixth column lists the associated Momentum Indicator (MI), which is defined and discussed below.
The MI is defined as the percent difference between the actual sales for a given month — in this case July 2010’s just published actual global sales of $24.568 billion and the forecasted sales estimate for July 2010, that is, $23.388 billion, which was calculated and published last month.
The MI can be either positive or negative and is a measure of the percent deviation of the actual monthly sales number from the previous month’s prediction derived by the model’s linear regression analysis of the past 26 years of historical, actual monthly global “sales experience” as gathered and published, each month, by the WSTS.
Note: August 2010’s sales forecast estimate is projected to be $25.448 billion. Read more…
I’ve just returned from Mentor Graphics’ EDA Tech Forum 2010, titled: Delivering the latest in 10X design improvements. The opening keynote by Pravin Madhani, GM, Place and Route Division, Mentor, could have been better — well, Dr. Walden C. Rhines, chairman and CEO, Mentor, had also delivered a similar lecture at this year’s VLSID 2010 conference.
However, the other two keynotes — by Dr. Kota Murali, lead scientist & program manager of nanotech, IBM India, and Manjunath Hebbar, VP & Head – Strategic Services, HCL Technologies Ltd, lived up to their billing.
The photomask industry is between the proverbial hard rock and the hard place. For instance, at 32nm, the mask cost works out to be $2 million today. In his keynote, Madhani said that the manufacturing industry would surely figure out a way to control mask costs.
Even fab costs are pretty high today — estimated at $50 billion in 2010, that is ~10 percent of the annual market. The global fab industry continues to figure out how to decrease costs. While design costs are projected to grow logarithmically, cost per function will continue to decline long after Moore’s Law is obsolete.
So, will we have any use for so many transistors? Down the years, growth in unit volumes has always distinguished the semiconductor industry. The semicon industry has been growing at 13 percent (10-year CAGR), while transistors have grown at 49 percent. These sit very well, as compared to say, computers – 9.3 percent, steel — 5.3 percent, and automobiles — 0.1 percent. The 49 percent transistor growth drives the semicon industry.
Madhani said that the note/netbook market seems to have several years of growth ahead. The Apple iPad has also created a new segment. Cell phone adoption has been in high-growth mode in the emerging markets. Smartphones are changing the video dynamics.
So, will applications require 10K more transistors by 2018? And, do we have the necessary design tools? Well, there will likely be a ~10K increase in transistors over the next eight years, going up to 40 billion transistors by 2018. Therefore, the industry will require tools ready now in order to design for 2018.
Four principal areas will require 10X improvements in design methodologies — system level design, verification, embedded software development, and back-end physical design and test. A 10X increase in the number of transistors will also require 1000X increase in verification.
In summary, reduction in costs per functionality will continue on a predictable learning curve long after Moore’s law is obsolete. The industry will also witness ~10X increase in transistors over the next eight years, leading up to 40 billion transistors by 2018.
Here are the latest forecast results for 2010 global semicon sales estimates associated with the forecasting model — the Cowan LRA model for predicting worldwide semicon sales.
The table provided below summarizes the latest updated global semiconductor sales forecast estimates derived from the Cowan LRA Model and is based upon the just published (by the WSTS) February 2010 actual sales results.
The updated sales forecast estimate for 2010 (of $298.88 billion) shows a large drop from last month’s forecast estimate (of $316.20 billion).
This corresponds to a decrease in the year-over-year sales growth estimate of 7.6 percentage points, namely from 39.7 percent to 32.1 percent.
It should be noted — the latest WSTS actual monthly sales numbers for Feb. reveal a (strong) downward revision to last month’s Jan sales (down $0.530 billion) as summarized here.
The Cowan LRA Model, however, “turns” this lagging monthly sales number into a “leading indicator” by virtue of its near-term forecasting capability looking out over the next five quarters.
This is the “beauty” of the model and, therefore, makes it dynamic in the sense that it can be run each month utilizing the most recent actual global S/C sales number published by the WSTS. Thus it allows “rigorous tracking” of the near-term sales forecast outlook for the global semiconductor industry on an “almost” real-time basis.
Consequently, the model’s monthly sales forecasts do not “sit still” but “evolve” with each month’s latest sales number. Since conditions change rapidly and unexpectedly in the semiconductor industry, market forecasters are hard pressed to keep up with these changes.
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.
There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.
Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).
Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.
In addressing power/performance challenges, 20SoC is said to be the quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC process is the first 32Gbps transceivers that are operating in 20nm silicon.
Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate
surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.
Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.
Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.
PMC-Sierra Inc. has launched the PM5440 DIGI 120G, said to be the industry’s only single-chip OTN processor supporting 10G, 40G and 100G speeds for OTN transport.
Elaborating, Kevin So, senior product line manager, PMC, said: “PMC is the first to integrate support for 12x10G, 3x40G or 1x100G in a single piece of silicon to address OTN transport (point-to-point), OTN aggregation (multiplexing) and OTN switching deployments. For example, with DIGI 120G, an OEM can design a line card on a P-OTP that supports 12x10G supporting per port configurable multi-service like OC-192/STM-64, 10GE, OTU2 or Fiber Channel.”
Using the same chip and same software investment, they can also design a 3x40G card supporting 40GE, OC-768/STM-256 or OTU3. Another card can be designed to support 100GE or OTU4. An OEM can design 10+ cards across multiple platforms leveraging a single R&D investment using DIGI 120G. This also translates into the lowest cost of ownership for the OEMs, while achieving a time to market advantage.
How does OTN allow for flexible aggregation and switching from 1G to 100G? For that matter, what can this device do?
OTN is a defined as a carrier grade protocol to transparently carry and switch and aggregate multi-service traffic including 1GE all the way to 100GE over a WDM. The protocol is an ITU-T standard, and supports ODU0 (which is 1G) to ODU4 (which is 100G). In addition, OTN defines something called ODUflex, which is a flexible container that can be adjusted up and down from 1G to 100G in increments of 1G.
PMC’s DIGI 120G supports all these OTN container rates and enable the ability to multiplex and switch traffic between them. In addition, DIGI 120G provides the ability to scale ODUflex to carry packet traffic ranging from 1G to 100G without service interruption. DIGI 120G is a single chip solution that uniquely enables the transponders, muxponders and line cards on ROADMs and P-OTPs.
What are the innovations done by the PM5440 DIGI 120G? What if there is some new chip coming out?
Reducing line card power and bill-of-material by more than 50 percent, PMC’s DIGI 120G stands uniquely differentiated as:
* Industry’s only single-chip solution delivering 12x10G, 3x40G or 1x100G port densities.
* Industry’s highest number of 10G ports enabling 2x higher density 10G OTN line cards.
* Industry’s highest gain 40G/100G enhanced-FEC extending optical reach by 2x vs GFEC.
* Industry’s only 120G OTN solution with OIF’s OTN-over-Packet Fabric Protocol (OFP).
* First OTN processor to enable hitless packet traffic scaling with ITU-T’s G.hao/G.7044.
* Flexible per port client-mapping of OTN, Ethernet, Storage, IP/MPLS and SONET/SDH.
* Synchronous Ethernet (SyncE), 1588v2 Precision Time Protocol (PTP), and Ethernet Link OAM (802.3ah) delivering per port Carrier Ethernet performance.
To deliver these innovations, PMC integrated well over a billion transistors. The level of silicon integration is unprecedented – requiring engineering capabilities unmatched in the telecom industry. So added that PMC worked closely with tier-1 OEM customers from the start at the requirements phase in order to tailor the solution for their systems. As a result, the DIGI 120G is a key architectural element of their system.
By when does PMC sees enterprises ‘really’ going in for products with PM5440 DIGI 120G, to support Big Data? And, what happens if they still don’t?
So noted: “We have been working with our customers for the last few months developing their line cards using DIGI 120G. We are confident they will take their products using DIGI 120G to production in 2013.”
Does PMC actually see a reconfigurable optical add-drop multiplexer (ROADM) revolution?
According to So, a couple of things are happening in the ROADM market. On the photonics side, products are now available to allow service providers to deploy very flexible wavelength switches that are color independent, direction independent, wavelength contention-free and support flexible ITU grid widths.
On the platform architecture side, we are seeing a move away from traditional muxponders and transponders line card architectures where the client ports are fixed to a specific optical uplink port (wavelength). Instead, OEMs want to de-couple the client ports from the uplink optical capacity for great flexibility and in order to achieve better bandwidth utilization especially as the industry starts deploying 100G wavelengths.
Services in the network, especially those from the metro network edge is still largely 1G or 10G rates. To achieve this flexibility, central fabrics are added to the ROADM platform to support OTN switching. PMC’s Metro OTN processor family, including our latest DIGI 120G, enable OEMs to build line cards that can switch OTN and packet simultaneously in these platform architectures.
Finaly, is the bandwidth of common modulation format for 100G and beyond too broad for ROADMs?
Kevin So concluded: “OTN, as a protocol, is designed to scale to beyond 100G. The standard bodies are already working on this now. ROADMs, as a hardware platform will scale, but new components and technologies will likely be needed to take them beyond 100G.”
This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.
According to the WSTS’s Jan 2013 HBR (posted on March 8th, 2013), January 2013’s actual global semiconductor sales came in at $22.824 billion. This actual sales result for January is 2.9 percent higher than January’s sales forecast estimate, namely $22.180 billion.
Plugging January’s actual sales number into the Cowan LRA forecasting model yields, the following quarterly, half-year, and full year sales and sales growth forecast expectations for 2013 compared to 2012 sales depicted in the table.
It should be highlighted that with last month’s publishing of the final 2012 sales result by the WSTS, the Cowan LRA Model for forecasting global semiconductor sales was updated to incorporate the full complement of 2012′s monthly sales numbers, thereby capturing 29 years of historical, global semiconductor (actual) sales numbers as gathered, tracked and published each month by the World Semiconductor Trade Statistics (WSTS) on its website.
As described last month, the necessary mathematical computations required in order to update the complete set of linear regression parameters embedded in the Cowan LRA forecasting model for determining future sales were carried out. The newly derived set of linear regression parameters therefore reflect 29 years (1984 to 2012) of historical global semiconductor sales as the basis for predicting future quarterly and full year sales and sale growth forecast expectations by running the Cowan LRA Model.
Therefore, the table given above summarizes the model’s latest, updated 2013 sales and sales growth expectations reflecting the WSTS’s January 2013′s actual sales as calculated by the model’s newly minted set of linear regression parameters.
Note that the latest Cowan LRA Model’s expected 2013 sales growth of 6.6 percent relative to 2012 final sales ($291.562 billion) is more bullish than the WSTS’s adjusted Autumn 2012 sales growth forecast of 3.9 percent as well as the WSTS’s Autumn 2012′s original forecasted sales growth of 4.5 percent which was released back in November of last year.
In addition to forecasting 2013’s quarterly sales estimates the Cowan LRA Model also provides an forecast expectation for February 2013’s sales, namely $22.436 billion. This sales forecast yields a 3MMA forecast for February of $23.571 billion assuming the no or minimal sales revision is made to January’s actual sales.
Finally, the table provided below details the monthly evolution for 2013’s sales and sales growth forecast predictions as put forth by the Cowan LRA forecasting model dating back to September of last year.
Note that the most recent 2013 sales growth forecast is up compared to the previous two forecasts of 5.5 percent and 3.6 percent, respectively.
It should be mentioned that the previous 2013’s sales growth forecast for Dec 2012, namely 3.6 percent, was based upon a sales forecast estimate for Jan 2013 versus the latest sales growth forecast estimate of 6.6 percent, which utilizes Jan’s actual sales result just released in the WSTS’s January 2013 HBR, Historical Billings Report.