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Higher levels of abstraction growth area for EDA

September 1, 2013 2 comments

Dr. Ajoy Bose

Dr. Ajoy Bose

San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.

I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”

There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.

Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.

How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.

“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”

How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.

On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.

Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth.  Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry.  At a macro level, the consumer sector will drive a lot of the growth ahead.  For EDA, the higher levels of abstraction is where the growth will be.”

Is global semicon inventory level headed for oversupply in Q3?


Early this month, iSuppli had indicated that semiconductor inventory levels may have headed into oversupply territory in Q3.

It said: “Semiconductor Days Of Inventory (DOI) for chip suppliers are estimated to have climbed to 75.9 days in the third quarter of 2010, up 1.5 days from Q2. DOI in Q3 also was 4.8 percent higher than the seasonally adjusted average for the period.”

iSuppli added that the value of inventory was not been this high since the second quarter of 2008, when semiconductor suppliers’ stockpiles peaked at $35.4 billion.

Thanks to Jon Cassell and Debra Jaramilla at iSuppli, I was able to speak with Sharon Stiefel, analyst for semiconductor inventory and manufacturing for iSuppli on this situation.

Is there really an oversupply?

Sharon Stiefel, iSuppli.

Sharon Stiefel, iSuppli.

I asked Sharon Stiefel that given the growth that 2010 has seen so far, why are semiconductor inventory levels heading into oversupply territory in Q3?

She said that semiconductor inventories, overall, have risen both in terms of DOI and dollars for the past several quarters, and not yet achieved pre-recession levels last seen in 2008. “The overly lean conditions of 2009 and early 2010 are giving way to inventory levels, which are more appropriate for the strong growth experienced in 2010.

“Oversupply in Q3 2010 is not a foregone conclusion, but is possible that if the companies are not able to match manufacturing run rates with demand as the year winds to a close,” she added.

Which sectors have been witnessing or recording some softness in demand and why?

Stiefel said: “Companies reporting Q3 revenues over the past two weeks have reported a softening in demand, particularly in PC and consumer end markets, attributed to the continued uncertainty in the global economy, leaving consumers unwilling to spend.  A company with more exposure to these sectors has more potential of excessive inventories, versus a company with a more balanced product portfolio.”

Industry needs to moderate inventories
It is also said in iSuppli’s release that: ‘The industry will need to moderate inventories at the appropriate time in its growth curve in order to capture current revenue opportunities while they still exist.’ So, when exactly is that appropriate time?

Stiefel noted: “The appropriate time is when sales opportunities exist – projected quarters of growth, rather than revenue contraction. Semiconductor revenues are projected to grow in Q3 2010, contract in Q4 2010 and Q1 2011, and then resume moderate single digit growth for the remainder of 2011.” Read more…

Cadence: Plan verification to avoid mistakes!


Apurva Kalia

Apurva Kalia

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there’s verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

Global semicon industry trends in 2014: Analog Devices


Sam Fuller

Sam Fuller

I recently met Sam Fuller, CTO, Analog Devices, and had an interesting conversation. First, I asked him about the state of the global semicon industry in 2013.

Industry in 2013
He said: “Due to the uncertainties in the global economy in the last couple of years, the state of the global semiconductor industry has been quite modest growth. Because of the modest growth, there has been a buildup in demand. As the global economies begin to be more robust going forward, we expect to see more growth.”

Industry in 2014?
How does Analog Devices see the industry going forward in 2014? What are the five key trends?

He added: “I would talk about the trends more from an eco-system and applications perspective. Increased capability on a single chip: Given all the advances to Moore’s law, the capability of a chip has increased considerably in all dimensions and not just performance, be it the horsepower we see in today’s smartphones or the miniaturization and power consumption of wearable gadgets that were on show this year at CES.

“In Analog Devices’ case, as we are focused on high performance signal processing, we can put more of the entire signal chain on a single die. For our customers, the challenge is to provide their customers a more capable product which means a more complex product, but with a simpler interface.

“A classic example is our AD9361 chip, which is a single chip wideband radio transceiver for Software Defined Radio (SDR). It is a very capable ASSP (Application Specific Standard Products) as well as RF front end with a wide operating frequency of 70 MHz to 6 GHz.

“This chip, coupled with an all-purpose FPGA, can build a very flexible SDR operating across different radio protocols, wide frequency range and bandwidth requirements all controlled via software configuration. It finds a number of applications in wireless communication infrastructure, small cell Base stations as well as a whole range of custom radios in the industrial and aerospace businesses.”

Now, let’s see the trends for 2014!

More collaboration with customers: There is a greater emphasis on understanding customers’ end applications to provide a complete signal chain, all in a System on a Chip (SoC) or a System in a package (SiP). The relationship with our customers is changing as we move more towards ASSPs focused with few lead customers for target markets and target applications. While this has already been ongoing in the consumer industry with PCs and laptops, customers in other vertical markets like healthcare, automotive and industrial are and will collaborate more with semiconductor companies like Analog Devices to innovate at a solutions level.

More complete products: We have evolved from delivering just the silicon at a component level to delivering more complete products with more advanced packaging for various 3D chips or multi-die within a package. Our solutions now have typically much more software that makes it easier to configure or program the chips. It is a solution that is a combination of more advanced silicon, advanced packaging and more appropriate software.

With providing the complete solution, the products are more application specific and hence, the need for more collaboration with customers. For example, there may be one focused on Software Defined Radio, one for motor control, and one for vital signs monitoring for consumer health that we have launched recently.

We need it to be generic enough that multiple customers can use it, but it needs to be as tailored as possible to the customers’ needs for specific market segments. While because of the volume and standardization, availability of complete reference designs in the consumer world has been the norm, other market segments are demanding more complete products not-withstanding the huge variation in protocols and applications.

Truly global industry: The semiconductor and electronics industry has become truly global, so multiple design sites around the globe collaborate to create products. For example for Analog Devices, one of our premier design sites is our Bangalore product design center where we quite literally developed our most complex and capable chips. At the same time our customers are also global.

We see large multinational companies like GE, Honeywell, Cisco, Juniper, ABB, Schneider and many of our top strategic customers globally doing substantial system design work in Bangalore along with a multitude of India design houses. Our fastest growing region is in Asia, but we have substantial engagement with customers in North America and Europe. And our competition is also global, which means that the industry is ever moving faster as the competition is global.

Smarter design tools: The final trend worth talking about is the need for smarter design tools.  As our products and our customers’ products become more complex and capable, there have to be rapidly developing design tools, for us to design them.

This cannot be done by brute force but by designing smarter and better tools. There is a lot of innovation that goes on in developing better tool suites. There is also ever more capable software that caters to a market moving from 100s of transistors to literally billions of transistors for an application.

3D remains central theme for Applied in 2014!


Om Nalamasu

Om Nalamasu

Following a host of forecasts for 2014, it is now the turn of Applied Materials with its forecast for the year. First, I asked Om Nalamasu, senior VP, CTO, Applied Materials regarding the outlook for the global semicon industry in 2014.

Semicon outlook 2014
He said that Gartner expects the semiconductor industry to grow in mid-single digits to over $330 billion in 2014.

“In our industry – the semiconductor wafer fab equipment sector – we are at the beginning of major technology transitions, driven by FinFET and 3D NAND, and based a wide range of analyst projections, wafer fab equipment investment is expected to be up 10-20 percent in 2014. We expect to see a year-over-year increase in foundry, NAND, and DRAM investment, with logic and other spending flat to down.”

Five trends for 2014
Next, what are the top five trends likely to rule the industry in 2014?

Nalamasu said that the key trends continuing to drive technology in 2014 and beyond include 3D transistors, 3D NAND, and 3D packaging. 3D remains a central theme. In logic, foundries will ramp to 20nm production and begin early transition stages to3D finFET transistors.

With respect to 3D NAND, some products will be commercially available, but most memory manufacturers plan to crossover from planar NAND to vertical NAND starting this year. In wafer level packaging, critical mechanical and electrical characterization work is bringing the manufacturability of 3D-integrated stacked chips closer to reality.

These device architecture inflections require significant advances in precision materials engineering. This spans such critical steps as precision film deposition, precision materials removal, materials modification and interface engineering. Smaller features and atomic-level thin films also make interface engineering and process integration more critical than ever.

Driving technology innovations are mobility applications which need high performance, low power semiconductors. Smartphones, smart watches, tablets and wearable gadgets continue to propel industry growth. Our customers are engaged in a fierce battle for mobility leadership as they race to be the first to market with new products that improve the performance, battery-life, form-factor and user experience of mobile devices.

How is the global semiconductor industry managing the move to the sub 20nm era?

He said that extensive R&D work is underway to move the industry into the sub-20nm realm. For the 1x nodes, more complex architectures and structures as well as new higher performance materials will be required.

Some specific areas where changes and technology innovations are needed include new hard mask and channel materials, selective material deposition and removal, patterning, inspection, and advanced interface engineering. For the memory space, different memory architectures like MRAM are being explored.

FinFETs in 20nm!
By the way, have FinFETs gone to 20nm? Are those looking for power reduction now benefiting?

FinFET transistors are in production in the most advanced 2x designs by a leading IDM, while the foundries are in limited R&D production. In addition to the disruptive 3D architecture, finFET transistors in corporate new materials such as high-k metal gate (HKMG) that help to drastically reduce power leakage.

Based on public statements, HKMG FinFET designs are expected to deliver more than a 20 percent improvement in speed and a 30 percent reduction in power consumption compared to28nm devices. These are significant advantages for mobile applications.

Status of 3D ICs
Finally, what’s the status with 3D ICs? How is Applied helping with true 3D stacking integration?

Nalamasu replied that vertically stacked 3D ICs are expected to enter into production first for niche applications. This is due primarily to the higher cost associated with building 3D wafer-level-packaged (WLP) devices. While such applications are limited today, Applied Materials expects greater utilization and demand to grow in the future.

Applied is an industry leader in WLP, having spear-headed the industry’s development of through silicon via (TSV) technology. Applied offers a suite of systems that enable customers to implement a variety of packaging techniques, from bumping to redistribution layer (RDL) to TSV. Because of work in this area, Applied is strongly positioned to support customers as they begin to adopt this technology.

To manufacture a robust integrated 3D stack, several fundamental innovations are needed. These include improving defect density and developing new materials such as low warpage laminates and less hygroscopic dielectrics.

Another essential requirement is supporting finer copper line/spacing. Important considerations here are maintaining good adhesion while watching out for corrosion. Finally, for creating the necessary smaller vias, the industry needs high quality laser etching to replace mechanical drilling techniques.

India’s evolving importance to future of fabless: Dr. Wally Rhines

February 3, 2014 2 comments

Dr. Wally RhinesIf I correctly remember, sometime in Oct. 2008, S. Janakiraman, then chairman of the India Semiconductor Association, had proclaimed that despite not having fabs, the ‘fabless India” had been shining brightly! Later, in August 2011, I had written an article on whether India was keen on going the fabless way! Today, at the IESA Vision Summit in Bangalore, Dr, Wally Rhines repeated nearly the same lines!

While the number of new fabless startups has declined substantially in the West during the past decade, they are growing in India, said Dr. Walden C. Rhines, chairman and CEO, during his presentation “Next Steps for the Indian Semiconductor Industry” at the ongoing IESA Vision Summit 2014.

India has key capabilities to stimulate growth of semiconductor companies, which include design services companies, design engineering expertise and innovation, returning entrepreneurs, and educational system. Direct interaction with equipment/systems companies will complete the product development process.

Off the top 50 semicon companies in 2012, 13 are fabless and four are foundries. The global fabless IC market is likely to grow 29 percent in 2013. The fabless IC revenue also continues to grow, reaching about $78.1 billion in 2013.  The fabless revenue is highly concentrated with the top 10 companies likely to account for 64 percent revenue in 2013. As of 2012, the GSA estimates that there aere 1,011 fabless companies.

The semiconductor IP (SIP) market has also been growing and is likely to reach $4,774 million by 2020, growing at a CAGR of 10 percent. The top 10 SIP companies account for 87 percent of the global revenue. Tape-outs at advanced nodes have been growing. However, there are still large large opportunities in older technologies.

IoT will transform industry
It is expected that the Internet of Things (IoT) will transform the semiconductor industry. It is said that in the next 10 years, as many as 100 billion objects could be tied together to form a “central nervous system” for the planet and support highly intelligent web-based systems. As of 2013, 1 trillion devices are connected to the network.

Product differentiation alone makes switching analog/mixed-signal suppliers difficult. Change in strategy toward differentiation gradually raises GPM percentage.

India’s evolving importance to future of fabless
Now, India ranks among the top five semiconductor design locations worldwide. US leads with 507, China with 472, Taiwan with 256, Israel with 150, and India with 120. Some prominent Indian companies are Ineda, Saankhya Labs, Orca Systems and Signal Chip (all fabless) and DXCorr and SilabTech (all SIP).

India is already a leading source of SIP, accounting for 5.3 percent, globally, after USA 43 percent and China 17.3 percent, respectively. It now seems that India has been evolving from design services to fabless powerhouse. India has built a foundation for a fabless future. It now has worldwide leadership with the most influential design teams in the world.

Presently, there are 1,031 MNC R&D centers in India. Next, 18 of the top 20 US semiconductor companies have design centers in India. And, 20 European corporations set up engineering R&D centers in India last year. India also has the richest pool of creative engineering resources and educational institutions in the world. The experience level of Indian engineers has been increasing, but it is still a young and creative workforce. There is also a growing pool of angel investors in India, and also in the West, with strong connections to India.

So, what are the key ingredients to generate a thriving infrastructure? It is involvement and expertise with end equipment. Superb product definition requires the elimination of functional barriers. He gave some examples of foreign “flagged” Indian companies that produced early successes. When users and tool developers work in close proximity, “out-of-the-Box” architectural innovations revolutionize design verification.

Round-up 2013: Best of semiconductors, electronics and solar


Virtex UltraScale device.

Virtex UltraScale device.

Friends, here’s a review of 2013! There have been the usual hits and misses, globally, while in India, the electronics and semiconductor industries really need to do a lot more! Enjoy, and here’s wishing everyone a Very Happy and Prosperous 2014! Be safe and stay safe!!

DEC. 2013
What does it take to create Silicon Valley!

How’s global semicon industry performing in sub-20nm era?

Xilinx announces 20nm All Programmable UltraSCALE portfolio

Dr. Wally Rhines: Watch out for 14/16nm technologies in 2014!

Outlook 2014: Xilinx bets big on 28nm

NOV. 2013
Indian electronics scenario still dull: Leaptech

Connecting intelligence today for connected world: ARM

India poses huge opportunity for DLP: TI

SEMICON Europa 2013: Where does Europe stand in 450mm path?

OCT. 2013
Apple’s done it again, wth iPad Air!

IEF 2013: New markets and opportunities in sub-20nm era!

SEPT. 2013
ST intros STM32F4 series high-performance Cortex-M4 MCUs

Great, India’s having fabs! But, is the tech choice right?

G450C

G450C

Now, India to have two semicon fabs!

Higher levels of abstraction growth area for EDA

AUG. 2013
Moore’s Law could come to an end within next decade: POET

What’s happening with 450mm: G450C update and status

300mm is the new 200mm!

JULY 2013
Xilinx tapes-out first UltraScale ASIC-class programmable architecture

JUNE 2013
EC’s goal: Reach 20 percent share in chip manufacturing by 2020!
Read more…

How’s global semicon industry performing in sub-20nm era?


Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.

Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.

Jaswinder Ahuja

Jaswinder Ahuja

Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.

“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”

When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.

Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.

The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.

Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.

Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.

FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?

Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.

Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.
Read more…

Xilinx announces 20nm All Programmable UltraSCALE portfolio


Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.

Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.

“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”

Virtex UltraScale device.

Virtex UltraScale device.

Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.

* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.

* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.

KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.

There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.

Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”

The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.

There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite.
UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.

Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.

Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.

“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”

The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.

UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.

Connecting intelligence today for connected world: ARM


ARMARM calls the spirit of innovation as collective intelligence at every level. It is within devices, between people, through tech and across the world. We are still pushing boundaries of mobile devices.

Speaking at the ARM Summit in Bangalore, Dr Mark Brass, corporate VP, Operations, ARM, said that the first challenge was the number of people on the planet. Technology development and innovation also pose challenges.

According to him, mobile phones are forecast to grow 7.3 percent in 2013 driven by 1 billion smartphones. Mobile data will ramp up 12 times between now and 2018. Mobile and connectivity are creating further innovation.

August, a compamy, has introduced an electronic lock for doors, controlled by the smartphone. Another one is Proteus, which looks at healthcare. The smartphone is becoming the center of our world. All sorts of sensors are also getting into smartphones. Next, mobile and connectivity are growing in automobiles. Companies like TomTom are competing with automobile companies. Connectivity is also transforming infrastructure and data centers. They are now building off the mobile experience.

As per ARM, an IoT survey done has revealed that 76 percent of companies are dealing with IoT. As more things own information, there will be much more data. The IoT runs on ARM.

“There’s more going on than just what you think. IoT is not just about things. Skills development should not be an afterthought. Co-operation is critical. Solutions will emerge. All sorts of things are going to happen. Three years from now, only 4 percent of companies won’t have IoT in the business at all,” Dr. Brass added.

IoT will be present in industrial, especially motors, transportation, energy, and healthcare. Smart meters are coming in to help with energy management. There is a move to Big Data from Little Data.

Challenges in 2020 would be in transportation, energy, healthcare and education. ARM and the ARM partnership is addressing those. “We are delivering an unmatched diversity of solutions. We are scaling from sensors to servers, connecting our world,” Dr. Brass concluded.

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