San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.
I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”
There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.
Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.
How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.
“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”
How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.
On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.
Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth. Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry. At a macro level, the consumer sector will drive a lot of the growth ahead. For EDA, the higher levels of abstraction is where the growth will be.”
Early this month, iSuppli had indicated that semiconductor inventory levels may have headed into oversupply territory in Q3.
It said: “Semiconductor Days Of Inventory (DOI) for chip suppliers are estimated to have climbed to 75.9 days in the third quarter of 2010, up 1.5 days from Q2. DOI in Q3 also was 4.8 percent higher than the seasonally adjusted average for the period.”
iSuppli added that the value of inventory was not been this high since the second quarter of 2008, when semiconductor suppliers’ stockpiles peaked at $35.4 billion.
Thanks to Jon Cassell and Debra Jaramilla at iSuppli, I was able to speak with Sharon Stiefel, analyst for semiconductor inventory and manufacturing for iSuppli on this situation.
Is there really an oversupply?
I asked Sharon Stiefel that given the growth that 2010 has seen so far, why are semiconductor inventory levels heading into oversupply territory in Q3?
She said that semiconductor inventories, overall, have risen both in terms of DOI and dollars for the past several quarters, and not yet achieved pre-recession levels last seen in 2008. “The overly lean conditions of 2009 and early 2010 are giving way to inventory levels, which are more appropriate for the strong growth experienced in 2010.
“Oversupply in Q3 2010 is not a foregone conclusion, but is possible that if the companies are not able to match manufacturing run rates with demand as the year winds to a close,” she added.
Which sectors have been witnessing or recording some softness in demand and why?
Stiefel said: “Companies reporting Q3 revenues over the past two weeks have reported a softening in demand, particularly in PC and consumer end markets, attributed to the continued uncertainty in the global economy, leaving consumers unwilling to spend. A company with more exposure to these sectors has more potential of excessive inventories, versus a company with a more balanced product portfolio.”
Industry needs to moderate inventories
It is also said in iSuppli’s release that: ‘The industry will need to moderate inventories at the appropriate time in its growth curve in order to capture current revenue opportunities while they still exist.’ So, when exactly is that appropriate time?
Stiefel noted: “The appropriate time is when sales opportunities exist – projected quarters of growth, rather than revenue contraction. Semiconductor revenues are projected to grow in Q3 2010, contract in Q4 2010 and Q1 2011, and then resume moderate single digit growth for the remainder of 2011.” Read more…
ARM calls the spirit of innovation as collective intelligence at every level. It is within devices, between people, through tech and across the world. We are still pushing boundaries of mobile devices.
Speaking at the ARM Summit in Bangalore, Dr Mark Brass, corporate VP, Operations, ARM, said that the first challenge was the number of people on the planet. Technology development and innovation also pose challenges.
According to him, mobile phones are forecast to grow 7.3 percent in 2013 driven by 1 billion smartphones. Mobile data will ramp up 12 times between now and 2018. Mobile and connectivity are creating further innovation.
August, a compamy, has introduced an electronic lock for doors, controlled by the smartphone. Another one is Proteus, which looks at healthcare. The smartphone is becoming the center of our world. All sorts of sensors are also getting into smartphones. Next, mobile and connectivity are growing in automobiles. Companies like TomTom are competing with automobile companies. Connectivity is also transforming infrastructure and data centers. They are now building off the mobile experience.
As per ARM, an IoT survey done has revealed that 76 percent of companies are dealing with IoT. As more things own information, there will be much more data. The IoT runs on ARM.
“There’s more going on than just what you think. IoT is not just about things. Skills development should not be an afterthought. Co-operation is critical. Solutions will emerge. All sorts of things are going to happen. Three years from now, only 4 percent of companies won’t have IoT in the business at all,” Dr. Brass added.
IoT will be present in industrial, especially motors, transportation, energy, and healthcare. Smart meters are coming in to help with energy management. There is a move to Big Data from Little Data.
Challenges in 2020 would be in transportation, energy, healthcare and education. ARM and the ARM partnership is addressing those. “We are delivering an unmatched diversity of solutions. We are scaling from sensors to servers, connecting our world,” Dr. Brass concluded.
SEMICON Europa was recently held in Dresden, Germany on Oct. 8-10, 2013. I am extremely grateful to Malcolm Penn, chairman and CEO, Future Horizons for sharing this information with me.
SEMICON Europa included a supplier exhibition where quite a few 450mm wafers were on display. One highlight was a working 450mm FOUP load/unload mechanism, albeit from a Japanese manufacturer. These exhibits did illustrate though that 450mm is for real and no longer a paper exercise. There was also a day-long conference dedicated to 450mm in the largest room. This was crowded throughout the time and a large number of papers were given.
Paul Farrar of G450C began with a presentation about Supply Chain Collaboration for 450mm. His key message was there are 25 different tools delivered to G450C of which 15 are installed in the NFN cleanroom. This number will grow to 42 onsite and 19 offsite by Q1 2015.
He stated that Nikon aims to have a working 193i litho machine in 2H 2014 and install one in Albany in 1H 2015. Farrar also reported a great improvement in wafer quality which now exceed the expected M76 specification, and prime wafers to the M1 spec should be available in Q3 2014. There has also been good progress on wafer reclaim and it is hoped some wafers can be reused up to 10 times, although at least three is the target.
Metrology seems to be one of the most advanced areas with eight different machines already operational. The number of 450mm wafers in their inventory now stands at over 10,000 with these moving between the partners more rapidly. It was immediately noticeable from Farrar’s speech that G450C is now recognising the major contribution Europe is making to 450mm and is looking for more collaborations.
Facilities part of F450C
Peter Csatary of M&W then dealt with the facilities part of G450C, known as F450C. This group consists of:
• M&W (co-ordination)
• Mega Fluid Systems
• Haws Corp.
• Air Liquide
• Ceres Technlogies
• CS Clean Systems
F450C is seen as streamlining communications with the semiconductor companies and their process tool suppliers. The group will focus on four key areas, namely Environmental Footprint, Facility Interface Requirements, Cost and Duration, and Safety and Sustainability.
One interesting point raised was that 450mm equipment is inherently more massive and one suggestion has been that ceiling mounted cranes will be required to install and remove equipment. This of course means that fab roofs would need to be stronger than previously. This topic was discussed at the latest F450C meeting subsequent to this conference.
Another new concept is that of a few standardised 3D templates and adapter plates to allow fab services to be pre-installed before the equipment is placed. An interesting point made elsewhere by M&W is that the current preference is to place a fab where there are already other fabs in existence so that the infrastructure to transport products, materials and services is already in place, as are basic utilities such as power, natural gas and water supply.
However, the scale of the expected utility demand at 450 mm ups the stakes as for example a large 300 mm facility uses about 4 million gallons of water per day, whereas a 450 mm fab will use almost double that, putting immense strain on a location’s infrastructure should there be other fabs in the region. This could affect future site selections.
An outcome of this phenomenon is that the reduction, reclaim and re-use of materials will no longer be driven only by the desire to be a good corporate citizen, but will also be driven by cost control and to ensure availability of required resources such as power, water, specialty gases and chemicals.
Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.
The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.
I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.
I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.
The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.
To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.
To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.
This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.
Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.
This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.
What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.
It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.
Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.
New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Don’t want to miss deadlines? Feel challenged about resources to deliver on critical business issues/initiatives? Well, are you desirous of responding much, much faster to customer requirements? Welcome to the converged infrastructure (CI)!
Is the future of IT enterprises resting on a converged infrastructure? Perhaps, yes! The CI comes with pre-integrated storage, networking, and virtualization — all as a single platform. That would surely increase the efficiency, agility and resiliency of any organization.
So, what exactly does the CI involve? Well, it will integrate all your servers, networking and storage into a single solution. This would improve the utilization of these collective resources effectively and efficiently. There will be tremendous simplification and centralization of management of resources. Further, it can bring down your IT expenditure by at least 30-40 percent, if not more! Enterprises can even have their RoIs within one or two years of implementation.
Having a CI in an enterprise involves having a strategic approach that touches every part of IT, such as applications, infrastructure and management, leading to:
* Accelerated IT service deployment.
* Efficiency across the IT services lifecycle.
* Strengthened IT service quality.
Dell’s PowerEdge VRTX shared infrastructure platform aims to do exactly all of the above, thereby the redefine office IT! There are integrated servers, storage and networking in a compact chassis optimized for office environments.
Dell’s PowerEdge VRTX provides a shared infrastructure platform, scalable performance, flexible shared storage, simple and versatile systems management, integrated networking and flexible I/O, and seamless management integration. CIOs definitely do not need to worry about loud servers, cabling nightmares, etc.
Dell’s PowerEdge VRTX is meant not only for SMBs, but also for large companies in retail, banking, healthcare, education, financial, etc. For example, a large company may have a huge data center somewhere that manage various stores. However, at each individual store/location, there’s no central IT management or administration. Hence, this acts like an IT administrator-in-a-box by giving the IT administrator the ability to manage across any store/location across the world using just from one box.
The PowerEdge VRTX is really a shared infrastructure platform, offering extensive performance and capacity with office-level acoustics in a single, compact tower chassis. It is ideal for small and midsize businesses, as well as remote and branch offices of large enterprises.
There is no compromise on scalable performance. Dell VRTX can help businesses gain fast application response times, run multiple applications that need performance or low latency, power through peak processing periods and scale for future business growth. There is flexible shared storage. All four server nodes have access to the low-latency internal shared storage that is ideal for virtualization and clustering. Local storage is also available in the chassis, which is highly economical and easier to manage than traditional SAN.
The PowerEdge VRTX offers integrated networking and flexible I/O. It includes a GbE embedded switch that eliminates the need to purchase a separate networking device and PCIe resources that are shared across the compute nodes within the chassis.
It also allows simple, efficient and versatile systems management. Full-functioned unified system management with Chassis Management Controller (CMC) and GeoView helps take much of the time and effort out of system administration and control. Deploy, monitor, update and maintain through a unified console that covers servers, storage and networking. Dell’s VRTX systems management is also integrated with major third-party management tools, protecting the CIOs installed investments and allowing them to use what they know.
This is a paid post in conjunction with IDG and Dell.
The European Commission is said to have a goal: to reach 20 percent world-share in chip manufacturing by 2020! Heinz Kundert, president, SEMI Europe, has even laid out an industrial strategy that will cover three complementary lines, such as:
* Transition to 450mm, expected to primarily benefit equipment and material manufacturers in Europe.
* “More than Moore” on 200mm and 300 mm.
* “More Moore” for ultimate miniaturization on 300mm wafers.
Investment will be focusing on Europe’s clusters of excellence in manufacturing and design — Grenoble, Dresden and Eindhoven-Leuven — and support partnerships and alliances across the value chain in Europe.
The key question of why Europe needs 450mm wafers has been answered by Mike Bryant of Future Horizons. The European semiconductor industry’s vision is to recover a leading position in the world throughout the entire value chain and to reverse the current negative trend of its worldwide competitiveness.
Among the many strategies the EC is planning to adopt include:
* Benefit from a single explicit European semiconductor industry policy.
* Maintain a high level of R&D effort, in a balanced way between the 150/200/300/450mm fields, between “More Moore” and “More than Moore”.
* Strengthen all elements of the value chain, from design to application.
* Develop co-operating programs and synergy initiatives between all semiconductor actors operating in Europe.
Europe has always stressed on stronger co-operation among the other industry segments. Some of these are automotive, energy, healthcare and well-being, security and safety, etc.
Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?
Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”
Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?
According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.
He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.
“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”
Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?
“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”
What will be the impact of transistor variability and other physics issues?
As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.
The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.
At Cadence, the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.
What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.
On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.