Global forecast estimates based on WSTS’s May semicon sales: Cowan LRA model

This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.

The WSTS posted May 2011′s HBR, Historical Billings Report, on its website on Tuesday, July 5th, 2011.

According to the WSTS’s HBR, May’s actual sales came in at $23.494 billion with the corresponding May 3MMA sales at $25.031 billion. It should be noted that two months experienced slight downward sales revisions from last month’s published HBR, namely March (down by $0.147 billion) and April (down by $0.112 billion), respectively.

The Cowan LRA model’s sales forecast estimates for May as published last month were $24.565 billion (actual) and $25.474 billion (3MMA), respectively. Thus, the model’s May MI (Momentum Indicator) came in at minus 4.4 percent.

This indicates (mathematically speaking) that the semiconductor industry’s actual May sales result was much lower than the model’s expectation by $1.071 billion and that, most probably, 2011′s sales growth will be trending downward for the rest of this year.

Plugging the latest actual sales number for May into the model yields the following updated sales and sales growths forecast estimates for 2011:

Global semicon sales monthly update based on Cowan's LRA model.

The key take-aways from comparing the latest versus previous month’s forecast results are highlighted below:
* 2011′s sales forecast estimate fell by $3.937 billion to $318.391 billion (from last month’s sales forecast estimate of $322.328 billion).
* Correspondingly, 2011′s sales growth forecast estimate dropped by 1.3 percentage points to 6.7 percent (from last month’s 8 percent sales growth forecast estimate).
* June 2011′s actual sales forecast expectation is $29.435 billion which corresponds to a June 3MMA sales estimate of $25.445 billion assuming no (or minor) sales revisions for either April or May’s previously published actual sales from last month.

Next month’s forecast update based upon June’s actual sales are expected to be available on or about Friday, Aug 5th, 2011.

“Look ahead” to May 2011′s predicted yearly global semicon sales: Cowan LRA model

This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.

May 2011′s “actual” global semiconductor sales is scheduled to be released by the WSTS, via its monthly HBR (Historical Billings Report), on or about Tuesday, July 5th.

In anticipatation of the upcoming May sales release by the WSTS, Cowan demonstrated an analysis capability of the Cowan LRA Model for forecasting worldwide semicon sales; namely, the ability to provide a “look ahead” scenario analysis for 2011′s global semicon sales forecast range as a function of next month’s (in this case May’s) “actual” global semiconductor sales estimate.

The detailed results of the “look ahead” analysis are summarized in the scenario analysis matrix provided in the table below. These results are also discussed in the subsequent paragraphs:

2011 May global semicon sales and sales growth scenario matrix: Cowan LRA model.

In order to demonstrate this “look ahead” forecast capability, an extended range in possible May 2011′s “actual” sales is selected a-priori; in this particular scenario analysis, a May 2011 sales range (from $23.065 billion to $26.065 billion, in increments of $0.25 billion, was chosen) as listed in the first column of the above table.

This estimated range in possible “actual” May sales numbers is “centered around” the projected May sales forecast estimate of $24.565 billion as gleamed from last month’s Cowan LRA Model run (based upon April’s published “actual” sales numbers). The corresponding May 3MMA sales forecast estimate is projected to be $25.474 billion (NOTE – assumes no, or minor. revisions in either March’s or April’s previously published “actual” sales numbers released last month by the WSTS) .

The overall year 2011 sales forecast estimate for each of the assumed May sales over the pre-selected range of ‘actual’ sales estimates is calculated by the model, and is shown in the second column of the table. The third column reveals the associated year-on-year sales growth estimates compared to year 2010′s actual sales result of $298.315 billion.

The fourth and fifth columns show the corresponding May 3MMA, three Month Moving Average, sales estimates and the corresponding yr-o-yr sales growths relative to May 2010′s 3MMA sales of $24.701 billion, respectively. Finally, the sixth column lists the model’s Momentum Indicator, MI, defined as the percentage delta between the actual May sales result and the previous month’s sales projection for May.

May 2010 global semicon update: Four quarters of sequential growth, yet still no one believes! Wake up, says Future Horizons

Here are the excerpts from the Global Semiconductor Monthly Report, May 2010, provided by Malcolm Penn, chairman, founder and CEO of Future Horizons. There are a lot of charts associated with this report. The report also covers market trends. Those interested to know more may contact Future Horizons.

March’s total semiconductor sales came in at $26,533 billion, slightly above our February expectation, closing the quarter at $69,181 billion. This was up 2.8 percent over Q4-2009 and one of the strongest first quarter performances ever in what is normally a negative growth quarter. We have now had four straight quarters of industry growth, yet still no one believes in the strength of the recovery!

Of course, something unexpected can always go wrong but the industry fundamentals have never been better aligned. Just as 2001 ushered in the conditions for the so-called the perfect (semiconductor) storm, 2010 is now wallowing in the inverse effect. Surprisingly, few firms are tough. Most are too timid, too cautious or too scared. Welcome to the brave new world of semiconductor company ambivalence and life-threatening risk aversion. “Hello”.

Future Horizons presented its review and forecast for the global semiconductor market on the first day of their ongoing 19th International Electronics Forum (IEF) 2010 in Dresden, Germany, May 6-8. Our overall prediction was that the 2010 chip market would have a barnstorming year; only a disaster of the Lehmann Brothers scale could now derail the market.

The overall five-year forecast presented was:

* 2010: +31 percent, with still some scope for upwards revision.

* 2011: +28 percent; based on: peak of the structural cyclical boom (could stretch into 2012).

* 2012: +18 percent; based on: normal cyclical trash cycle starting 2H-2012 (1H-2013?).

* 2013: +3 percent based on: market correction in full flow (could be negative, cap ex overspend and inventory build depending).

* 2014: +12 percent; based on: start of the next cyclical recovery (single digit, if 2013 is negative).

This would take the industry to around $300 billion in 2010 with a CAGR of 11.8 percent between 2010-14. It would also signal a 180-degree reversal in the industry’s fortunes following its ‘zero growth’ 2000-09 lost decade of growth. Moreover, despite the apparent bullishness of these numbers, given the now unavoidable 2010-11 fab shortage, the growth upside for 2010-12 is still huge.

The real tragedy however of what ought to have been good news for the industry was: (a) still, no one believes in the numbers; and (b) it was entirely predictable.

We first presented this forecast in January 2009, at the high point of the industry’s economic and business uncertainty. The only change we have made in the last 17 months was to increased 2010’s growth number from 15 to 31 percent number. Whilst all other industry analysts, business leaders, trade associations and economists alike wrestled with what was happening, we alone never lost faith in the industry or what the underlying fundamentals were saying.

This cycle’s forecast was the easiest we have ever had to make. All we had to do for the IEF meeting was to adjust for the fact that the 2009 recovery was faster and steeper than even we had dared to predict. The bottom line? The industry fundamentals may often get distorted by events but they never lie, ignore them at your peril.

We were ridiculed for our optimism in January 2009 and throughout the year when we stuck to our guns. We never stopped believing in the numbers however and never subscribe to industry fashion, trend or sentiment, despite this sometime being out on a limb with industry consensus.

We are proud of the fact only we got this analysis right but equally sad that no one had the courage to listen. This was not forecast luck either; this was simply doing what we do best, making a considered analysis and then believing in what the forecast tells us.

March’s data validated forecast; Q1 WAS cyclical bottom! Semicon update May’09

Here are the excerpts from the Global Semiconductor Monthly Report, May 2009, provided by Malcolm Penn, chairman, founder and CEO of Future Horizons. There are a lot of charts associated with this report. Those interested to know more about this report should contact Future Horizons.

This will be followed by the update for June, and I am speaking with Malcolm Penn to find out more!

Executive overview
“At $14.085 billion, March’s IC sales were up 28.4 percent versus February, equivalent to plus 2.7 percent on a five-week month adjusted basis. Whilst this still puts the market down 31.2 percent versus March 2008, the momentum that started in January 2009 continues to steadily gain traction.

Overall, the ICs in Q1 were down just 13.4 percent in value, comprising a 19.6 percent fall in units offset by a whopping 7.8 percent gain in ASPs. At the total semiconductor level, sales came in at $17.271 billion, up 27.1 percent on February (1.7 percent on a 5-week month adjusted basis), slightly higher than our $17.019 billion April Report estimate.

Q1 was thus down only 15.7 percent on Q4, sizeably better than our 18.5 percent estimate. This is good news for industry… ‘ah but’ say the sceptics!

During our January 2009 International Forecast Seminar, we took the view that, from an economic recovery perspective, things would stabilise during the first half of the year, starting to gain traction by the end of 2009, given the dramatic economic stimuli since September 2008. The recovery would then accelerate quite fast in 2010-11, i.e. following a similar pattern as to what happened after the 2000 dot-com crash. There is every reason to believe this will still be the case.

Until recently, the big industry problem was uncertainty but there have been no horrible surprises now for several weeks and things do seem like we are bumping along the bottom. The global economy has stabilised; there have been no new gut-wrenching surprises and the ‘unknown unknowns’ in the economy have subsided. This means we are now left facing the ‘known unknowns’, which is clearly something that industry can adjust to and deal with.

Despite its severity, there are also many mitigating circumstances. At the personal level, this recession is quite like no other. For those without a job, or on short-time working, it is clearly bad news as no one is currently hiring. But, those with a job ironically have never been better off, with inflation, mortgage interest rates and repayments (the single biggest expense item on the personal expense budget) at rock bottom levels. This is very unlike the past recessions, which were accompanied by high inflation and cripplingly high interest rates.

Another factor is that no one really knows how much of the current GDP shrinkage (and for that matter the previous five-years above average growth) is (was) smoke and mirrors. With CDIs valued at 1.2x total world GDP in 2007 only to be written down to junk bond status the following year, the absolute GDP and growth rate numbers have been compromised. That makes it hard to judge what they mean from a top down perspective, more so when one considers the total electronics manufacturing industry’s contribution to world GDP is barely 3 percent.

Finally, even though cars, mobiles, PCs etc may fall in unit terms by ’15-30 percent’ this year, that still means ’70-85 percent of the market’ remains. With inventory levels everywhere in the value chain at all-time lows, we are currently back now building to demand from newly bought components, albeit some 20 percent lower than the 2008 highs.

At the chip level, the market is obviously driven by the economy but it also has its own drivers, especially capacity and ASP trends. Thus, whilst the existence of a link between the chip market and the economy is clear, mathematically the nature of this link is imprecise. Dislocations in growth dynamics are thus relatively frequent.

What then of our January 2009 quarterly growth pattern (Q1 -18 percent, Q2 -2 percent, Q3 +12 percentand Q4 +3 percent)? Clearly Q1, at -15.7 percent, was better than forecast which, if the rest of the growth pattern continues as planned, would rein in the full year market decline slightly from -28 to -25.3 percent, but still within the forecast margin of error. Q1 has thus reinforced, not altered, our January prognostications.

If Q1′s stronger momentum however carries through into Q2, Q2 would come in much stronger than our 2 percent decline, say to plus 2 percent instead. This would positively change our forecast dynamics with a further two percentage points improvement on the full year’s number, improving our forecast from -28 percent to -23.2 percent. Whilst we are not yet prepared to call for a formal forecast revision, the odds are in its favour and the downside forecast risks dispersed.

Clearly Q1 was the cyclical bottom; from here on out the growth trends will be up. Once the inventory purge is over, excess capacity will soon be absorbed with a corresponding strong recovery in utilisation rates. Given capex is currently at an 18-month all time low, with no near-term correction in prospect until late Q3-Q4 at the earliest, the industry will enter 2010 staring into a new net capacity famine.

We definitely will be revising our 2010 forecast up, from the current +15 percent to the mid-to high twenties.

Industry capacity
The table C1 shows the quarterly semiconductor equipment sales trends for the period Q1-2008 through Q1-2009 inclusive. The total Q1-2009 equipment sales were $3,235 million, down 31.4 percent from Q4-2008, which in turn was down 28.1 percent from Q3-2008. This represents the biggest sequential falls in the history of the chip industry.Source: Future Horizons

Wafer processing equipment represented 76 percent of the total, just slightly higher than its 75 percent average. Total Q1-2009 investment represented only 7.3 percent of the quarterly semiconductor sales, although it must be remembered that an equipment sale in Q1-2009 will not produce incremental semiconductor sales until three quarters later, namely Q4-2009.

Q1-2009 wafer fab equipment sales were down a staggering 69.4 percent on Q1-2008, the fourth consecutive quarterly high double-digit drop, with further declines in the prospect. Capex levels are now running at levels not seen since the early 1990s when the overall chip market was one-third its current size.

As mentioned earlier, Q1-2009 was down 31.4 percent versus Q4-2008, on top of the three previous quarterly declines of 28.1 (Q4 vs Q3), 16.3 (Q3 vs Q2) and 25.8 (Q2 vs Q1) percent respectively. It should not be forgotten that these cutbacks were not triggered by the current chip market recession; the first two quarterly drops, namely Q2 and Q3-2008, took place against a backdrop of strong IC unit growth, i.e., well before the Q4-2008 chip market collapsed.

The cutbacks were a clear intent to engineer tight capacity, a strategy that would by now have bitten home were it not for the cruel interruption on the Q4-2008 market collapse. We have never before seen such an extensive cut back prior to a collapse; ironically this will help the recovery process, albeit for the wrong reasons. It will also underpin the underlying strategy — post recession IC capacity is going to be tighter than tight.

We also tracked the total semiconductor equipment sales by month since January 1988, both in absolute value and as a percent of semiconductor sales. One significant feature that can be seen from these trends is that the absolute value of the total semiconductor equipment sales has been significantly lower than the previous 1999-2000 investment peak, despite the fact the total semiconductor market has expanded in size.

During this same time period, the investment trend relative to the size of the total semiconductor market has also been trending well below its long-term 16.75 percent average, despite this being a period of heavy 300mm conversion.

The corresponding data for the Wafer Processing equipment sector, shows an increasing trend as a percent of semiconductor sales. This trend, however, is not a sign of excess investment, rather that the wafer processing portion is gaining overall market share, currently at around 75 percent of the total equipment spend, up from around 60 percent in the late 1980s.

We also tracked the total capex spent as a percent of semiconductor revenues on an annual basis since 1990-2008, and data but for the total semiconductor equipment spend. We also tracked the relative relationship between the wafer processing and total semiconductor spends.

These show that a higher proportion of revenues are being spent on the wafer processing sector, a trend that we believe is likely to continue.

We believe that the current levels of capex expenditure are unprecedentedly low and cannot be wholly accounted for improvements in productivity and factory loading. Even if they are, these gains are one-off improvements; once they have been realised there is no more gain in prospect and expenditure levels will return to ‘normal’ trends.

We tracked the wafer processing equipment spend versus the corresponding increase in capacity on a quarterly basis since Q1-1999 but with the capacity increase delayed by three quarters.

Once the three-quarter slippage in introduced into the equation, the overlay of the two curves, whilst not perfect, is a very good fit. In short, it takes three quarters for increases in wafer processing spend to translate into new capacity. This is the time it takes to hook up and calibrate the kit and make it volume production ready. Add to this an additional one-quarter delay through wafer fab and assembly process, the net result is a one year delay from wafer processing spend to incrementally more IC shipments out.

Adding in a further one-quarter lead-time for equipment delivery, results in a typically 15 month delay for an existing clean room structure from wafer processing investment decision to increased unit sales, one year longer still if a new building is required.

These long lead-times, however, have a positive side in that one has excellent visibility three quarters out into how much additional capacity is due to come on stream, just by analysing the front-end capex spend numbers. Once the frontend
capex is committed, the addition capacity is inevitable, needed or not, the difference being determined by the capacity utilisation number.

One is thus making an investment decision based on a unit demand forecast 12 months down the road, which would not be so problematic were demand more predictable.

As can be seen, however, from the unit sales charts in the Market Summary section of this report, IC unit demand fluctuates violently from its underlying long-term ten percent per year annual growth rate on a month-by-month basis, quarter-by-quarter basis, not withstanding the inevitable — and unavoidable — routing inventory adjustments.

The biggest single problem with semiconductor capex is thus both the long time delay from investment decision and additional IC units out and the non-linearity of the month-by-month unit demand. It is this mismatch that gives rise to the investment uncertainty. Getting the investment timing right, however, is not an exact science; there are bound to be ongoing capacity mismatches within this overall favourable trend.

Entering 2009, the current new capacity investment is trending well below the long-term trend, and is projected to slow even more so in 2009 as the economic recession bites home. This means over-investment is not going to accentuate the current industry downturn, as has so often happened before.

This time it seems investment has been deliberately slowed in order to improve the return on capital employed. The seeds have also been sown for the next market shortage in 2010-11. Foundry wafer prices will rise; dust down the ‘makebuy’ Excel spreadsheets … the ‘fablite’/IDM debate dynamics has yet to run its course.”

Wherever you may roam!

I recall editing an article of this name during my days at DiSyCom, way back in late 1994. Those were the early days of cellular/mobile telephony in India. At a seminar on mobility at the Taj Palace in New Delhi in early 1995, I had the first-hand experience to learn what roaming was all about, thanks to a nice gentleman from the ITU.

Today, 13 years down the road, roaming is hardly the subject to discuss. People take it for granted that if they are carrying a mobile phone, they MUST be roaming. Its also one of the safest bets for operators to make money.

I recall, in December 2002, in Hong Kong, some colleagues from India were unable to call home as they weren’t on roaming, and I had to lend them my phone to call. On the contrary, I was once stuck in Munich as I wasn’t on roaming and couldn’t call, and had to seek help from a ‘friend’ at the airport.

Of course, I’ve noticed in places across the Asia Pacific, such as Hong Kong, China, Taiwan and Singapore, that people buy local SIM cards in order to save on roaming costs. Even I’ve done the same on several occasions.

Today, we have come a long, long way as far as mobility is concerned. Soon, video roaming or the ability to make video calls, while roaming, would be upon us. I wonder how people would take to that experience! Also, it’d be interesting to see how the operators charge consumers on video calls and especially, video roaming.

Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines

Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?

Dr. Wally Rhines.

Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”

Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?

According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.

He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.

“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”

Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?

“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”

What will be the impact of transistor variability and other physics issues?

As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.

Critical success factors for MEMS commercialization

MEMS

MEMS still has a long way to go to meet the challenges of commercialization! Critical success factors include efficient process transfer from breadboard to production. There is a need to pay attention to customers’ needs. More resources need to be adopted from the semiconductor industry, said Roger Grace, president, Roger Grace Associates.

There is a need to create significant awareness as to the unique solution benefits of MEMS based systems and establish defensible product differentiation. Firms need to better understand customer/market needs.

Emerging opportunities include single MEMS based system solutions, especially in analytical instruments, double magnetic MEMS, triple point-of-care bio, energy harvesting/storage, etc. There are barriers to commercialization of MEMS. Until recently, it is plagued by lack of high-volume apps. There is lack of well-defined direction from roadmaps, industry standards and associations. Packaging and testing costs are typically at 70 percent of total value. There is also a lack of focus on customer needs and lack of capital formation opportunities, risk averse investors.

Besides, successive bubble busts, i.e., biomems, optical telecom, have seen wary investors. There are very fragmented markets, many small companies and few large players. Also, there are limited ‘success stories’ of MEMS/MST companies, eg., Invensense. There are new market opportunities for large volume apps, eg. in automotive, CE, etc.

Downturn hit research hard! R&D remains a novelty for most firms. Now, there is an increase in university and R&D labs for MEMS development. There is still plenty of R&D available from DARPA, SBIR and STTRs. Now, we are seeing a healthy amount of activity in new devices and systems research.

As for DfM (design for manufacturing), Invensense’s ‘shuttle’ process may finally become a usable standard. New approaches are also changing the paradigm of cost structure. Examples are Invensense gyros, Freescale chip-stacking accelerometers, ST, etc.

While there seems to be strong MEMS infrastructure, there is some fraying at the ends. The industry needs to remain competitive and lean. As for profitability, while the margins don’t seem great for high volume MEMS devices, they are holding on somewhat. The general consensus of the VC community has been that MEMS has lot of growth potential, but it doesn’t have a good track record of producing profitable firms, as yet.

The lack of DfM emphasis and the absence of a coherent package and test capability is the lack of management insight. As for standards, the creation of the first Standardized Sensor Performance Parameter Definitions is a huge step in the right direction.

Tensilica acquisition to broaden Cadence’s IP portfolio

Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash.

With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto infotainment and home applications.

The Tensilica IP also complements industry-standard processor architectures, providing application-optimized subsystems to increase differentiation and get to market faster. Finally, over 200 licensees, including system OEMs and seven of the top 10 semiconductor companies, have shipped over 2 billion Tensilica IP cores.

Pankaj Mayor

Talking about the rationale behind Cadence acquiring Tensilica, Pankaj Mayor, VP and head of Marketing, Cadence, said: “Tensilica fits and furthers our IP strategy – the combination of Tensilica’s DPU and Cadence IP portfolio will broaden our IP portfolio. Tensilica also brings significant engineering and management talent. The combination will allow us to deliver to our customers configurable, differentiated, and application-optimized subsystems that improve time to market.”

It is expected that the Cadence acquisition will also see the Tensilica dataplane IP to complement Cadence and Cosmic Circuits’ IP. Cadence had acquired Cosmic Circuits in February 2013.

What are the possible advantages of DPUs over DSPs? Does it mean a possible end of the road for DSPs?

As per Mayor, DSPs are special purpose processors targeted to address digital signaling. Tensilica’s DPUs are programmable and customizable for a specific function, providing optimal data throughput and processing speed; in other words, the DPUs from Tensilica provide a unique combination of customized processing, plus DSP. Tensilica’s DPUs can outperform traditional DSPs in power and performance.

So, what will happens to the MegaChips design center agreement with Tensilica? Does it still carry on? According to Mayor, right now, Cadence and Tensilica are operating as two independent companies and therefire, Cadence cannot comment until the closing of the acquisition, which is in 30-60 days.

What’s next in complex SoC verification?

Functional verification is critical in advanced SoC designs. Abey Thomas, verification competency manager, Embitel Technologies, said that over 70 percent effort in the SoC lifecycle is verification. Only one in three SoCs achieves first silicon success.

Thirty percent designs needed three or more re-spins. Three out of four designs are SoCs with one or more processors. Three out of four designs re-use existing IPs. Almost all of the embedded processor IPs have power controllability. Almost all of the SoCs have multiple asynchronous clock domains.

An average of 75 percent designs are less than 20 million gates. Significant increase in formal checking is approaching. Average number of tests performed has increased exponentially. Regression runs now span several days and weeks. Hardware emulation and FPGA prototyping is rising exponentially. There has been a significant increase in verification engineers involved. A lot of HVLs and methodologies are now available.

Verification challenges
Verification challenges include unexpected conflicts in accessing the shared resource. Complexities can arise due to an interaction between standalone systems. Next, there are arbitration priority related issues and access deadlocks, as well as exception handling priority conflicts. There are issues related to the hardware/software sequencing, and long loops and unoptimized code segments. The leakage power management and thermal management also pose problems.

There needs to be verification of performance and system power management. Multiple power regions are turned ON and OFF. Multiple clocks are also gated ON and OFF. Next, asynchronous clock domain crossing, and issues related to protocol compliance for standard interfaces. There are issues related to system stability and component reliability. Some other challenges include voltage level translators and isolation cells.

Where are we now? It is at clock gating, power gating with or without retention, multi-switching (multi-Vt) threshold transistors, multi-supply multi-voltage (MSMV), DVFS, logic optimization, thermal compensation, 2D-3D stacking, and fab process and substrate level bias control.

So, what’s needed? There must be be low power methods without impacting on performance. Careful design partitions are needed. The clock trees must be optimized. Crucial software operations need to be identified at early stages. Also, functional verification needs to be thorough.

Power hungry processes must be shortlisted. There needs to be compiler level optimization as well as hardware acceleration based optimization. There should be duplicate registers and branch prediction optimization. Finally, there should be big-little processor approach.

Present verification trends and methodologies include clock partitions, power partitions, isolation cells, level shifters and translators, serializers-deserializers, power controller, clock domain manager, and power information format – CPF or UPF. In low-power related verification, there is on power-down and on power-up. In the latter, the behavioral processes are re-enabled for evaluation.

Open source verification challenges
First, the EDA vendor decides what to support! Too many versions are released in short time frame. Object oriented concepts are used that are sometimes unfit for hardware. Modelling is sometimes done by an engineer who does not know the difference between a clock cycle and motor cycle! Next, there is too much of open source implementations without much documentation. There can be multiple, confusing implementation options as well. In some cases, no open source tools are available. There is limited tech support due to open source.

Power aware simulation steps perform register/latch recognition from RTL design. They perform identification of power elements and power control signals.They support UPF or CPF based simulation. Power reports are generated, which can be exported to a unique coverage database.

Common pitfalls include wrapper on wrapper bugs, eg. Verilog + e wrapper + SV. There is also a dependency on machine generated functional coverage goals. There may be a disconnect between the designer and verification language. There are meaningless coverage reports and defective reference models, as well as unclear and ambiguous specification definition. The proven IP can become buggy due to wrapper condition.

Tips and tricks
There needs to be some early planning tips. Certain steps need to be completed. There should be completion of code coverage targets, completion of functional coverage targets, completion of targeted checker coverage, completion of correlation between functional coverage and checker coverage list, and a complete review of all known bugs, etc.

Tips and tricks include bridging the gap between design language and verification language. There must be use of minimal wrappers to avoid wrapper level bugs. There should be a thorough review of the coverage goals. There should be better interaction between designer and verification engineers. Run using basic EDA tool versions and lower costs.

PC’s Electronic Components Blog named top resource for electrical engineers! ;)

Today, Feb. 14th, has turned out to be a great day for me! I received an email early morning, which stated: PC’s Electronic Components Blog is featured on the list of 100 Top Resources for Electrical Engineers that we published on ElectricalEngineeringSchools.org, USA!

Wow! This happens to be my sixth world title in a row!! The picture of the award badge is given alongside!!!

I am so very happy that my blog on electronic components has bagged an award! I had started my career writing about electronic components for Asian Sources Media, now Global Sources‌, in Hong Kong.

Back in those days – 1994-1995, there used to be some presence of electronic components made by local manufacturers, especially in Naraina Industrial Area, New Delhi. I still remember, very clearly, doing the rounds of Naraina, along with my friend, Dolly! Back then, most of the components were made for colour TV sets, and a few makers had just started making components for cellular phones.

Today, there are big-sized, very large representatives of electronic components in India.

I recall one of my earlier stories was on DIP switches. There used to be slide and rocker types of DIP switches. I wonder whether they are still used today! Maybe, they are, in some electronic devices! I also recall there used to be some demand for TV antennae at that time, as well as for cell phone antennae! How time has flown by since!!

May I take this opportunity and offer sincere thanks to all of my readers, well wishers, friends and acquaintances I have made over the years for their continuous love and support! Without you, no award is ever possible!

I’d like to conclude by taking the names of two gentlemen, who have spurred me on to write blogs on components, electronics and semiconductors, as well as telecom. They happen to be Alfred Cheng. country manager, Hong Kong, Global Sources, and Spenser Au, former publisher, CTG and now, CEO, Global Sources, Hong Kong, who made me work on the Telecom specs tables.

A word is also due for Raj Gopinath, my editor-in-chief at Asian Sources, and Daniel Tam, who replaced Spenser, back in 1999, as publisher of CTG. Special mention needs to be made of Claudius Chan, who I consider as a ‘guru’ of electronic components. Whatever I am today is largely due to my time spent at Global Sources! Thanks a lot, my dear friends!!

Alfred just sent me a mail saying: Hi Pradeep, How many more prizes would you like to win, my friend? I wish I could write as good as, maybe 50 percent as good as you do since we used to work together in the electronics industry. Thanks a lot, my friend!