Milpitas, USA-based Sonics Inc. participated in TSMC’s Soft IP Alliance 2.0 beta program. Driving high quality soft IP eases customer integration and expedites time-to-market.
Sonic’s role in TSMC beta program
Speaking on the beta program and Sonics’ role, Frank Ferro, director of Product Marketing, Sonics, said: “TSMC’s Soft IP kit 2.0 beta program is part of TSMC’s Open Innovation Platform program that creates a complete ecosystem for customers with the overall goal of shortening design time. This is done by providing a large catalog of partner provided IP that is silicon-verified and production-proven.
For vendors like Sonics, TSMC has extended this ecosystem to include Soft-IP (IP not designed for a specific process, but delivered as RTL). The program allows Soft-IP partners to access and leverage TSMC’s process technologies to optimize power, performance and area for their IP.
IP cores are checked through TSMC’s foundry checklist to ensure the customers have optimized design results with fast IP integration built into their design. This flow also facilitates easy IP reuse for subsequent designs. The soft IP Kit beta 2.0 program is an extension of the current program through implementing additional quality checks, improving results and making the flow easier for customers.
There are several advantages to Sonics as a participant in this program. First, customers of TSMC will have access to Sonics IP through TSMC’s IP library. Given TSMC’s strong market share, this will allow Sonics IP to be visible to a large customer base. In addition, TSMC’s customers will feel securing using Sonics IP because they know that it has been put through a rigorous series of IP checks that meet the highest quality standards. It also allows Sonics early access to TSMC’s process libraries, allowing Sonics to optimize performance and area for each IP product.
So, what can the TSMC’s Soft IP Kit 2.0 do? How does Sonics enhance its capabilities? The Soft IP Kit 2.0 provides a specific RTL design flow methodology and hand-off which includes: lint (RTL coding consistency), clock domain crossings (CDC), power (CPF/UPF), physical design (routing congestion), design for test (DFT), constraints and documentation.
Using this flow enhances Sonics IP quality and reliability because many RTL errors can be caught at an early stage. As mentioned above, this flow ensures lowest power and best performance of the IP for a given process node.
Atrenta SpyGlass improves packaging
There is a role played by Atrenta SpyGlass. According to Ferro, Atrenta SpyGlass is the tool used to run all the tests. The flow was developed to TSMC’s standards and implemented by Atrenta. Given Sonics strong relationship with TSMC and Atrenta, we were invited to be a beta partner using our IP to test the new flow. A number of companies do participate in the program, although only Sonics has announced participation in the beta 2.0 program to date.
This tie up with Atrenta will likely improve IP packaging. As part of the overall flow, the final step, after all basic and advanced IP checks, is IP packaging. This step includes providing the IP with information on the design intent, set-up and analysis reports. Again, this is done using the SpyGlass tool from Atrenta.
This IP packaging was available to customers in the past via the Soft IP 1.0 program. The attraction of this type of IP packaging is a result of the growing number of IP cores being integrated into complex SoCs. As the number of third party IP grew, the need for a better, broader methodology was developed.
NXP Semiconductors N.V. has announced the first NWP ISO 11898-6 and AUTOSAR R3.2.1 compliant solution supporting CAN Partial Networking.
The stand-alone TJA1145 CAN transceiver and integrated system basis chip UJA1168 – the world’s first highly integrated solution to support CAN Partial Networking – give design engineers precision control over a vehicle’s bus communication network. By intelligently de-activating electronic control units (ECUs) that are currently not needed, engineers can significantly reduce vehicle fuel consumption and CO2 emissions without sacrificing performance or consumer experience.
Reducing CO2, improving energy efficiency
So, how will the NXP solution reduce CO2 and improve energy efficiency in vehicles? Karsten Penno, business development manager, Business Unit Automotive, NXP, said: “In current CAN networks, all ECUs are always active and consuming power when the vehicle is in use. This is the case even if the applications they control aren’t continuously required, such as seat positioning, sun roof operation, park assistance systems, etc.
“CAN Partial Networking changes this model by activating only those ECUs that are functionally required, while other ECUs remain in a low-power mode until needed. This results in significant savings in power/fuel consumption, reducing costs, wiring and CO2 emissions. CAN Partial Networking is also extremely beneficial for electric and hybrid vehicles as it helps extending their operating range and optimizing charging time. Saving potential: 0.11l fuel savings/100km and 2.6g CO2 reduction/km.”
Why not before?
Now, if the CAN Partial Networking solution is so novel, why wasn’t it thought of before?
Penno said: “Innovations like CAN Partial Networking always require a broad industry acceptance and standardization. The CAN bus system – as key component of in-vehicles networks – has been around for many years (introduced in early ’90s). However, only with the rising awareness on CO2 emissions and overall vehicle efficiency – along with growing CAN node counts – came the need for a more efficient CAN standard. NXP is innovation leader in this area and is chairs the standardizing working group within ISO.” Read more…
Friends, here is part two of my discussion with Vincent Ratford, senior vice president, worldwide marketing and business development, Xilinx. This post will discuss FPGAs and Xilinx’s estimate of the global FPGA industry, as well as its university development program.
Estimate of global FPGA industry
Ratford said that in 2010, Xilinx sees tremendous growth opportunities for programmable platforms in electronics infrastructure applications, such as wired communications, 3G and LTE wireless deployment — all of which will require high performance DSP processing in excess of 1000 Giga operations per second and packet processing at a rate of more than 100 Gbps.
He added: “Green IT will need power efficient, high performance, compute architectures that will exploit the high level of parallel computing. The smart grid will rely on programmable, flexible appliances and metering. And finally surveillance and security will require sophisticated image processing algorithms. These compute-intensive applications are ideally suited to the performance and flexibility of today’s leading edge FPGAs.
“This trend bodes well for the PLD industry to outperform the overall semiconductor industry over the long term, as the technology ‘most responsive to change’ displaces costly, high-risk application-specific solutions for all but a narrow set of high-volume commodity markets.
Is there still a debate regarding FPGAs vs. ASICs?
As per Ratford, there is no debate! “From our perspective the market has spoken. FPGA design starts are on the rise, as ASIC design starts continue their steep decline. Today, ASICs can only be justified for a short list of ultra-high volume commodity products, such as video games (Nintendo Wii, Sony PlayStation and Microsoft Xbox360), hard drives for PCs, mobile/smartphones, etc.”
The ability to quickly create differentiated products — and the freedom to innovate — is why more and more companies in India and all over the world are choosing FPGAs. Due to their inherent flexibility, Xilinx silicon, software, IP, evaluation kits and reference designs are used by more than 20,000 customers to:
i) get to the market in a matter of weeks;
ii) drastically reduce research and development costs; and
iii) change or upgrade end product features and functions “on the fly” to meet new market demands and adapt to changing industry standards.
On intelligent mixed-signal devices
Early this month, at the Embedded World conference, Actel Corp. had unveiled SmartFusion, the world’s first intelligent mixed signal FPGA. I was keen to find out whether Xilinx has plans for similar devices, or rather, when is its intelligent mixed-signal FPGA planned.
Ratford agreed that introducing analog/mixed signal capabilities in FPGAs is a good idea. “We are looking at ways to provide that in the future, but it needs to be as part of our TDP (Targeted Design Platform) strategy including IP, software, reference designs.” Read more…
He added: “We have an ongoing and long-term commitment to working with the Indian semiconductor industry. We want to promote growth through partnerships with UK innovation and excellence. The UK and Indian semiconductor industries working together have enormous potential to create a powerful solution for customers in India, the UK and the rest of the world.”
The UK electronics industry is about £25 billion a year. It is made up of more than 11,500 companies employing about 250,000 people. UK is the acknowledged leader in independent systems design with over 40 percent market share.
Hyde presented some examples of UK’s innovative industry, such as CamSemi — a spinoff from Cambridge University, which provides power conversion solutions to make electronics industry ‘greener’; DisplayLink — a pioneer in connecting multiple screens to one PC through USB; and PicoChip — experts in wireless infrastructure and signal processing. Several of UK’s semiconductor companies also have strong presence in Bangalore, India, such as ARM, CSR and Wolfsen.
He said that the UK has a vibrant start-up community that supports strong industry clusters in the South West of England, Central Scotland and Cambridge. Experts from these regions are present at the ISA Vision Summit for discussions.
Hyde added that the UK’s consumer electronics market is the strongest in Europe. Sales of flat panel and LCD TVs hit £8.8 million in 2008. Despite the downturn, there has been further growth in 2009. Blue ray players and HD based technology have continued to grow, and that is important as this technology was developed in the UK. The UK also remains Europe’s largest ICT market with sales of £171 billion per annum with over £20 billion in equipment sales.
Hyde touched upon the SemiConclave workshop organized by the Science and Invvovation Network within the Deputy High Commission team and the ISA in October 2008. One of the outcomes of the event has been that the Bangalore based Center for Emerging Technologies at the Jain University is now working with the Scottish Microelectronics Center on a research project to fabricate MEMS devices.
He added that the ISA is helping UKTI drive its Global Value Chain program. “Our goal is now to encourage and develop more direct business to business interaction. A good example of this is the agreement signed in December between Lord Mandelson and Azim Premji of Wipro, which aims to promote UK/Indian joint work to develop new and innovative low carbon technologies.
“We are looking forward to the next stage of development of this important relationship, in particular, the promotion of the UK Core Initiative Group. We aim to have increasing representation from each other’s industries at each other’s events, including the ISA session on Innovation Ecosystems. And we want increasing number of companies working together and develop partnerships.”
He concluded that this indeed is an exciting area and an exciting time for the semiconductor industry. Delegates at ISA Vision Summit 2010 can look forward to meeting leading UK companies, such as the TTP Group, PowerOasis, Advanced Hall Sensors and the Scottish Microelectronics Center.
Friends, as promised, here is the second part of the discussion I had with Accenture’s Scott Grant, based on Accenture’s recent study: Managing Through Challenging Times!
4. Reducing the time to cash for new products.
When companies industrialize the market concept, and they procure design win opportunities, we tend to see critical components involved with this: a) maintaining relationships of requirements from market analysis through final manufacturing build plan; b) leaders who use consistent lifecycle management of a product development flow; and c) IP management with integrated roadmap portfolio capabilities.
“Firms at times are not able to convert concepts to cash quickly. The process to integrate them has several gaps including innovation lifecycles, conversion of R&D concepts to volume products, and ability to optimize the engineering capacity constraints within their P&Ls.”
Product lifecycle management, portfolio & market analytics, and engineer skills/human resource management help to address these gaps. Portfolio management and roadmap planning process are a must. When done, semiconductor companies will be able to map quickly with the customers and the market insights.
5. Sharpening customer focus through more in-depth and accurate customer insight.
Most firms won’t survive if they are unable to gain rapid adoption of their product offering. From our experience, high performing companies build detailed customer usage-models and insight into end-device markets early in their R&D process.
The challenge many find is that without this baseline of understanding it is difficult to convert concepts into cash once the end-product is delivered to the market.
Many of the insights are available from Point of Sale trends, which can help a semicon firm exist at either an OEM (PC, handset, etc.) or distributor. High performers have enhanced the relationship with their work collaborators and customers to gain access to this data. They also build a “Trusted Advisor” relationship where they build scenarios for each end market to better predict what their end-customer may desire in features or functions.
It is difficult for a semicon firm to know how a product will be used. It is really the beginning of gaining insight into utilization, the consumer, and what usage model should be employed. So a semicon firm should study carefully how things can be used in the market. User behavior is crucial. If companies don’t understand that, they may be missing out.
6. Pursuing alliances to share the cost burden of new product development.
The point here is to make sure that semiconductor companies are taking a strategic view and look at the right places to pursue alliances. There’s a lot of impact in pursuing alliances. When semicon companies do this, they can absolutely share the burdens, but it can impact the operating model.
Other recommendations for the industry
What are the other recommendations that Accenture have for the semiconductor industry going forward?
Grant recommends the industry to focus on achieving high performance business results. Those include sustained leadership in various financial metrics such as return to shareholders, profits, and revenue growth.
“Recognize and adapt to the reality that we are now living in a multi-polar world. This is a world in which a growing number of emerging countries and economies are becoming more financially powerful, competitive and relevant in competing against the traditionally more developed parts of the world such as North America, Asia and Europe. This means there are a multitude of growing business opportunities in these emerging nations for semiconductor companies to capitalize on.
“Proactively invest during a recession rather than pull back investments and just wait until the economy pulls out of this down cycle. History has shown that those companies that invest the most perform better in the years after the market recovers.”
Companies repeating mistakes?
Now, these recessions always have a bad habit of occuring cyclically! Therefore, why do semiconductor (and other) companies tend to repeat those same mistakes again and again?
According to Grant, one reason is they tend to indiscriminately and rapidly cut costs without thinking more strategically and carefully about what costs to cut. “They tend to lay off workers who they need when the market recovers, but they can’t hire them back because those employees have moved on with their careers. These semiconductor companies don’t think hard enough about what employees and assets they will need when the market recovers.”
Layoffs? What about design and development?
Finally, are layoffs the only solution to combat recession? What happens to design and development?
Grant agrees that layoffs are absolutely not the only solution to combat recession. Investing in core competencies is crucial, and spending less time and effort on non-core capabilities is important.
“Employee morale tends to fall within design and development during a recession because they see some of their colleagues lose their jobs and they take on more work. And they lose more control of what work they are assigned to do. And they’re less secure about their job security.
“But, much of this can be alleviated by giving employees a chance to share their ideas and concerns at regularly scheduled Town Hall meetings, to communicate with them regularly and candidly, and to focus them on achieving high performance business results.”
Connecting with new friends from all over the world is one of the best things that I have experienced while writing a semicon and electronics blog. One such gentleman is Ingo Guertler from Europartners Consultants. He is based in Munich, Germany — a city I have frequented several times.
Guertler has been part of my LinkedIn network as well. He has spent 30 years in leading positions in the electronic components market, mostly with semiconductors, at General Instrument, QT Optoelectronics and Vishay. Since 2005, he has been the senior partner at Europartners Consultants, a network of independent consultants, mostly located in Europe.
Beside individual projects, Europartners analyze the worldwide distribution market for electronic components each year and publish the results in its Worldwide Distribution Report.
Additionally, the company also organizes a two-day conference in Paris every two years, with high-level speakers out of the electronic component industry, discussing actual topics with top managers from component manufacturer and distributors.
This year, the headline will cover the world economy crisis, its effect on the electronics industry, and how companies can successful manage the crisis.
Naturally, our conversation revolved around the global semiconductor market, the memory market turmoil, and how European companies view the Indian semiconductor industry.
Semicon to decline 20 percent in 2009
Ingo Guertler expects a decrease in the global semiconductors market of approximately a minimum of 20 percent. Europartners does not see a recovery before the middle of 2010.
Guertler said: “Maybe, there can be a light recovery in the second quarter 2010 in some regions. Everything will depend on how fast the funds of the governments to the industry will draw. We have to specifically watch, the American and Chinese markets.”
Regarding the memory market, he added that everybody had expected that Vista will stimulate the markets. However, that did not happen. “For the time being, the industry has no direct killer application for memories available or in the design stage. I expect a further price erosion on memories, especially on DRAMs,” he cautioned.
Europe’s interest in Indian semicon
Again, it was natural for me to query Ingo on how European companies view the Indian semiconductor industry.
According to him, for the time being, collaboration between the European and Indian companies is limited in the most cases, or on a one-way service base, using the excellent skills and resources of the Indian software companies and engineers that also includes EDA. “I don’t think that will change in the near future,” he added.
Guertler said: “Personally, I see India as a new market challenge in the next 10 years or more for the European companies, because the local demand will grow faster in India, than we today see in China. Also, I believe and have seen it already, that a lot of companies will likely shift their production bases from China to India the next time, simply because of lower costs, availability of good, graduate engineers and a more Western orientated politics of the Indian government.”
However there is one handicap for the Indian continent! That is: the current infrastructure and the political situation between India and Pakistan.
According to Guertler, India has to set up huge investment programs to invite more investors in the country. Very importantly, is there any feeling that overseas companies’ interest in India is slowing down?
“Definitely not, as far as the European companies are concerned. If India meets the industry’s requirements, I believe their preference will be for India in comparison to China,” he said.
That indeed, is great to hear! The Indian interest is very much intact, in Europe and elsewhere. Now, it is time for India to get some work started on semiconductor product development companies.
Turning my attention to the programmable logic market, I took advantage of my recent meeting with Jordan Plofsky, Senior Vice President Market, Altera Corp., during the Altera SOPC conference.
Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.
Altera’s India strategy
In this context, it will be interesting to note Altera’s strategy within the Indian semiconductor industry.
Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.
He says: “Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here.”
Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. “We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology,” adds Plofsky.
Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.
Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!
According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.
Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.
In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.
Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry’s first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.
To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.
As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.
Adds Plofsky: “We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time.”