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ST intros STM32F4 series high-performance Cortex-M4 MCUs


STMicroelectronics has introduced the STM32F4 series STM32 F4x9 and STM32F401, which are high-performance Cortex-M4 microcontrollers (MCUs).

On the growth drivers for GP MCUs, the market growth is driven by faster migration to 32 bit platform. ST has been the first to bring the ARM Cortex based solution, and now targets leadership position on 32bit MCUs. An overview of the STM32 portfolio indicates high-performance MCUs with DSP and FPU up to 608 CoreMark and up to180 MHz/225 DMIPS.

Features of the STM32F4 product lines, specifically, the STM32F429/439, include 180 MHz, 1 to 2-MB Flash and 256-KB SRAM. The low end STM32F401 has features such as 84 MHz, 128-KB to 256-KB Flash and 64-KB SRAM.

The STM32F401 provides thebest balance in performance, power consumption, integration and cost. The STM32F429/439 is providing more resources, more performance and more features. There is close pin-to-pin and software compatibility within the STM32F4
series and STM32 platform.

The STM32 F429-F439 high-performance MCUs with DSP and FPU are:
• World’s highest performance Cortex-M MCU executing from Embedded Flash, Cortex-M4 core with FPU up to 180 MHz/225 DMIPS.
• High integration thanks to ST 90nm process (same platform as F2 serie): up to 2MB Flash/256kB SRAM.
• Advanced connectivity USB OTG, Ethernet, CAN, SDRAM interface, LCD TFT controller.
• Power efficiency, thanks to ST90nm process and voltage scaling.

In terms of providing more performance, the STM32F4 provides up to 180 MHz/225 DMIPS with ART Accelerator, up to 608 CoreMark result, and ARM Cortex-M4 with floating-point unit (FPU).

The STM32F427/429 highlights include:
• 180 MHz/225 DMIPS.
• Dual bank Flash (in both 1-MB and 2-MB), 256kB SRAM.
• SDRAM Interface (up to 32-bit).
• LCD-TFT controller supporting up to SVGA (800×600).
• Better graphic with ST Chrom-ART Accelerator:
— x2 more performance vs. CPU alone
— Offloads the CPU for graphical data generation
* Raw data copy
* Pixel format conversion
* Image blending (image mixing with some transparency).
• 100 μA typ. in Stop mode.

Some real-life examples of the STM32F4 include the smart watch, where it is the main application controller or sensor hub, the smartphone, tablets and monitors, where it is the sensor hub for MEMS and optical touch, and the industrial/home automation panel, where it is the main application controller. These can also be used in Wi-Fi modules for the Internet of Things (IoT), such as appliances, door cameras, home thermostats, etc.

These offer outstanding dynamic power consumption thanks to ST 90nm process, as well as low leakage current made possible by advanced design technics and architecture (voltage scaling). ST is making a large offering of evaluation boards and Discovery kits. The STM32F4 is also offering new firmware libraries. SEGGER and ST signed an agreement around the emWin graphical stack. The solution is called STemWin.

How semicon firms can achieve high performance — Part II


Friends, as promised, here is the second part of the discussion I had with Accenture’s Scott Grant, based on Accenture’s recent study: Managing Through Challenging Times!

4. Reducing the time to cash for new products.
When companies industrialize the market concept, and they procure design win opportunities, we tend to see critical components involved with this: a) maintaining relationships of requirements from market analysis through final manufacturing build plan; b) leaders who use consistent lifecycle management of a product development flow; and c) IP management with integrated roadmap portfolio capabilities.

“Firms at times are not able to convert concepts to cash quickly. The process to integrate them has several gaps including innovation lifecycles, conversion of R&D concepts to volume products, and ability to optimize the engineering capacity constraints within their P&Ls.”

Product lifecycle management, portfolio & market analytics, and engineer skills/human resource management help to address these gaps. Portfolio management and roadmap planning process are a must. When done, semiconductor companies will be able to map quickly with the customers and the market insights.

5. Sharpening customer focus through more in-depth and accurate customer insight.
Most firms won’t survive if they are unable to gain rapid adoption of their product offering. From our experience, high performing companies build detailed customer usage-models and insight into end-device markets early in their R&D process.

The challenge many find is that without this baseline of understanding it is difficult to convert concepts into cash once the end-product is delivered to the market.

Many of the insights are available from Point of Sale trends, which can help a semicon firm exist at either an OEM (PC, handset, etc.) or distributor. High performers have enhanced the relationship with their work collaborators and customers to gain access to this data. They also build a “Trusted Advisor” relationship where they build scenarios for each end market to better predict what their end-customer may desire in features or functions.

It is difficult for a semicon firm to know how a product will be used. It is really the beginning of gaining insight into utilization, the consumer, and what usage model should be employed. So a semicon firm should study carefully how things can be used in the market. User behavior is crucial. If companies don’t understand that, they may be missing out.

6. Pursuing alliances to share the cost burden of new product development.
The point here is to make sure that semiconductor companies are taking a strategic view and look at the right places to pursue alliances. There’s a lot of impact in pursuing alliances. When semicon companies do this, they can absolutely share the burdens, but it can impact the operating model.

Other recommendations for the industry
What are the other recommendations that Accenture have for the semiconductor industry going forward?

Grant recommends the industry to focus on achieving high performance business results. Those include sustained leadership in various financial metrics such as return to shareholders, profits, and revenue growth.

“Recognize and adapt to the reality that we are now living in a multi-polar world. This is a world in which a growing number of emerging countries and economies are becoming more financially powerful, competitive and relevant in competing against the traditionally more developed parts of the world such as North America, Asia and Europe. This means there are a multitude of growing business opportunities in these emerging nations for semiconductor companies to capitalize on.

“Proactively invest during a recession rather than pull back investments and just wait until the economy pulls out of this down cycle. History has shown that those companies that invest the most perform better in the years after the market recovers.”

Companies repeating mistakes?
Now, these recessions always have a bad habit of occuring cyclically! Therefore, why do semiconductor (and other) companies tend to repeat those same mistakes again and again?

According to Grant, one reason is they tend to indiscriminately and rapidly cut costs without thinking more strategically and carefully about what costs to cut. “They tend to lay off workers who they need when the market recovers, but they can’t hire them back because those employees have moved on with their careers. These semiconductor companies don’t think hard enough about what employees and assets they will need when the market recovers.”

Layoffs? What about design and development?
Finally, are layoffs the only solution to combat recession? What happens to design and development?

Grant agrees that layoffs are absolutely not the only solution to combat recession. Investing in core competencies is crucial, and spending less time and effort on non-core capabilities is important.

“Employee morale tends to fall within design and development during a recession because they see some of their colleagues lose their jobs and they take on more work. And they lose more control of what work they are assigned to do. And they’re less secure about their job security.

“But, much of this can be alleviated by giving employees a chance to share their ideas and concerns at regularly scheduled Town Hall meetings, to communicate with them regularly and candidly, and to focus them on achieving high performance business results.”

CONCLUDED

Categories: Accenture, Scott Grant

How semicon firms can achieve high performance by simplifying business!


Engineers in the global semiconductor industry have typically have had considerable control of their work. Processes are pretty straightforward, sequential, and logical — and satisfying for an honest day’s work.

However, due to the ongoing global economic downturn, many of these engineers are rapidly losing control of more of their professional lives. Caught like the rest of the world in a recession, they are losing more control of what work they are assigned to do, how they do it, in what sequence, by when and with whom.

Given these inter-related problems, many semiconductor companies need to make rapid and fundamental changes in their business operations, strategies and workforce management practices to emerge from this downturn, and for year beyond, as high performers.

Once this recession ends, these people will be entering a market with a different landscape than the market that existed when the downturn began. They need to figure out how to restart their businesses, regain their footing and connect to a new purpose.

They need to address the so-called ‘soft’ aspects of business, such as the engineers who design chips and how they feel. It’s time for them to pay more attention to the little things that may seem innocuous but are actually central to achieving high performance.

Thanks to Charlie Hartley, Accenture, US, I was able to get hold of Accenture’s recent study: Managing Through Challenging Times!! Quite an interesting read!

Naturally, it led to a conversation with Scott Grant, Executive Global Lead of Accenture’s Semiconductor Operating Unit (see image here), who led the research and analysis of this new Accenture report released now about these issues and recommended solutions.

Accenture’s report has seven suggestions or recommendations.

1. Divesting the business of unproductive assets.
2. Infusing a higher degree of operational excellence into the business.
3. Maintaining morale and energy in the workforce, especially in the key area of innovation.
4. Reducing the time to cash for new products.
5. Sharpening customer focus through more in-depth and accurate customer insight.
6. Pursuing alliances to share the cost burden of new product development.
7. Acquiring key assets.

Let’s take a look at those, one by one!

1. Divesting the business of unproductive assets.
From Accenture’s perspective, it has become evident during the past few years that among the top 20 semiconductor a growing number are fabless. That trend will continue in the future mainly because fabless companies have more competitive cost structures than semiconductor manufacturing companies that incur such high fixed-asset costs for their operations. Accenture’s clients (customers) are seeking to understand the business operating model that best fits their desired position in the market. Our assessment leads to having a leaner product portfolio.

The first thing we look at is true cost at length. Traditionally, industry looks at cost per wafer metrics. Accenture studies what the hidden costs are. We look at Total Cost to Land including NPI re-spin costs, complete organization costs, advanced manufacturing process costs, plus the traditional material and labor costs. The goal is to find a fair comparison with an external manufacturing model that presents key improvement opportunities.

We also look for an integrated roadmap for manufacturing, design technology and intellectual property (IP). There are opportunities to better use IP investments across both leading products and derivatives, resulting in reduced cost in product ramp/readiness. To divest of unproductive assets, high performing firms build an accurate and balanced cost baseline for comparison.

In addition, we also look at strategic sourcing. Semiconductor companies often ask how they can lower costs. Sometimes this has the adverse affect within material quality. Strategic sourcing is an important factor to balance both sides of this equation. We suggest that our clients compare costs objectively against their peer groups and external suppliers. Many times we see lower direct material costs through use of external manufacturing models, because of the manufacturing supplier’s economies of scale.

2. Infusing a higher degree of operational excellence into the business.
Traditionally, semiconductor companies were all about operational excellence. In the late 90s and early 2000s, the industry was about R&D excellence. Now, we see operational excellence in terms of sales and marketing — with the amount of feet on the ground, the amount of time invested per design wins. Accenture strives to understand how companies better integrate sales operations into the manufacturing and production operation process.

Given the focus on external manufacturing, operational excellence is now being applied to the IP Ecosystem. IP management is critical for the current industry landscape. Semiconductor companies need to have a compelling argument to differentiate their IP. IP management and external management have been the crux of the strategy. Companies see the design importance growing. They see the change in their clients’ requests towards a focus on sales operation and the IP ecosystem.

We see a few shifts in sales opeations. Many of Accenture’s clients are challenged when they take emerging products into certain regional and local markets. One key challenge is the ability to maintain consistency in quoting, contracting and ordering. The other challenge is training and investing in sales. Sales is being asked to do more. They seem to spend 45 percent of their time in non-sales activities such as administrative tasks. However, they need to spend much more of their total time than that on sales activities and have others do more of the administration.

When Accenture examines the sales cycles of semiconductor companies, we tend to see limited performance metrics that follow. These companies tend to adhere to regional sales models — and the complexity arises regarding how to be consistent with quoting, contracting and ordering.

3. Maintaining morale and energy in the workforce, especially in the key area of innovation.
One of the key decisions during a downturn is workforce reduction. For those employees remaining with the companies after reductions, it’s key for these companies to re-enforce their connection to the new strategy, and how can they re-adjust from a training perspective to prepare such employees for innovation.

Investing in innovation is a huge priority. The transition Accenture sees in workforce reduction includes engineers feeling a loss of control. To maintain moral and energy, semiconductor executives need to continue to communicate strategic objectives to all employees.

Sometimes amid the change, a semiconductor company needs to ask whether it has thought beyond the change event (portfolio, workforce or facility reductions) and also focused on the complete organizational transition. This is a process of communication — to help employees reconnect with their companies. Getting employees to understand, adapt and connect to the new direction takes a lot longer, and it also impacts productivity. Yet it must be emphasized.

Part II continues tomorrow. Stay tuned, folks!

Measuring performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future


There is this really great story from IBM Research Labs that I simply have to seed here for my readers.

IBM’s scientists have created a method to measure the performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future. Of course, you can also read it on IBM Research Lab’s site as well as on CIOL’s semicon site.

IBM scientists have measured the distribution of electrical charges in tubes of carbon that measure less than 2nm in diameter, 50,000 times thinner than a strand of human hair.

This novel technique, which relies on the interactions between electrons and phonons, provides a detailed understanding of the electrical behavior of carbon nanotubes, a material that shows promise as a building block for much smaller, faster and lower power computer chips compared to today’s conventional silicon transistors.

Phonons are the atomic vibrations that occur inside material, and can determine the material’s thermal and electrical conductivity. Electrons carry and produce the current. Both are important features of materials that can be used to carry electrical signals and perform computations.

The interaction between electrons and phonons can release heat and impede electrical flow inside computer chips. By understanding the interaction of electrons and phonons in carbon nanotubes, the researchers have developed a better way to measure their suitability as wires and semiconductors inside of future computer chips.

In order to make carbon nanotubes useful in building logic circuitry, scientists are pushing to demonstrate their high speed, high packing density and low power consumption capabilities as well as the ability to make them viable for potential mass production.

Dr. Phaedon Avouris, IBM Fellow and lead researcher for IBM’s carbon nanotube efforts, said: “The success of nanoelectronics will largely depend on the ability to prepare well characterized and reproducible nano-structures, such as carbon nanotubes. Using this technique, we are now able to see and understand the local electronic behavior of individual carbon nanotubes.”

To date, researchers have been able to build carbon nanotube transistors with superior performance, but have been challenged with reproducibility issues. Carbon nanotubes are sensitive to environmental influences.

For example, their properties can be altered by foreign substances, affecting the flow of electrical current and changing device performance. These interactions are typically local and change the density of electrons in the various devices of an integrated circuit, and even along a single nanotube.

SEMI materials outlook: Semicon West 2014


Source: SEMI, USA.

Source: SEMI, USA.

At the recently held Semicon West 2014, Daniel P. Tracy, senior director, Industry Research and Statistics, SEMI, presented on SEMI Materials Outlook. He estimated that semiconductor materials will see unit growth of 6 percent or more. There may be low revenue growth in a large number of segments due to the pricing pressures and change in material.

For semiconductor eequipment, he estimated ~20 percent growth this year, following two years of spending decline. It is currently estimated at ~11 percent spending growth in 2015.

Overall, the year to date estimate is positive growth vs. same period 2013, for units and materials shipments, and for equipment billings.

For equipment outlook, it is pointing to ~18 percent growth in equipment for 2014. Total equipment orders are up ~17 percent year-to-date.

For wafer fab materials outlook, the silicon area monthly shipments are at an all-time high for the moment. Lithography process chemicals saw -7 percent sales decline in 2013. The 2014 outlook is downward pressure on ASPs for some chemicals. 193nm resists are approaching $600 million. ARC has been growing 5-7 percent, respectively.

For packaging materials, the Flip Chip growth drivers are a flip chip growth of ~25 percent from 2012 to 2017 in units. There are trends toward copper pillar and micro bumps for TSV. Future flip chip growth in wireless products are driven by form factor and performance. BB and AP processors are also moving to flip chip.

There has been growth in WLP shipments. Major applications for WLP are driven by mobile products such as smartphones and tablets. It should grow at a CAGR of ~11 percent in units (2012-2017).

Solder balls were $280 million market in 2013. Shipments of lead-free solder balls continues to increase. Underfillls were $208 million in 2013. It includes underfills for flip chip and packages. The increased use of underfills for CSPs and WLPs are likely to pass the drop test in high-end mobile devices.

Wafer-level dielectrics were $94 million market in 2013. Materials and structures are likely to enhance board-level reliability performance.

Die-attach materials has over a dozen suppliers. Hitachi Chemical and Henkel account for major share of total die attach market. New players are continuing to emerge in China and Korea. Stacked-die CSP package applications have been increasing. Industry acceptance of film (flow)-over-wire (FOW) and dicing die attach film (DDF) technologies are also happening.

 

Semiconductor capital spending outlook 2013-18: Gartner


At Semicon West 2014, Bob Johnson, VP Research, Gartner, presented the Semiconductor Capital Spending Outlook at the SEMI/Gartner Market Symposium on July 7.

First, a look at the semiconductor revenue forecast: it is likely to grow at a 4.3 percent CAGR from 2013-2018. Logic continues to dominate, but growth falters. As per the 2013-2018 CAGRs, logic will be growing 3.5 percent, memory at 4.5 percent, and other at 6.3 percent.

Bob Johnson

Bob Johnson

As for the memory forecast, NAND should surpass DRAM. At 2013-2018 CAGRs, DRAM should grow -1.1 percent, while NAND should grow 10.8 percent. Smartphone, SSD and Ultramobile are the applications driving growth through 2018. SSDs are powering the NAND market.

Among ultramobiles, tablets should dominate through 2018. They should also take share from PCs. Next, smartphones have been dominating mobile phones.

Looking at the critical markets for capital investment, smartphones are the largest growth segment, but have been showing signs of saturation. The revenue growth could slow dramatically by 2018. Ultramobiles have the highest overall CAGR, but at the expense of PC market. Tablets are driving down semiconductor content. Desktop and notebook PCs are a large, but declining market. This also requires critical revenue to fund logic capex. Lastly, SSDs are driving NAND Flash growth. The move to data centers is driving sustainable growth.

In capital spending, memory is strong, but logic is weak through 2018. The 2014 spending is up 7.1 percent, driven by strong memory market. Strength in NAND spending will drive future growth. Note that memory oversupply in 2016 can create next cycle. NAND is the capex growth driver in memory spending.

The major semiconductor markets, which justify investment in logic leading edge capacity, are now running out of gas. Ultramobiles are cannibalizing PCs, smartphones are saturating and both are moving to lower cost alternatives. It is increasingly difficult to manufacture complex SoCs successfully at the absolute leading edge. Moore’s Law is slowing down, while costs are going up. Breakthrough technologies (i.e., EUV) are not ready when needed. Much of the intelligence of future applications is moving to the cloud. The data centers’ needs for fast, low power storage solutions are creating sustainable growth for NAND Flash.

The traditional two-year per node pace of Moore’s Law will continue to slow down. Only a few high volume/high performance applications will be able to justify the costs of 20nm and beyond. Whether this will require new or upgraded capacity is uncertain. 28nm will be a long lived node as mid-range mobility products demand higher levels of performance. Finally, the cloud will continue to grow in size and influence creating demand for new NAND Flash capacity and technology.

Categories: Semiconductors

How Intel competes on today’s fabless ecosystem?


The SEMI/Gartner Market Symposium was held Semicon West 2014 at San Francisco, on July 7. Am grateful to Ms. Becky Tonnesen, Gartner, and Ms Agnes Cobar, SEMI, for providing me the presentations. Thanks are also due to Ms Deborah Geiger, SEMI.

Dean Freeman, research VP, Gartner, outlined the speakers:

• Sunit Rikhi, VP, Technology and Manufacturing Group, GM, Intel Custom Foundry Intel, presented on Competing in today’s Fabless Ecosystem.

• Bob Johnson, VP Research, Gartner, presented the Semiconductor Capital Spending Outlook.

• Christian Gregor Dieseldorff, director Market Research, SEMI, presented the SEMI World Fab Forecast: Analysis and Forecast for Fab Spending, Capacity and Technology.

• Sam Wang, VP Research Analyst, Gartner, presented on How Foundries will Compete in a 3D World.

• Jim Walker, VP Research, Gartner, presented on Foundry versus SATS: The Battle for 3D and Wafer Level Supremacy.

• Dr. Dan Tracy, senior director, Industry Research & Statistics, SEMI, presented on Semiconductor Materials Market Outlook.

Let’s start with Sunit Rikhi at Intel.

As a new player in the fabless eco-system, Intel focuses on:
* The value it brings to the table.
* How it delivers on platforms of capability and services.
* How it leverage the advantages of being inside the world’s leading Integrated Device Manufacturer (IDM)
* How it face the challenges of being inside the world’s leading IDM.

Intel sunit-rikhiIntel has leadership in silicon technologies. Transistor performance per watt is the critical enabler for all. Density improvements offset wafer cost trends. Intel currently has ~3.5-year lead in introducing revolutionary transistor technologies.

In foundry capabilities and services platforms, Intel brings differentiated value on industry standard platforms. 22nm was started in 2011, while 14nm was started in 2013. 10nm will be starting in 2015. To date, 125 prototype designs have been processed.

Intel offers broad capability and services on industry standard platforms. It also has fuller array of co-optimized end-to-end services. As for the packaging technology, Intel has been building better products through
multi-component integration. Intel has also been starting high on the yield learning curve.

Regarding IDM challenges, such as high-mix-low-volume configuration, Intel has been doing configuration optimization in tooling and set-up. It has also been separating priority and planning process for customers. Intel has been providing an effective response for every challenge.

Some of Intel Custom Foundry announced customers include Achronix, Altera, Microsemi, Netronome, Panasonic and Tabula.

Is GaN-on-Si disruptive technology?


The mass adoption of GaN on Si technology for LED applications remains uncertain. Opinions regarding the chance of success for LED-On-Si vary widely in the LED industry from unconditional enthusiasm to unjustified skepticism. Although significant improvements have been achieved, there are still some technology hurdles (such as performance, yields, CMOS compatibility, etc.).

The differential in substrate cost itself is not enough to justify the transition to GaN on Si technology. The main driver lies in the ability to manufacture in existing, depreciated CMOS fabs in 6” or 8”. For Yole Développement, if technology hurdles are cleared, GaN-on-Si LEDs will be adopted by some LED makers, but it will not become an industry standard.

Yole is more optimistic about the adoption of GaN on Si technology for power GaN devices. Contrary to LED industry, where GaN on Sapphire technology is the main stream and presents a challenging target, GaN on Si will dominate the GaN based power electronics applications. Although the GaN based devices remain more expensive than Si based devices, the overall cost of GaN device for some applications are expected to be lower three years from now according to some manufacturers.

Source:  Yole Développement, France.

Source: Yole Développement, France.

In 2020, GaN could reach more than 7 percent of the overall power device market and GaN on Si will capture more than 1.5 percent of the overall power substrate volume, representing more than 50 percent of the overall GaN on Si wafer volume, subjecting to the hypothesis that the 600 V devices would take off in 2014-2015.

GaN targets a $15 billion served available device market. GaN can power 4 families of devices and related applications. These are blue and green laser diodes, LEDs, power electronics and RF (see image).

Regarding GaN-on-Si LED, there will be no more than 5 percent penetration by 2020. As for GaN-on-GaN, it will be less than 2 percent. Yole considers that the leading proponents of LED-On-Si will successful and eventually adopt Si for all their manufacturing. Those include Bridgelux/Toshiba, Lattice Power, TSMC and Samsung. It expects that Silicon will capture 4.4 percent of LED manufacturing by 2020.

GaN wafer could break through the $2000 per 4” wafer barrier by 2017 or 2018, enabling limited adoption in applications that require high lumen output other small surfaces.

Plunify’s InTime helps FPGA design engineers meet timing and area goals!


Kirvy Teo

Kirvy Teo

Engineers designing FPGA applications face many challenges. Using Plunify’s automation and analysis platform, engineers can run 100 times more builds, analyze a larger set of builds and quickly zoom in on better quality results. Using data analytics and the cloud, Plunify created new capabilities for FPGA design, with InTime being an example.

Kirvy Teo said: What happens when you need to close timing in FPGA design and still can’t get it to work? Here is a new way to solve that problem – machine learning and analytics. InTime is an expert software that helps FPGA design engineers meet timing and area goals by recommending “strategies”. Strategies are combination of settings found in the existing FPGA software. With more than 70 settings available in the FPGA software, no sane FPGA design engineer have the time or capacity to understand how these affect the design outcomes.

One of the common methods now is to try random bruteforce using seeds. This is a one-way street. If you get to your desired result, great! If not, you would have wasted a bunch of time running builds with you none the wiser. Another aspect of running seeds is that the variance of the results is usually not very big, meaning you can’t run seeds on a design with bad timing scores.

However, using InTime, all builds become part of the data that we used to recommend strategies that can give you better results, using machine learning and predictive analytics. This means you will definitely get a better answer at the end of the day, and we have seen 40 percent performance improvements on designs!

How has Plunify been doing this year so far? According to Teo, Plunify did a controlled release to selected customers in first quarter of 2014, who are mainly based in China. It is easier to guess who as we nicknamed them “BCC” – Big Chinese Corporations.

Unsurprisingly, they have different methodologies to solving timing problems and design guidelines, many of which were done to pre-empt timing problems at the later stage of the design. InTime was a great way to help them to achieve their performance targets without disrupting their tool flows.

Plunify is announcing the launch of InTime during DAC and will be looking to partner with sale organizations in US.

What’s the future path likely to be? Teo added: “Machine learning and predictive analytics are one of the hottest topics and we have yet seen it being used much in chip design. We see a lot of potential in this sector. Beyond what InTime is doing now, there are still many chip design problems that can be solved with similar techniques.

“First, there is a need to determine the type of problems that can be solved with these techniques. Second, we are re-looking at existing design problems and wondering, if I can throw 100 or 1000 machines to this problem, can I get a better result? Third, how to get that better result without even running it!

“As you know, we do offer a FPGA cloud platform on Amazon. One of the most surprising observations is that people do not know how to use all those cheap power in the cloud! FPGA design is still confined to a single machine for daily work, like email. Even if I give you 100 machines, you don’t know how to check your emails faster! We see the same thing, the only method they know is to run seeds. InTime is what they need to make use of all these resources intelligently.

Why would FPGA providers take up the solution?

The InTime software works as a desktop software which can be installed in internal data centers or desktops. It is on longer just a cloud play. It works with the current  in-house FPGA software that the customer already own. We are helping FPGA providers like Xilinx or Altera, by helping their customers with the designs. They will feel: How about “Getting better results without touching your RTL code!”

Optic2Connect develops software for photonics!


Sean Seah

Sean Seah

Optic2Connect will be present at this year’s DAC. I caught up with Sean Seah, project manager, to find out more.

First, what’s the company’s X factor and why? (What is it that makes your offering special and noteworthy – how are you different from competitors)?

Optic2Connect develops software solutions for the photonics industry. The demand to manage high volumes of data in networks, especially with the current smart-phone and cloud computing trend, has increased tremendously. As design gets more complex, simulation tools need to scale with regard to fidelity and accuracy.

Currently, photonic designers, scientists, and fabrication engineers adopt an approximated approach from the electrical data to build an equivalent optical model, hence losing on device physics details. At the same time the process is long as the model needs to be described block-by-block with denser blocks representing a more detailed model. Our competitors are well established in their respective domains, electrical or optical, but they are strong in their own respective fields. However, intimate knowledge in both are essential to fully understand this newer generation of photonic devices. Failure to understand fully results in false results from the manufacturing.

With patented know-how, Optic2Connect provides software solutions that SOLVES this pertinent challenge. It maps accurately simulations from one domain to another, e.g. electrical to optical. This technology has been developed by a team of researchers at A*Star – Singapore Public Research Institute. The technology overcomes error-prone and detailed oriented simulation setups. We demonstrated the ability to map without losing any fidelity in the simulation files.

Optic2Connect’s IP differs from its competitors because it simulates directly from the beginning device processing, to electrical device performance until the final high-speed optical eye diagram. This is in stark contrast to the usual method of representing their operation using simplified transfer functions.

Furthermore, the Optic2Connect design flow uses the same reliable tools and processes from the semiconductor industry that are fully compatible with the Complementary Metal Oxide Semiconductor (CMOS) fabrication process of silicon microelectronics. This design flow uses standard tools libraries, device models especially for active components such as modulators, and simulation of these components incorporating the models.

How have you been doing this year so far? Seah said: “It has been excellent! We are racing to complete our product prototypes and we secured a contract from an MNC and another from universities.”

What’s the future path likely to be? Seah added: “We intend to further validate our prototype with our partners from industry and academia, and integrating advanced modulation formats into our solutions. We want to offer a fully integrated solution for photonic devices to our customers. Our goal is to offer a one-stop solution for leading integrated-circuit (IC) manufacturers!”

Why this name? You sounded like a telecom company!

Seah said: “We strongly believe the future of communications is via optics which has the ability to circumvent the data bottleneck issues. Optic2Connect is meant to offer connect using optical communications. Our goal is a one-stop solution for optical connections. “

How will the solution significantly shorten product time-to-market and reduce development costs of photonics devices?

For complex photonics devices, minute changes to design parameters are significant and could affect loss performance, and operating voltage requirements. One common approach in the industry today is to physically build the variations into multiple device / runs and test them out. Each run cost is the range of hundreds of thousands and consume precious time. Especially, if the first batch of devices do not meet required parameters and additional batches are required. This cost both money and time, which in turn is more money.

Hence, Optic2Connect provides an elegant solution with our accurate modelling and simulation solutions, this accelerates manufacturing prototypes and at much lower production costs. Our software solutions provide a 10x improvement in time reduction and time to market. Further, our cloud solution overcomes traditional problems of insufficient servers / licenses, especially during periods of peak demand.

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