How semicon firms can achieve high performance — Part II

Friends, as promised, here is the second part of the discussion I had with Accenture’s Scott Grant, based on Accenture’s recent study: Managing Through Challenging Times!

4. Reducing the time to cash for new products.
When companies industrialize the market concept, and they procure design win opportunities, we tend to see critical components involved with this: a) maintaining relationships of requirements from market analysis through final manufacturing build plan; b) leaders who use consistent lifecycle management of a product development flow; and c) IP management with integrated roadmap portfolio capabilities.

“Firms at times are not able to convert concepts to cash quickly. The process to integrate them has several gaps including innovation lifecycles, conversion of R&D concepts to volume products, and ability to optimize the engineering capacity constraints within their P&Ls.”

Product lifecycle management, portfolio & market analytics, and engineer skills/human resource management help to address these gaps. Portfolio management and roadmap planning process are a must. When done, semiconductor companies will be able to map quickly with the customers and the market insights.

5. Sharpening customer focus through more in-depth and accurate customer insight.
Most firms won’t survive if they are unable to gain rapid adoption of their product offering. From our experience, high performing companies build detailed customer usage-models and insight into end-device markets early in their R&D process.

The challenge many find is that without this baseline of understanding it is difficult to convert concepts into cash once the end-product is delivered to the market.

Many of the insights are available from Point of Sale trends, which can help a semicon firm exist at either an OEM (PC, handset, etc.) or distributor. High performers have enhanced the relationship with their work collaborators and customers to gain access to this data. They also build a “Trusted Advisor” relationship where they build scenarios for each end market to better predict what their end-customer may desire in features or functions.

It is difficult for a semicon firm to know how a product will be used. It is really the beginning of gaining insight into utilization, the consumer, and what usage model should be employed. So a semicon firm should study carefully how things can be used in the market. User behavior is crucial. If companies don’t understand that, they may be missing out.

6. Pursuing alliances to share the cost burden of new product development.
The point here is to make sure that semiconductor companies are taking a strategic view and look at the right places to pursue alliances. There’s a lot of impact in pursuing alliances. When semicon companies do this, they can absolutely share the burdens, but it can impact the operating model.

Other recommendations for the industry
What are the other recommendations that Accenture have for the semiconductor industry going forward?

Grant recommends the industry to focus on achieving high performance business results. Those include sustained leadership in various financial metrics such as return to shareholders, profits, and revenue growth.

“Recognize and adapt to the reality that we are now living in a multi-polar world. This is a world in which a growing number of emerging countries and economies are becoming more financially powerful, competitive and relevant in competing against the traditionally more developed parts of the world such as North America, Asia and Europe. This means there are a multitude of growing business opportunities in these emerging nations for semiconductor companies to capitalize on.

“Proactively invest during a recession rather than pull back investments and just wait until the economy pulls out of this down cycle. History has shown that those companies that invest the most perform better in the years after the market recovers.”

Companies repeating mistakes?
Now, these recessions always have a bad habit of occuring cyclically! Therefore, why do semiconductor (and other) companies tend to repeat those same mistakes again and again?

According to Grant, one reason is they tend to indiscriminately and rapidly cut costs without thinking more strategically and carefully about what costs to cut. “They tend to lay off workers who they need when the market recovers, but they can’t hire them back because those employees have moved on with their careers. These semiconductor companies don’t think hard enough about what employees and assets they will need when the market recovers.”

Layoffs? What about design and development?
Finally, are layoffs the only solution to combat recession? What happens to design and development?

Grant agrees that layoffs are absolutely not the only solution to combat recession. Investing in core competencies is crucial, and spending less time and effort on non-core capabilities is important.

“Employee morale tends to fall within design and development during a recession because they see some of their colleagues lose their jobs and they take on more work. And they lose more control of what work they are assigned to do. And they’re less secure about their job security.

“But, much of this can be alleviated by giving employees a chance to share their ideas and concerns at regularly scheduled Town Hall meetings, to communicate with them regularly and candidly, and to focus them on achieving high performance business results.”

CONCLUDED

How semicon firms can achieve high performance by simplifying business!

Engineers in the global semiconductor industry have typically have had considerable control of their work. Processes are pretty straightforward, sequential, and logical — and satisfying for an honest day’s work.

However, due to the ongoing global economic downturn, many of these engineers are rapidly losing control of more of their professional lives. Caught like the rest of the world in a recession, they are losing more control of what work they are assigned to do, how they do it, in what sequence, by when and with whom.

Given these inter-related problems, many semiconductor companies need to make rapid and fundamental changes in their business operations, strategies and workforce management practices to emerge from this downturn, and for year beyond, as high performers.

Once this recession ends, these people will be entering a market with a different landscape than the market that existed when the downturn began. They need to figure out how to restart their businesses, regain their footing and connect to a new purpose.

They need to address the so-called ‘soft’ aspects of business, such as the engineers who design chips and how they feel. It’s time for them to pay more attention to the little things that may seem innocuous but are actually central to achieving high performance.

Thanks to Charlie Hartley, Accenture, US, I was able to get hold of Accenture’s recent study: Managing Through Challenging Times!! Quite an interesting read!

Naturally, it led to a conversation with Scott Grant, Executive Global Lead of Accenture’s Semiconductor Operating Unit (see image here), who led the research and analysis of this new Accenture report released now about these issues and recommended solutions.

Accenture’s report has seven suggestions or recommendations.

1. Divesting the business of unproductive assets.
2. Infusing a higher degree of operational excellence into the business.
3. Maintaining morale and energy in the workforce, especially in the key area of innovation.
4. Reducing the time to cash for new products.
5. Sharpening customer focus through more in-depth and accurate customer insight.
6. Pursuing alliances to share the cost burden of new product development.
7. Acquiring key assets.

Let’s take a look at those, one by one!

1. Divesting the business of unproductive assets.
From Accenture’s perspective, it has become evident during the past few years that among the top 20 semiconductor a growing number are fabless. That trend will continue in the future mainly because fabless companies have more competitive cost structures than semiconductor manufacturing companies that incur such high fixed-asset costs for their operations. Accenture’s clients (customers) are seeking to understand the business operating model that best fits their desired position in the market. Our assessment leads to having a leaner product portfolio.

The first thing we look at is true cost at length. Traditionally, industry looks at cost per wafer metrics. Accenture studies what the hidden costs are. We look at Total Cost to Land including NPI re-spin costs, complete organization costs, advanced manufacturing process costs, plus the traditional material and labor costs. The goal is to find a fair comparison with an external manufacturing model that presents key improvement opportunities.

We also look for an integrated roadmap for manufacturing, design technology and intellectual property (IP). There are opportunities to better use IP investments across both leading products and derivatives, resulting in reduced cost in product ramp/readiness. To divest of unproductive assets, high performing firms build an accurate and balanced cost baseline for comparison.

In addition, we also look at strategic sourcing. Semiconductor companies often ask how they can lower costs. Sometimes this has the adverse affect within material quality. Strategic sourcing is an important factor to balance both sides of this equation. We suggest that our clients compare costs objectively against their peer groups and external suppliers. Many times we see lower direct material costs through use of external manufacturing models, because of the manufacturing supplier’s economies of scale.

2. Infusing a higher degree of operational excellence into the business.
Traditionally, semiconductor companies were all about operational excellence. In the late 90s and early 2000s, the industry was about R&D excellence. Now, we see operational excellence in terms of sales and marketing — with the amount of feet on the ground, the amount of time invested per design wins. Accenture strives to understand how companies better integrate sales operations into the manufacturing and production operation process.

Given the focus on external manufacturing, operational excellence is now being applied to the IP Ecosystem. IP management is critical for the current industry landscape. Semiconductor companies need to have a compelling argument to differentiate their IP. IP management and external management have been the crux of the strategy. Companies see the design importance growing. They see the change in their clients’ requests towards a focus on sales operation and the IP ecosystem.

We see a few shifts in sales opeations. Many of Accenture’s clients are challenged when they take emerging products into certain regional and local markets. One key challenge is the ability to maintain consistency in quoting, contracting and ordering. The other challenge is training and investing in sales. Sales is being asked to do more. They seem to spend 45 percent of their time in non-sales activities such as administrative tasks. However, they need to spend much more of their total time than that on sales activities and have others do more of the administration.

When Accenture examines the sales cycles of semiconductor companies, we tend to see limited performance metrics that follow. These companies tend to adhere to regional sales models — and the complexity arises regarding how to be consistent with quoting, contracting and ordering.

3. Maintaining morale and energy in the workforce, especially in the key area of innovation.
One of the key decisions during a downturn is workforce reduction. For those employees remaining with the companies after reductions, it’s key for these companies to re-enforce their connection to the new strategy, and how can they re-adjust from a training perspective to prepare such employees for innovation.

Investing in innovation is a huge priority. The transition Accenture sees in workforce reduction includes engineers feeling a loss of control. To maintain moral and energy, semiconductor executives need to continue to communicate strategic objectives to all employees.

Sometimes amid the change, a semiconductor company needs to ask whether it has thought beyond the change event (portfolio, workforce or facility reductions) and also focused on the complete organizational transition. This is a process of communication — to help employees reconnect with their companies. Getting employees to understand, adapt and connect to the new direction takes a lot longer, and it also impacts productivity. Yet it must be emphasized.

Part II continues tomorrow. Stay tuned, folks!

Measuring performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future

There is this really great story from IBM Research Labs that I simply have to seed here for my readers.

IBM’s scientists have created a method to measure the performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future. Of course, you can also read it on IBM Research Lab’s site as well as on CIOL’s semicon site.

IBM scientists have measured the distribution of electrical charges in tubes of carbon that measure less than 2nm in diameter, 50,000 times thinner than a strand of human hair.

This novel technique, which relies on the interactions between electrons and phonons, provides a detailed understanding of the electrical behavior of carbon nanotubes, a material that shows promise as a building block for much smaller, faster and lower power computer chips compared to today’s conventional silicon transistors.

Phonons are the atomic vibrations that occur inside material, and can determine the material’s thermal and electrical conductivity. Electrons carry and produce the current. Both are important features of materials that can be used to carry electrical signals and perform computations.

The interaction between electrons and phonons can release heat and impede electrical flow inside computer chips. By understanding the interaction of electrons and phonons in carbon nanotubes, the researchers have developed a better way to measure their suitability as wires and semiconductors inside of future computer chips.

In order to make carbon nanotubes useful in building logic circuitry, scientists are pushing to demonstrate their high speed, high packing density and low power consumption capabilities as well as the ability to make them viable for potential mass production.

Dr. Phaedon Avouris, IBM Fellow and lead researcher for IBM’s carbon nanotube efforts, said: “The success of nanoelectronics will largely depend on the ability to prepare well characterized and reproducible nano-structures, such as carbon nanotubes. Using this technique, we are now able to see and understand the local electronic behavior of individual carbon nanotubes.”

To date, researchers have been able to build carbon nanotube transistors with superior performance, but have been challenged with reproducibility issues. Carbon nanotubes are sensitive to environmental influences.

For example, their properties can be altered by foreign substances, affecting the flow of electrical current and changing device performance. These interactions are typically local and change the density of electrons in the various devices of an integrated circuit, and even along a single nanotube.

On-chip networks: Future of SoC design

Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.

John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage – saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.

Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.

For the record, there are several SoC integration challenges that need to be addressed, such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.

SGN exceeds requirements
SGN met the tablet performance requirement with fabric frequency of 1066MHz. It has an efficient gate count of 508K gates. There are features such as an advanced system partitioning, security and I/O coherency. There is support for system concurrency as well as advanced power management.

Sonics offers system IP solutions such as SGN, a router based NoC solution, with flexible partitioning and VC (Virtual Channel) support. The frequency is optimized with credit based flow control.

SSX/SLX is message based crossbar/ShareLink solutions based on interleaved multi-channel technology. It has target based QoS with three arbitration levels. The SonicsExpress is for power centric clock domain crossing. There is sub-system re-use and decoupling. The MemMax manages and optimizes the DRAM efficiency while maintaining system QoS. There is run-time programmability for all traffic types. The SonicsConnect is a non-blocking peripheral interconnect.

Convergence of PV materials, test and reliability: What really matters?

SEMI, USA recently hosted the seminar on ‘Convergence of PV Materials, Test and Reliability: What Really Matters?

Reliability in growing PV industry
Speaking on the importance of reliability to a growing PV industry, Sarah Kurtz, principal scientist, Reliability group manager, NREL, said that confidence in long-term performance is a necessity in the PV industry. Current failure rates are low. There is need to demonstrate confidence so that failure rates will stay low. There has been exponential growth of the PV industry so far. PV is a significant fraction of new installations. It now represents a significant fraction of new electricity generating installations of all kinds.

How does one predict the lifetime of PV modules? There has been a qualification test evolution for JPL block buys. Most studies of c-Si modules show module failures are small. Internal electrical current issues often dominate.

The vast majority of installations show very low PV module failure rates (often less than 0.1 percent). There has been evidence that PV is low risk compared to other investments. To sustain the current installation rate, we need to demonstrate confidence that justifies the annual investment of $100 million or so.

Critical factors in economic viability of PV
DuPont has broad capabilities under one roof. It offers materials, solar cell design, and processes integrated with panel engineering. Speaking about Critical factors in economic viability of PV – materials matter – Conrad Burke, global marketing director, DuPont PV Solutions, said that material suppliers have a distinct advantage to view trends. The industry can expect consolidation among large PV module producers and large materials suppliers.

There is an increasing dependence on materials suppliers for processes, tech support and roadmap. There is renewed attention to long-term reliability and quality of materials in PV products.

There is a race for survival among panel producers. There are dropping prices for solar panels, and quality is getting compromised. There are reduced incentives in established markets. The market will continue to grow. Key factors that determine investment return for PV include lifetime, efficiency and cost.

When materials fail, the consequences are dire. There are failures such as encapsulant discoloration, backsheet failure, glass delamination, etc. Average defect rates in new-build modules has been increasing. Significant number of PV installations do not deliver the projected RoI. The system lifetime is as important as cost and incentives.

Solar cell power continues to improve. There have been improvements from metal pastes and processes. Performance loss impacts the RoI. The US Department of Energy hired JPL to develop 30-year PV modules. Recent cost pressures have led to the dramatic changes in module materials and a lack of transparency.

Analyzing modules from the recent service environments show performance issues. Certification does not mitigate risk. Tests do not predict the actual field performance. He showed tier-1 solar panel manufacturing problems from China, Japan and the USA. Backsheet is critical to protect solar panels. Few materials have lengthy field experience. We will continue to see drop in prices for solar panels and opening of new markets. Focus for PV module makers will remain efficiency, etc.

Why do we need 450mm wafers?

Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

Mike Bryant.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.

Optimizing Ethernet networks for mobile access and cloud service delivery

Uday Mudoi.

Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).

Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.

Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.

ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.

ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.

Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.

The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.

Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure
network for L2 VPN services at 50 percent lower cost than alternative solutions.

Tensilica to expand Cadence IP footprint in SoCs

Chris Rowan.

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.

Embedded systems trends and developer opportunities

Herb Hinstorff.

Today, the world is transitioning from independent devices to  connected systems. Intel has been inside the embedded systems market for over 35 years, having developed 270+ CPUs and SoCs as well as 100+ chipsets.

Herb Hinstorff, director of Marketing, Developer Products Division, Intel Software, said that Intel has been engaged at all levels of the solution stack. He was speaking at the 13th Global Electronics Summit at Santa Cruz, USA.

There are tools to deliver on developer needs, such as debuggers, analyzers, compilers and libraries. There are tools to provide the deep system-level insights into power, reliability and performance.

On the debuggers side, they increase system and device stability and reliability. There is an efficient system, SoC-wide defect analysis and ultra-fast system-wide tracing for software debug. There is an integrated application level debugger. Overall, it speeds system bring-up and development. Analyzers focus on boosting reliability, power efficiency and performance, enabling differentiated designs, system-wide analysis and deep insights.

Compilers go on to optimize performance and efficiency. There is the industry-leading C/C++ compiler. It boosts system and application performance on Intel Atom, Core and Xeon processors. Compilers also take advantage of the multicore to boost performance.

There are libraries for performance and efficiency. Software building blocks increase the developer productivity and boost performance. There are specialized testing functions that handle signal processing, data processing, complex math operations and multimedia processing. Besides, there is future-proof software investments. The libraries provide an easy way to take advantage of the multicore capabilities to boost performance.

The Intel System Studio is an integrated software tool suite that provides deep, system-wide insights to help accelerate time-to-market, strengthen system reliability, and boost power effiency and performance. The JTAG interface has system and application code running Linux.

There is a continued broadening of the OS support, and a broader range of tools to match the expanding SoC capabilities. There is more extensive software based training and simulation, as well as market-specific libraries and APIs.

Given that the market is transitioning from independent devices to connected systems, more capable SoC platforms and complex software stacks require deeper and broader system-level insights and optimizations. Embedded developers can take advantage of the Intel System Studio to accelerate the time-to-market, strengthen system reliability, and boost power efficiency and performance of the Intel architecture-based embedded and mobile systems.

Algotochip building ecosystem with IP providers in targeted markets

Satish Padmanabhan.

Algorithm-to-chips is Algotochip’s mission. It turns algorithms into chips by converting your behavioral algorithm C-code into architecture C-code into RTL into GDS-II.

Speaking about architecture evolution at the 13th Global Electronics Summit at Santa Cruz, USA, Satish Padmanabhan, CTO and founder, Algotochip, said that the interconnect between CPU and all the HA blocks needs to be determined.

The market approach includes building an ecosystem with leading IP providers in targeted markets. Some areas Algotochip is looking at are LTE and smart grid markets.

Nitto Denko is committed to support Algotochip moving forward. Year 2013 will see significant investment increases in terms of engineering resources, as well as sales and marketing organization to cover USA, China and Japan.

Algotochip is showing that its technology is sound in improving system hardware and software partitioning and first time right design. The LTE turbo decoder performances in terms of throughput, power and gates count is showing the benefits of Algotochip BlueBox. The company is now building an ecosystem around its technology.

ARM Holdings and Tensilica are the first of the few partners that Algotochip wants to collaborate with to improve the overall time-to-market of digital design of the SoC, ASIC and FPGA, etc.