The number of MEMS and sensors going into mobile, consumer and gaming applications is expected to continue to skyrocket. As a result, OSAT and Wafer foundry players are getting more and more interest in MEMS module packaging, as volume and complexity of MEMS SiP modules is increasing dramatically, said Dr. Eric Mourier, Yole Developpement.
It implies that IDMs needs to find second source partnersand qualify some OSATs in order to secure their supply chain. Also, standardization(coming from both foundries, OSAT, WLP houses or substrate suppliers) is critical and necessary to implement in order to keep the packaging, assembly, and test cost of MEMS modules under control. There are many different players with different designs, and it’s not likely we’ll see one solution adopted by all the players.
As for wafer-level packaging (WLP) for LEDs, WLP has not been strongly deployed in the LED industry due to associated technical challenges. In the short-term, there is ESD integration in Si substrate. In the long-term, LED drivers could be integrated at the package level for Intelligent lighting. Ultimately, there are wafer-to-wafer manufacturing schemes for certain packaget types.
Real production of HB-LEDs with a mixed approach of WLP+through silicon vias (TSV) is just starting. There are some Taiwanese players such as TSMC, Xintec, Visera, Touch MicroTech and Sibdi, and South Korea-based LG Innotek. Additional players in the semiconductor and MEMS industry are seeking to enter the field.
SiC is implemented in several power systems and is gaining momentum and credibility.
Yole Developpement stays convinced that the most pertinent market for SiC lands in high and very high voltage (more than 1.2kV), where applications are less cost-driven and where few incumbent technologies can’t compete in performance. This transition is on its way as several device/module makers have already planned such products at short term.
Even though EV/HEV skips SiC, the industry could expand among other apps. The only question remains: Is there enough business to make so many contenders live decently? Probably, yes, as green-techs are expanding fast, strongly requesting SiC. Newcomers should carefully manage strategy and properly size capex according to the market size.
Power electronics industry outlook
Electronics systems were worth $122 billion in 2012, and will likely grow to $144 billion by 2020 at a CAGR of 1.9 percent. Power inverters will grow from $41 billion in 2012 to over $70 billion by 2020 at a CAGR of 7.2 percent. Semiconductor power devices (discretes and modules) will grow from $12.5 billion in 2012 to $21.9 billion by 2020 at a CAGR of 7.9 percent. Power wafers will grow $912 million in 2012 to $1.3 billion by 2020 at a CAGR of 5.6 percent.
Looking at the power electronics market in 2012 by application and the main expectations to 2015, computer and office will account for 25 percent, industry and energy 24 percent, consumer electronics 18 percent, automotive and transport 17 percent, telecom 7 percent and others 9 percent.
The main trends expected for 2013-2015 are:
* Significant increase of automotive sector following EV and HEV ramp-up.
* Renewable energies and smart-grid implementation will drive industry sector ramp-up.
* Steady erosion of consumer segment due to pressure on price (however, volumes (units) will keep on increase).
The 2011 power devices sales by region reveals that overall, Asia is still the landing-field for more than 65 percent of power products. Most of the integrators are located in China, Japan or Korea. Europe is very dynamic as well with top players in traction, grid, PV inverter, motor control, etc. Asia leads with 39 percent, followed by Japan with 27 percent, Europe with 21 percent and North America with 13 percent.
The 2011 revenues by company/headquarter locations reveals that the big-names of the power electronics industry are historically from Japan. Nine companies of the top-20 are Japanese. There are very few power manufacturers in Asia except in Japan. Europe and US are sharing four of the top five companies. Japan leads with 42 percent, followed by Europe and North America with 28 percent each, respectively, and Asia with 2 percent.
Looking at the TAM comparison for SiC (and GaN), very high voltage, high voltage of 2kV and medium voltage of 1.2kV appear as a more comfortable area for SiC. The apps are less cost-driven and SiC added value is obvious. Low voltage from 0-900V is providing strong competition with traditional silicon technologies, SJ MOSFET and GaN. There are cost-driven apps.
It is always a pleasure to chat with Dr. Wally (Walden C.) Rhines, chairman and CEO, of Mentor Graphics. I chatted with him, trying to understand gigascale design, verification trends, strategy for power-aware verification, SERDES design challenges, migrating to 3D FinFET transistors, and Moore’s Law getting to be “Moore Stress”!
Chip design in gigascale, hertz, complex
First, I asked him to elaborate on how implementation of chip design will evolve, with respect to gigascale design, gigahertz and gigacomplex geometries.
He said: “Thanks to close co-operation among members of the foundry ecosystem, as well as cooperation between IDMs and their suppliers, serious development of design methods and software tools is running two to three generations ahead of volume manufacturing capability. For most applications, “Gigascale” power dissipation is a bigger challenge than managing the complexity but “system-level” power optimization tools will continue to allow rapid progress. Thermal analysis is becoming part of the designer’s toolkit.”
Functional verification is continually challenged by complexity but there have been, and continue to be, many orders of magnitude improvement in performance just from adoption of emulation, intelligent test benches and formal methods so this will not be a major limitation.
The complexity of new physical design problems will, however, be very challenging. Design problems ranging from basic ESD analysis, made more complex due to multiple power domains, to EMI, electromigration and intra-die variability are now being addressed with new design approaches. Fortunately, programmable electrical rule checking is being widely adopted and will help to minimize the impact of these physical effects.
Is verification keeping up?
How is the innovation in verification keeping up with trends?
Dr. Rhines added that over the past decade, microprocessor clock speeds have leveled out at 3 to 4 GHz and server performance improvement has come mostly from multi-core architectures. Although some innovative approaches have allowed simulators to gain some advantage from multi-core architectures, the speed of simulators hasn’t kept up with the growing complexity of leading edge chips.
Emulators have more than made up the difference. Emulators offer more than four orders of magnitude faster performance than simulators and emulators do so at about 0.005X the cost per cycle of simulation. The cost of power per year is more than one third the cost of hardware in a large simulation farm today, while emulation offers a 12X savings in power per verification clock cycle. For those who design really complex chips, a combination of emulation and simulation, along with formal methods and intelligent test benches, has become standard.
At the block and subsystem level, high level synthesis is enabling the next move up in design and verification abstraction. Since verification complexity grows at about the square of component count, we have plenty of room to handle larger chips by taking advantage of the four orders of magnitude improvement through emulation plus another three or four orders of magnitude through formal verification techniques, two to three orders of magnitude from intelligent test benches and three orders of magnitude from higher levels of abstraction.
By applying multiple engines and multiple abstraction levels to the challenge of verifying chips, the pressure is on to integrate the flow. Easily transitioning and reusing verification efforts from every level—including tests and coverage models, from high level models to RTL and from simulation to emulation—is being enabled through more powerful and adaptable verification IP and high level, graph-based test specification capabilities. These are keys to driving verification reuse to match the level of design reuse.
Powerful verification management solutions enable the collection of coverage information from all engines and abstraction levels, tracking progress against functional specifications and verification plans. Combining verification cycle productivity growth from emulation, formal, simulation and intelligent testing with higher verification abstraction, re-use and process management provides a path forward to economically verifying even the largest, most complex chips on time and within budget.
Good power-aware verification strategy for SoCs
What should be a good power-aware verification strategy for SoCs
According to him, the most important guideline is to start power-aware design at the highest possible level of system description. The opportunity to reduce system power is typically an order of magnitude greater at the system level than at the RTL level. For most chips today, that means at least the transaction level when the design is still described in C++ or SystemC.
Significant experience and effort should then be invested at the RTL level using synthesis and UPF-enabled simulation. Verification solutions typically automate the generation of correctness checks for power-control sequences and power-state coverage metrics. As SoC power is typically managed by software, the value of a hardware/software co-verification and co-debug solution in simulation and emulation becomes apparent in power-management verification at this level.
As designers proceed to the gate and transistor level, accuracy of power estimation improves. That is why gate level analysis and verification of the fully implemented power management architecture is important. Finally, at the physical layout, designers traditionally were stuck with whatever power budget was passed down to them. Now,they increasingly have power goals that can be achieved using dozens of physical design techniques that are built into the place and route tools.
There are more available solutions than ever in power devices, according to Alexandre Avron, market and technology analyst, Yole Développement. The landscape is moving, and its moving quite fast, from every region of the world.
There are many opportunities for power device manufacturers. This is the time for strong strategic planning and making the best choices. He was speaking at a seminar on the power semiconductor devices industry, in Lyon, France.
IGBTs and SJ MOSFETs
Silicon is not dead and will still live for a long time. Standard device design are slowly disappearing (planar IGBT, planar MOSFET). IGBT and SJ MOS are highly mature technologies. Rules of competition are evolving.
Historic players need to keep on innovating. New entrants have a different business model: there are more and more foundries, with fab-less and fab-light players. IGBT is still a key asset: master and secure IGBT supply is necessary for system makers. SJ MOSFETS will be used in more and more systems, taking market shares to planar MOSFET.
About SiC and GaN, there is still a big question mark: Where and when? With time, it is becoming clearer. SiC will target medium and high power. From our point of view, medium power (1200V base) is a mean to arrive to high power (+3.3kV). R&D has to go through this to reach higher voltage. The main issue is still on current ratings (having a high impact on cost).
GaN will target low and medium power, and will probably allow extraordinary power supplies designs (Tiny supplies, very high frequency systems). It is almost ready for 600V, but not yet at 1200V. It leaves room for SiC to develop and expand. Major players are involved on both fields — SiC and GaN. They need to be present on both domains, as there will be an overlap, but the split is unclear: we will probably experience a very fine segmentation, not only by voltage or current, but also by frequency, ruggedness, system size, temperature of operation or maybe culture or history.
SiC is now here. First full SiC PV inverters are available. First field tests for SiC in rail traction is ongoing. GaN is under qualification. According to the most advanced players, 600V GaN devices samples are tested by system makers.
Alexandre Avron, market analyst in power electronics, Yole Développement, provided a briefing on semiconductor material’s potential through an analysis of devices and systems for power electronics.
According to him, there is still a bright future for silicon. It will keep good market share until at least 2016 and even further, being cost competitive and very standard. On the other side, SiC is more applied to higher voltages. These are the smallest markets, but probably the one requiring SiC properties the most. PV inverters and EV/HEV are at intermediary voltage levels, they could both be targeted by SiC and GaN, this makes the predictions very difficult.
No technical aspects helps in knowing which material will be more used. They have their advantages and drawbacks, and both deserve their place. Prediction must be based on developments advancements.
The points to watch about SiC and GaN devices include: samples availability is a main point for future integration, reliability is also a main concern, especially for SiC devices, voltage capability seems to keep GaN at smaller power, and cost: GaN appears to be potentially cheaper, as it is based on Si wafers and can be CMOS compatible. Read more…
SuVolta Inc., based in California, USA, develops and licenses CMOS semiconductor technologies that significantly reduce the power consumption of integrated circuits (ICs). Back in June 2011, introduced the PowerShrink low-power platform and the first licensee, Fujitsu. Thanks to Amanda Crnkovich of The Hoffmann Agency, I interacted with Dr. Scott E. Thompson, CTO, SuVolta, on the deeply depleted channel (DDC) technology that delivers over 50 percent reduction in IC power consumption, while maintaining performance.
What’s DDC technology all about?
First, I asked Dr. Thompson what the DDC technology is all about? He said that SuVolta’s PowerShrink platform in planar, bulk CMOS provides dramatic improvements in variability and device performance, and is compatible with existing CMOS processes. It integrates using conventional fabrication equipment and materials, and enables the reuse of existing circuit IP infrastructure. SuVolta is focusing on solving the power problem in system-on-chips (SoCs) across multiple CMOS process technology nodes.
He added: “SuVolta’s DDC transistor reduces threshold voltage (VT) variability and enables continued CMOS scaling. The structure works by forming a deeply depleted channel when a voltage is applied to the gate. In a typical implementation the DDC channel has several regions – an undoped or very lightly doped region, a VT setting offset region and a screening region. Each implementation of SuVolta’s DDC transistor may vary depending on the wafer fabrication facility and specific chip design requirements.”
The DDC transistor has a much tighter distribution of threshold voltages. In addition, DDC transistors allow for the setting of multiple VTs, which is vital for today’s low-power products.
“Perhaps, the biggest benefit is in embedded SRAM memory blocks. For most chips, lowering supply voltage is limited by the SRAM. However, with a DDC transistor, conventional 6T SRAMs have been demonstrated operating below 500 milli Volts. This is significant as it is amongst the lowest voltage ever reported in a standard embedded SRAM,” added Dr. Thompson.
Impact on reducing IC power consumption in devices
So, what impact will all of this have on reducing IC power consumption in devices, such as smartphones, tablets, etc.? While the increased density in transistors enables more features for all types of devices, power has now become the biggest issue in semiconductors. This “power impasse” is critical or two reasons:
* Excessive power consumption limits battery life for mobile devices, and causes huge electricity bills for server farms.
* Devices are hitting their thermal (heat) limit, thus preventing more capabilities from being added. Power consumption directly creates heat. This is becoming a major problem in mobile devices, which have very strict thermal limits. To hit thermal limits, chip makers must forego adding additional content, or “throttle” the chip back to a slower speed.
The impact of excess power on consumers is profound: shorter battery life, lower-content mobile devices – fewer features and/or slower performance, higher electronics costs because transistors hit their scaling limit because of power, excessive energy bills and an increased global demand for energy.
Dr. Thompson added: “SuVolta’s PowerShrink platform enables semiconductor firms to cut chip power in half without sacrificing performance, losing functionality, or migrating to a more advanced, and costly, semiconductor process node. And, it does so using planar, bulk CMOS, and does not require development of new manufacturing facilities or IP blocks.” Read more…
Lattice Semiconductor Corp. has introduced the low-cost and low-power ECP4 FPGAs. These feature 6Gbps SERDES in low cost wire-bond packages, powerful DSP blocks and hard IP-based communication engines for cost- and power-sensitive wireless, wireline, video, and computing markets.
The LatticeECP4 FPGA family features high performance, low power in low cost 65nm process, making a great FPGA family even better. Lower cost, high yield 65nm process is ideal for mid-range FPGAs. There has been an extensive use of wire-bond packaging. The FPGAs have CDR capable I/Os that lower customers’ implementation cost. The POWER sysDSP minimizes multipliers and LUTs, and enables high bandwidth in a small area. There is also a 10X area reduction by use of hardened MACO communication engines.
The ECP4 features lower power architecture. It is optimized for mid-density devices, and not based on high-density high overhead platform. Modified logic/routing power ratio helps achieve higher performance with modest dynamic power increase. It also features higher bandwidth and performance.
As it is, the FPGA boasts 10X more efficient hard MACO engines. Besides, it has 7X more DSP processing capability, 2X faster SERDES (6G), 66 percent more LUTs, 50 percent higher LVDS performance, 42 percent more memory and 33 percent higher DDR3 I/O performance.
Diamond 1.4 beta design software is available for select customers, especially those who jumpstart cost-effective platform designs. The ECP4 device samples will be available in 1H 2012, and the ECP4 production devices will be available in 2H 2012. Read more…
I had the pleasure of interacting with Dr. Charlie Gay, president, Applied Solar, Applied Materials Inc., recently. He began by saying that solar power was becoming increasingly affordable.
Dr. Gay said: “Most people don’t realize that solar is already cost effective in a number of locations and applications, and as those uses of solar expand, the scale of the industry grows. As scale increases, cost declines in a highly predictable way for manufactured technologies like PV.
“In 2011, PV electricity is already cost-competitive with traditional sources of residential power in 19 countries, including Italy, Spain and the Caribbean. By 2020, this number can grow to more than 100 countries, representing 98 percent of world population; 99.7 percent of world GDP; 99.2 percent of energy related CO2 emissions; and 99.5 percent of global residential electricity consumption. Areas with plenty of sunshine, such as India, already have costs that are a fraction of what they are elsewhere in the world.
“A common rule in the solar power industry is that for each cumulative doubling of installed photovoltaic (PV) solar power (the type of panel commonly seen on the roofs of homes and businesses) the price of solar modules decreases by 18 percent.”
We have now reached a critical inflection point in the cost reduction of solar. Applied continues to drive down cost is to make the manufacturing of solar panels more efficient. The reduced cost is being driven by:
• A decreased cost for silicon, a key ingredient in solar panels.
• Increased capacity in solar panel manufacturing.
• Technology innovation, i.e., ability to cut thinner wafers at higher yields w/less silicon loss.
Dr. Gay added that the cost of manufacturing solar panels is already reported by some to have fallen below $1 per watt and is capable of continued decreases due to reductions in the cost of silicon, innovative crystal growth techniques, high precision printing technologies operating at 3,000 wafers per hour and many more advances based on increased yield and scientific insights. In 2010, for example, approximately 63 gigawatts of cumulative solar PV had been installed worldwide, with 18 installed last year alone.
“Solar power is already an ideal solution for electric power during peak use times in many locations and will continue to get more cost competitive as the manufacturing learning curve continues –namely, that for each cumulative doubling of installed photovoltaic solar power the price of solar modules decreases by 18 percent.” Read more…
STMicroelectronics has introduced the STM32L advanced ultra-low-power Cortex-M3 based MCU platform.
Built on cutting-edge proprietary process – robustness, it is part of a wide 32-bit product portfolio. The MCU platform is based on the just-enough energy concept and has an all inclusive package applications.
STM32L 32- to 128-Kbyte products are entering full production in the second half of March 2011. It is part of the industry’s largest ARM Cortex-M 32-bit microcontroller family with six STM32 families. STMicroelectronics is developing the STM32L portfolio up to 384 Kbytes of embedded memory. The STM32L is also Continua ready for its USB peripheral driver.
STM32L’s robustness has been derived from an automotive qualified process. It is all inclusive for ultra-low-power applications, and comes with hardware integrated features and software library packages. STM32L also has a ‘just-enough energy concept’, which includes undervolting, user controlled and an innovative architecture, all of this for less than 1 µA.
ST’s ultra-low-power EnergyLite platform features ST’s 130nm ultra-low-leakage process technology. It makes use of shared technology, architecture and peripherals. The company’s ultra-low-power portfolio for 2011 will be in production second half of March 2011. Many others will also be in production in the second half of April 2011. In fact, there will be over 100 part numbers from 4- to 384-Kbyte flash, and from 20 to 144 pins.
STM32L is based on ultra-low-power architecture, which is all inclusive for ultra low power applications. It also features ultra-low voltage, with power supply down to 1.8 V with BOR and also down to 1.65 V without BOR.The analog functional can be down to 1.8 V and the reprogramming capability can be down to 1.65 V.
STM32L is also flexible and secure, featuring +/- 0.5 percent internal clock accuracy when trimmed by RTC oscillator. It has up to five clock sources and has the MSI to achieve very low power consumption at seven low frequencies.
It also feattures dynamic voltage scaling in Run mode. The voltage scaling optimizes the product efficiency. User selects a mode (voltage scaling) according to external VDD supply, DMIPS performance required and maximum power consumption. It features the energy saving mode as well, down to 171 µA/DMIPS from Flash in Run mode. Read more…