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Game changers: New paradigms for future of electronic product realization


The Cadence Executive Forum, titled, ‘Game Changers: New Paradigms for the Future of Electronic Product Realization’, was held this evening in Bangalore, India. The speakers were Lip-Bu Tan, president and CEO, Cadence, and Bhaskar Pramanik, chairman of Microsoft India.

In the opening address, Tan remarked that there is likely to be challenging next 12 months in the USA and Europe. It may also impact the Asia Pacific region. However, from an EDA perspective, there will be new design, as companies would be involved in designing next-generation products and killer applications. There will also be more consolidation, which will continue. Another trend is that the number of start-ups has dropped.

There are two main drivers — technology and market. The cloud is starting to present a big opportunity. Other key areas include green technology and power management. Video will be driving a lot of traffic. The impact on the electronics industry will be new product development, with the IP having expanded beyond processor cores, an increase in collaborations and a changing EDA landscape — Cadence is investing on its decision to deliver the on the EDA360 vision.

Some of the recent highlights include Cadence’s new software development suite that addresses the hardware-software design gap, expansion of the Palladium XP, and releasing the industry’s first DDR4 solution, which includes controller, soft and hard PHY, drivers, verfication IP (VIP) memory models and signal integrity reference designs.

He spoke about horizontal collaborations such as app programing interface, and  vertical collaborations, which creates differentiation in the end markets. It also engages foundries in EDA, IP, etc. As an example, Tan spoke of Spreadtrum achieving one-pass silicon realization for the first 40nm product. Some other examples include Samsung designing and implementing 20nm product, ARM and Cadence collaborating on GHz implementation of Cortex-A15, and ARM, TSMC and Cadence collaborating on the industry’s first 20nm Cortex-A15.

Speaking on ‘Consumerization of IT’, Bhaskar Pramanik touched upon consumer trends driving IT. These trends include the economic system of computers, natural interaction, data explosion, social computing, pervasive displays, ubiquitous connectivity, and cloud computing.

According to him, computers will adapt to us. They will enable computing interfaces that are far more easier to use. The key business requirement is to balance the user expectations with the enterprise requirements.

Cadence: Plan verification to avoid mistakes!


Apurva Kalia

Apurva Kalia

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there’s verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence


Jaswinder Ahuja.

Jaswinder Ahuja.

Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.

The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.

At Cadence,  the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.

What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.

On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.
Read more…

Xilinx stays a generation ahead!


Tom Feist.

Tom Feist.

Today, the challenge is all about abstraction and putting automation around it. Productivity is automation and abstraction. Tom Feist, senior marketing director, Design Methodology Marketing, Xilinx said that the company’s strategy has been about All Programmable abstractions. He was speaking at the ongoing 13th Global Electronics Summit being held in Santa Cruz, USA.

Today’s hardware design abstractions include accelerated time to integration, abstracting hardware. For IP abstractions, Xilinx has introduced the IP integrator. It enables IP re-use and time to integration. The Vivado uses multiple plug-and-play IP. Vivado IP integrator is co-optimized for platforms and for silicon, respectively.

Vivado IP integrator has features such as correct-by-construction and automated IP systems. Vivado high-level synthesis allows C/C++ abstractions. Xilinx introduced the OpenCV library, accelerating smarter vision. It supports frame-level processing library for PS. It also supports pixel processing interfaces and basic functions for analytics.

Mathworks has model based abstraction. The automatic C and HDL code generation is supported from the same algorithmic level.

Hardware/software partitioning is supported for Zynq-7000 AP SoCs.  There are comprehensive video, motor control and signal processing IP libraries. There are automated workflows targeting Xilinx platforms.

Xilinx is also working with National Instruments. The automated C and HDL code generation is from the same graphical syntax in the LabVIEW IDE. It automatically generates a hardware implementation to meet requirements, abstracting Xilinx tool flow. There is a comprehensive software, hardware and I/O platform for creating control and monitoring systems.

Abstraction evolution has evolved to system level abstraction. It is abstracting all hardware through an increasing layer of automation.

All Programmable realization empowers software and systems engineers. There is a common compilation environment for heterogenous systems. It consumes C, C++ or OpenCL and libraries with user directives. There is automated flow — the user determines the program modules that run on various components.

The Vivado Design Suite 2013 abstractions with IP based design, C, C++, SystemC and OpenCV is new. Mathworks and National Instruments system level design abstractions with new levels of automation is emerging. Xilinx’s vision has been to empower the software and systems engineers by extending abstractions and automation.

Round-up 2011: Best of semiconductors


Right folks! This is the last post for 2011!! Here’s a look at the good, bad and ugly, that the year had to offer in semiconductors. Enjoy! ;) Happy new year, everyone!

Dec. 2011
Round-up 2011: Best of semiconductors

Video and mobility drivers for global semicon in 2012

Future materials and devices for power electronics

SuVolta solving power problem in SoCs across multiple CMOS process nodes

Global semiconductor industry keeps consolidating; 28nm will be stable: Dr. Wally Rhines

Synopsys acquires Magma! And, another one bites the dust!!

Nov. 2011
Lattice intros low power ECP4 FPGAs

Global semicon sales forecast at $329.4 billion for 2012! – What about this one? A well-read piece! ;)

MEMS Executive Congress 2011 round-up

Global semiconductor market will be $313 billion in 2012: SSIA – It seems 2012 will pan out this way! ;)

MEMS market overview: IHS iSuppli

NXP licenses Broadcom’s BroadR-Reach Ethernet technology for in-vehicle networking

MEMS devices driving healthcare apps!

Updated global semicon sales forecast 2011′s estimate falls $2.74 billion

Oct. 2011
DIT outlines initiatives to promote ESDM in India

Game changers: New paradigms for future of electronic product realization

Designing systems to thrive in disruptive trends!

Realizing EDA360: Charlie Huang, Cadence – Focus on EDA360! ;)

What’s happening with ISA and Indian semicon industry? – Defining piece! ;)

Altera launches SoC FPGAs

Emerging piezoMEMS apps and ion beam etch solutions for next gen MEMS and sensors

ESDM all over again? When will Indian semicon and electronics industries learn??

Semiconductor supply chain dynamics: Future Horizons @ IEF2011

Sep. 2011
India has restricted itself to only semicon design and R&D!

ST launches STM32 F4 series of MCUs

ARM connecting the world!

Renesas enhancing localization of products in India!

Magma announces Silicon One strategy

Need to work toward sustainable future: imec

Aug. 2011
Freescale launches first ‘base-station-on-chip’ products!

Semicon industry at inflection point of innovation: Rich Beyer

NXP launches CAN partial networking solution for automotives

Fabless fables and all that! Is India listening?

What’s happening with global semicon industry?

2011 global semicon sales growth likely to trend downward for rest of year? Read more…

Realizing EDA360: Charlie Huang, Cadence


Long-term trends are strong for semiconductor and electronics. According to databeans estimate (Feb. 2011), semiconductor revenue will likely reach $450 billion by 2015 and electronics revenuw will likely reach $2,800 billion by 2015.

Speaking at the CDNLive! 2011 event in Bangalore, India, Charlie Huang, SVP of Worldwide Field Operations, Cadence Design Systems Inc., said that the challenges in the near term are slowdown in Europe and USA. The weakness is driven by increasingly negative views on the global economy, end demand, orders and outlook. Key indicators are also showing that the economy is facing headwinds. The 2011 GDP growth projections have deteriorated since the beginning of the year. The economy has been marred by high unemployment and low consumer confidence.

As of now, innovation has been driving growth. Apps have been driving innovation, followed by video, mobility, cloud and green technology. The impact on the electronics industry is multi-fold. There is a new development paradigm and collaboration has been increasing. The IP is also expanding beyond cores and the EDA is changing.

Source: Cadence.

Source: Cadence.

The new development paradigm for system companies is to differentiate on applications and semiconductor companies must deliver on application-driven hardware-software platforms. IP has now expanded well beyond the core. EDA is also changing, and Cadence is investing to deliver on the EDA360 vision. There are multiple silicon realization challenges. Cadence silicon realization solutions enable fast, deterministic, end-to-end path to silicon success.

As an example, ARM and Cadence have collaborated on the GHz implementation of Cortex-A15. ARM chose ARM Artisan physical IP, evaluated the Cortex-A15 RTL, and supported CPF. Cadence optimized the EDA flow, experienced support at EAC, and provided EDA tool releases and iRM.

ARM, TSMC and Cadence also collaborated on the industry’s first 20nm Cortex-A15. TSMC provided the 20nm process qualification and A15 learnings. ARM handled the 20nm implementation experience, A15 considerations in 20nm and TSMC 20nm readiness milestone. Cadence provided the 20nm research to reality, contributed and grew the A15 expertise and TSMC 20nm readiness milestone.

The end result: the industry’s first 20nm Cortex-A15 tapeout, thanks to a successful three-way vertical collaboration. ARM, Cadence and TSMC engineers worked side-by-side. The project priorities included 20nm DPT implementation schedule and 20nm readiness milestone.
Read more…

Design-Lite — new model for semiconductor development: Taher Madraswala

November 16, 2010 1 comment

Taher Madraswala, VP of Engineering, Open-Silicon.

Taher Madraswala, VP of Engineering, Open-Silicon.

Taher Madraswala, VP of Engineering, Open-Silicon Inc., presented the guest keynote titled ‘Moving toward Design-Lite for Innovation’ this afternoon at the ongoing CDNLive India 2010. His mission is clear, “We want our customers to find newer ways of growing their markets.”

Madraswala first dwelt on the EDA360 vision and the rise of the applications platform. He discussed Design-Lite — a new model for semiconductor development, as well as how companies should be using derivaties to extend their market reach, and the new design derivative ecosystem.

On EDA360, he said that the semiconductor product value is now shifting to applications. The shift is providing applications focused platforms. There are also evolving integration challenges in both software and IP.

He added that non-traditional semiconductor development tasks are being pushed to the ecosystem. In this regard, the ecosystem collaboration is critical for success.

He said: “Buying an IP is one thing, but putting it together to develop a product that can be of mass usage is quite another. There was a time when we could add value in doing faster chips, etc. Now, the values have moved elsewhere. Customers also want to change the way they deliver value.”

Madraswala presented the example of Brite Semiiconductor. Open-Silicon had founded Brite in 2008 to brring its methodology to the Chinese market. Yesterday (15/11),  Semiconductor Manufacturing International Corp. (SMIC) announced that it has acquired an equity stake in Brite.

Introducing Design-Lite
Today’s global economy develops complex systems in a new manner, with design visionaries partnered with subsystem experts and uniquely skilled system integrators. Further, globalization has created the mechanism to optimize every piece of semicon design. Read more…

Industry should enable key capabilities of EDA360: John Bruggeman

November 16, 2010 2 comments

John Bruggeman, CMO, Cadence Design Systems.

John Bruggeman, CMO, Cadence Design Systems.

Delivering his keynote at the ongoing CDNLive India 2010, John Bruggeman, CMO, Cadence Design Systems, said: “Everything is changing very rapidly in the way you never expected. That was Lip-Bu’s comment. Cadence’s EDA360 is a vision for the industry. EDA360 is a vision — a transformation is underway. This isn’t a vision for Cadence or marketing, but for the entire industry.”

According to him, the semiconductor and EDA industries have new and complex problems, and there is a growing need to come together to solve those problems.

Application driven model rules
Touching on application driven models, Bruggeman gave an example of his new TV, which came preloaded with eight applications, such as YouTube, Pandora, NetFlix, etc.

Interestingly, there was also a link within the TV on to the application store where one could buy up to 200 additional applications.

“This is very important – it is at the heart of the fundamental sea change that is happeing in the industry,” he said. “Users want apps. They want to take their devices and want to be able to cusomize those into doing things they are most interested in. Users want their devices to have apps and content that they can customize.”

The fact that one can link to an app store – from either a washing machine or a toaster — that’s the seminal shift!

He added: “The life expantancy of a TV set in North America is 15.1 years. Wouldn’t it be better if I got revenue once every month, or week or day? An application driven model means a continuous revenue model!” Read more…

Semicon industry must be prepared to face challenges in new era: Lip-Bu Tan


Day 1, CDNLive India 2010, kicked of with Lip-Bu Tan, president and CEO, Cadence Design Systems Inc. delivering the main keynote.

Lip-Bu Tan, president and CEO, Cadence Design Systems Inc.

Lip-Bu Tan, president and CEO, Cadence Design Systems Inc.

This is a new era of an application driven platforms and products that have very short time to market. The global semiconductor industry needs to be ready and prepared to face and take on the upcoming challenges.

Talking about the global economy in general, Tan said that there has been gradual GDP growth, and that the semiconductor growth has exceeded GDP growth this year.

Healthy semicon industry
Tan said: “There is cautious investment as well as government engagement. There have been seasonal adjustments in the industry. I see 5-7 percent growth over the next five years. It is a healthy semiconductor industry.”

There has also been some improvement in major capital investment, especially in China and India. The IPO market has also been encouraging, especially in semicon space.

He added that India, especially, is coming up very strong. The domestic market has been coming up quite strong as well. “I am excited about the whole of investment over the next five years.”

Tan advised that various national governments are realizing that the semiconductor is critical, and hence, it is now becoming a significant industry. “China realized that they import more semiconductors than oil. India will realize this fact sooner, rather than later. I am sure that India will also mark semiconductors as a key area.”

On globalization, he added that all companies were now moving toward globalization. Some major companies, such as TI, ST, etc., have experienced tremendous growth in Asia Pacific.

On organizational matters, Tan expressed excitement regarding the amount of innovation and IT education happening in India. “India has all the brains and innovation. Now, the challenge is how to come up with products and market them globally. Tejas is doing very well, so is Cosmic Circiuts. So is Ittiam Systems.” The capital efficiency structure is also gaining in importance.

According to him, the M&A activity is also gaining in importance. “Some of the major system companies are moving into semiconductors, such as Apple,” he observed. A similar pattern was also visible with Oracle. “So, the system guys are starting to move into silicon. The next five years will be exciting as there will be a sea change. Read more…

EDA360 unplugged with Cadence’s Jaswinder Ahuja


Jaswinder Ahuja, corporate VP & MD, Cadence Design Systems (I) Pvt Ltd.

Jaswinder Ahuja, corporate VP & MD, Cadence Design Systems (I) Pvt Ltd.

Following the announcement of the EDA360 last week, I managed to get in touch with Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems (I) Pvt Ltd. We discussed a variety of topics such as why the EDA industry is at the crossroads, EDA360 unplugged, the integrators vs. creators concept, the IP stack and the road ahead for EDA360.

First, why is the EDA industry at the crossroads?

According to Ahuja, if you look at the evolution in the electronic design world, systems companies are finding differentiation and value through the creative, innovative applications or “apps” that are being demanded by end consumers. This is true not only in the mobile handset world, where iPhone and Android are obvious examples, but anywhere there’s a processor. Therefore, software is becoming a very important part in the scheme of things.

“Semiconductor companies are being asked by system companies to provide the hardware platform as well as the software that will run on that particular platform. That is the trend that Cadence is seeing today, and that is what is discussed in the EDA360 manifesto,” he added.

EDA is at crossroads because EDA companies can no longer provide the tools only for IP integration and silicon realization like they have been doing all these years. EDA now has to encompass SOC realization (including bare metal software) and then move towards system realization, which includes mechanical/board design, he noted.

EDA360 and its key features

As mentioned earlier, the EDA 360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.

Ahuja said that EDA360 represents System Realization, the development of a complete hardware/software platform ready for applications development; SoC Realization, the creation of a single SoC including hardware-dependent software; and Silicon Realization, which includes complex digital, analog, and mixed-signal designs.

The traditional approach to system development starts with the hardware, and appends the software and the applications later. With application-driven System Realization, designers start by envisioning the applications that will run on the system, define requirements, and then work their way down to hardware and software IP creation and integration. This flow requires some new and expanded capabilities.

Part of system realization is project management. EDA360 reaches beyond engineering teams to help customers meet project and business objectives.

Key features of EDA360 include:

* Outlining how companies can bridge the profitability gap, not just the productivity gap.
* Explaining the shifts to integration and profitability.
* Software aware SoC realization, which includes an integrated, optimized IP stack.

The four chapters of the EDA360 manifesto take a look at:

Chapter 1: EDA Industry Focus Shifts to Integration and Profitability.
Chapter 2: Application-Driven System Realization.
Chapter 3: Software-Aware SoC Realization.
Chapter 4: EDA360 Enables Silicon Realization. Read more…
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