SEMICON Europa was recently held in Dresden, Germany on Oct. 8-10, 2013. I am extremely grateful to Malcolm Penn, chairman and CEO, Future Horizons for sharing this information with me.
SEMICON Europa included a supplier exhibition where quite a few 450mm wafers were on display. One highlight was a working 450mm FOUP load/unload mechanism, albeit from a Japanese manufacturer. These exhibits did illustrate though that 450mm is for real and no longer a paper exercise. There was also a day-long conference dedicated to 450mm in the largest room. This was crowded throughout the time and a large number of papers were given.
Paul Farrar of G450C began with a presentation about Supply Chain Collaboration for 450mm. His key message was there are 25 different tools delivered to G450C of which 15 are installed in the NFN cleanroom. This number will grow to 42 onsite and 19 offsite by Q1 2015.
He stated that Nikon aims to have a working 193i litho machine in 2H 2014 and install one in Albany in 1H 2015. Farrar also reported a great improvement in wafer quality which now exceed the expected M76 specification, and prime wafers to the M1 spec should be available in Q3 2014. There has also been good progress on wafer reclaim and it is hoped some wafers can be reused up to 10 times, although at least three is the target.
Metrology seems to be one of the most advanced areas with eight different machines already operational. The number of 450mm wafers in their inventory now stands at over 10,000 with these moving between the partners more rapidly. It was immediately noticeable from Farrar’s speech that G450C is now recognising the major contribution Europe is making to 450mm and is looking for more collaborations.
Facilities part of F450C
Peter Csatary of M&W then dealt with the facilities part of G450C, known as F450C. This group consists of:
• M&W (co-ordination)
• Mega Fluid Systems
• Haws Corp.
• Air Liquide
• Ceres Technlogies
• CS Clean Systems
F450C is seen as streamlining communications with the semiconductor companies and their process tool suppliers. The group will focus on four key areas, namely Environmental Footprint, Facility Interface Requirements, Cost and Duration, and Safety and Sustainability.
One interesting point raised was that 450mm equipment is inherently more massive and one suggestion has been that ceiling mounted cranes will be required to install and remove equipment. This of course means that fab roofs would need to be stronger than previously. This topic was discussed at the latest F450C meeting subsequent to this conference.
Another new concept is that of a few standardised 3D templates and adapter plates to allow fab services to be pre-installed before the equipment is placed. An interesting point made elsewhere by M&W is that the current preference is to place a fab where there are already other fabs in existence so that the infrastructure to transport products, materials and services is already in place, as are basic utilities such as power, natural gas and water supply.
However, the scale of the expected utility demand at 450 mm ups the stakes as for example a large 300 mm facility uses about 4 million gallons of water per day, whereas a 450 mm fab will use almost double that, putting immense strain on a location’s infrastructure should there be other fabs in the region. This could affect future site selections.
An outcome of this phenomenon is that the reduction, reclaim and re-use of materials will no longer be driven only by the desire to be a good corporate citizen, but will also be driven by cost control and to ensure availability of required resources such as power, water, specialty gases and chemicals.
The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:
Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.
Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.
Now, this is excellent news for everyone interested in the Indian semiconductor industry.
One look at the numbers above tell me – NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let’s examine!
As you can probably see, both the projects have placed 22nm right at the very last phase! That’s very interesting!
Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel’s Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!
For discussion’s sake, let’s say, a fab in India comes up by say, early 2015. Let’s assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn’t it? Where will the rest of the global industry be by then?
You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members. What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE’s Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY’s College of Nanoscale Science and Engineering!
So, what does all of this tell me?
One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space! Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!
Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop!
Perhaps, these product lines will be good for India and serve well, for now, but not for long!
San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.
I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”
There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.
Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.
How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.
“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”
How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.
On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.
Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth. Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry. At a macro level, the consumer sector will drive a lot of the growth ahead. For EDA, the higher levels of abstraction is where the growth will be.”
POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in integrated circuits, by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost.
POET’s current IP portfolio includes more than 34 patents and seven pending. POET’s core principles have been in development by director and chief scientist, Dr. Geoff Taylor, and his team at the University of Connecticut for the past 18 years, and are now nearing readiness for commercialization opportunities. It recently managed to successfully integrate optics and electronics onto one monolithic chip.
Elaborating, Dr. Geoff Taylor, said: “POET stands for Planar Opto Electronic Technology. The POET platform is a patented semiconductor fabrication process, which provides integrated circuit devices containing both electronic and optical elements on a single chip. This has significant advantages over today’s solutions in terms of density, reliability and power, at a lower cost.
“POET removes the need for retooling, while providing lower costs, power savings and increased reliability. For example, an optoelectronic device using POET technology can achieve estimated cost savings back to the manufacturer of 80 percent compared to the hybrid silicon devices that are widely used today.
“The POET platform is a flexible one that can be applied to virtually any market, including memory, digital/mobile, sensor/laser and electro-optical, among many others. The platform uses two compounds – gallium and arsenide – that will allow semiconductor manufacturers to make microchips that are faster and more energy efficient than current silicon devices, and less expensive to produce.
“The core POET research and development team has spent more than 20 years on components of the platform, including 32 patents (and six patents pending).”
Moore’s Law to end next decade?
Is silicon dead and how much more there is to Moore’s Law?
According to Dr. Taylor, POET Technologies’ view is that Moore’s Law could come to an end within the next decade, particularly as semiconductor companies have recently highlighted difficulties in transitioning to the next generation of chipsets, or can only see two to three generations ahead.
Transistor density and its impact on product cost has been the traditional guideline for advancing computer technology because density has been accomplished by device shrinkage translating to performance improvement. Moore’s Law begins to fail when performance improvement translates less and less to device shrinkage – and this is occurring now at an increasing rate.
He added: “For POET Technologies, however, the question to answer is not when Moore’s Law will end – but what next. Rather than focus on how many more years we can expect Moore’s Law to last – or pinpoint a specific stumbling block to achieving the next generation of chipsets, POET looks at the opportunities for new developments and solutions to continue advancements in computing.
“So, for POET Technologies, we’re focusing less on existing integrated circuit materials and processes and more towards a different track with significant future runway. Our platform is a patented semiconductor fabrication process, which concentrates on delivering increases in performance at lower cost – and meets ongoing consumer appetites for faster, smaller and more power efficient computing.”
The Global 450mm Consortium (G450C) has been driving the effective industry 450mm development. It is co-ordinating test wafer capability supporting development and demonstrating unit process tool performance. The focus is now on improving tools with suppliers to be ready for customer operations.
Giving an update during the recently held Semicon West 2013 at San Francisco, USA, Paul Ferrer, GM, G450C, said that if one looks at the G450C lithography tool roadmap, by 1H-2014, the 300mm coupon, 450mm directed self-assembly and 450mm imprint will be completed. From 2H-2014 to 1H-2015, there will be 193i patterning service at Nikon’s site. Nikon 193i move-in will take place from 1H-2015 to 2H-2016.
Suppliers are developing the 450mm tool set with 10 tools per quarter being delivered to G450C, the global consortium for 450mm fabs. Significant progress has been made in wafer quality and wafer reclaim is almost ready. Automation and carriers are working, and suppliers are co-operating on the key initiatives. Global collaboration is said to be picking up steam.
In the NFX cleanroom, the 450mm OHT is ready for inter-fab transfer. There are nine tools in-fab — two metro, three process, and four stocker, respectively. There will be seven ODD 3Q2013, and 10 tools ODD 4Q2013, respectively.
As for 450mm notchless wafer activities, the key technical results include the backside fiducial marks that have achieved the desired accuracy (3σ = 0.5μm) using existing camera technology. There are design rules of fiducial marks, such as multiple locations (≤ 4) for robustness and speed, different patterns at multiple locations, and off crystal plane, fewer dots and shallower dots to minimize the Si crystal damage.
As for program highlights, there are collected designs from G450C member companies, tool suppliers, and optical detection suppliers. Also, there has been delivery of 300mm test wafers with fiducial marks. G450C has co-ordinated test wafer plans with suppliers. Further, for 450mm silicon wafer readiness, notchless wafers are technically achievable now.
The G450C members include CNSE/Research Foundation, GLOBALFOUNDRIES, Intel, IBM, Samsung and TSMC.
300mm is the new 200mm, said GlobalFoundries’ David Duke, during a presentation titled ‘Used Equipment Market’ at the recently held Semicon West 2013 in San Francisco, USA. Used semiconductor equipment sourcing and sales is a very interesting challenge.
Qimonda, Spansion, Powerchip and ProMOS had jumpstarted the market. Now, there is a broadening user base. There is an unexpected uptake by analog and power device producers to achieve economies of scale. There has been legacy logic scaling. Also, the 200mm fabs are being upgraded to 300mm with used equipment. Many 300mm tools can “bridge” to 200mm easily.
Parts tools are seeding the ecosystem. Third parties are also able to support refurb as well as tool moves. However, we need more! Software licensing is becoming a smaller hurdle. There has been no over-supply yet!
So, what are the ‘rough’ rules of thumb for 300mm? First, there are approximately 1,500 individual tools in the open market. Few sellers know the values as the market is still developing. Twenty percent of the transactions drive 80 percent of sales. Today, the number of 300mm buyers is around 1/10th the number of 200mm buyers!
Lithography has been the biggest difference. Leading edge DRAM is far more expensive in lithography. Lithography has seen the most dramatic financial effects with explosive pricing in technology (immersion) and the need for capacity (two-three critical passes vs. one with dual/triple gate patterning. As of now, financial shocks and bankruptcies are the main drivers for used 300mm.
Next, 200mm is now the new 150mm! The 200mm OEM support is starting to dry up. It is nearly impossible to compete in productivity vs. 300mm. Oversupply is causing values to stay suppressed. The only bright spot being: there is still strong demand for complete fabs. The 200mm market split is roughly by 40 percent Asia and 60 percent rest of the world.
So, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV.
That brings me to India! What are they doing about fabs over here? This article has enough pointers as to what should be done. Otherwise, the world is already moving to 450mm fabs! Am I right?
SEMI, USA recently hosted the seminar on ‘Convergence of PV Materials, Test and Reliability: What Really Matters?
Reliability in growing PV industry
Speaking on the importance of reliability to a growing PV industry, Sarah Kurtz, principal scientist, Reliability group manager, NREL, said that confidence in long-term performance is a necessity in the PV industry. Current failure rates are low. There is need to demonstrate confidence so that failure rates will stay low. There has been exponential growth of the PV industry so far. PV is a significant fraction of new installations. It now represents a significant fraction of new electricity generating installations of all kinds.
How does one predict the lifetime of PV modules? There has been a qualification test evolution for JPL block buys. Most studies of c-Si modules show module failures are small. Internal electrical current issues often dominate.
The vast majority of installations show very low PV module failure rates (often less than 0.1 percent). There has been evidence that PV is low risk compared to other investments. To sustain the current installation rate, we need to demonstrate confidence that justifies the annual investment of $100 million or so.
Critical factors in economic viability of PV
DuPont has broad capabilities under one roof. It offers materials, solar cell design, and processes integrated with panel engineering. Speaking about Critical factors in economic viability of PV – materials matter – Conrad Burke, global marketing director, DuPont PV Solutions, said that material suppliers have a distinct advantage to view trends. The industry can expect consolidation among large PV module producers and large materials suppliers.
There is an increasing dependence on materials suppliers for processes, tech support and roadmap. There is renewed attention to long-term reliability and quality of materials in PV products.
There is a race for survival among panel producers. There are dropping prices for solar panels, and quality is getting compromised. There are reduced incentives in established markets. The market will continue to grow. Key factors that determine investment return for PV include lifetime, efficiency and cost.
When materials fail, the consequences are dire. There are failures such as encapsulant discoloration, backsheet failure, glass delamination, etc. Average defect rates in new-build modules has been increasing. Significant number of PV installations do not deliver the projected RoI. The system lifetime is as important as cost and incentives.
Solar cell power continues to improve. There have been improvements from metal pastes and processes. Performance loss impacts the RoI. The US Department of Energy hired JPL to develop 30-year PV modules. Recent cost pressures have led to the dramatic changes in module materials and a lack of transparency.
Analyzing modules from the recent service environments show performance issues. Certification does not mitigate risk. Tests do not predict the actual field performance. He showed tier-1 solar panel manufacturing problems from China, Japan and the USA. Backsheet is critical to protect solar panels. Few materials have lengthy field experience. We will continue to see drop in prices for solar panels and opening of new markets. Focus for PV module makers will remain efficiency, etc.
Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.
This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.
It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.
In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.
Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.
The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:
Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.
Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.
Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.
A team of scientists at the Massachusetts Institute of Technology (MIT), comprising principally of Dr. Ishan Barman, Dr. Narahara Chari Dingari and Dr. Jaqueline Soares, and their clinical collaborators at University Hospitals, Cleveland have developed the Raman scattering-based concomitant diagnosis of breast cancer lesions and related micro-calcifications.
Let’s find out more about this new breast cancer research done by the team at MIT.
Early detection necessary!
According to MIT, one in eight women in the US will suffer from breast cancer in her lifetime and breast cancer is the second leading cause of cancer death in women. Worldwide, breast cancer accounts for 22.9 percent of all cancers (excluding non-melanoma skin cancers) in women. In 2008, breast cancer caused 458,503 deaths worldwide (13.7 percent of cancer deaths in women).
Therefore, technological advancements for its early detection and subsequent treatment can make a significant impact by preventing patient morbidity and mortality and reducing healthcare costs, and are thus of utmost importance to society. Currently, mammography followed by stereotactic breast biopsy serves as the most promising route for screening and early detection of cancer lesions.
Nearly 1.6 million breast biopsies are performed and roughly 250,000 new breast cancers are diagnosed in the US each year. One of the most frequent reasons for breast biopsy is microcalcifications seen on screening mammography, the initial step in early detection of breast cancer. Microcalcifications are micron-scale deposits of calcium minerals in breast tissue that are considered one of the early mammographic signs of breast cancer and are, therefore, a target for stereotactic breast needle biopsy.
However, despite stereotactic guidance, needle biopsy fails to retrieve microcalcifications in one of five breast biopsy patients. In such cases, the resulting breast biopsies are either non-diagnostic or false-negative, thereby, placing the patient at risk and potentially necessitating a repeat biopsy, often as a surgical procedure.
There is an unmet clinical need for a tool to detect microcalcifications in real time and provide feedback to the radiologist during the stereotactic needle biopsy procedure as to whether the microcalcifications seen on mammography will be retrieved or the needle should be re-positioned, without the need to wait for a confirmatory specimen radiograph.
Such a tool could enable more efficient retrieval of microcalcifications, which would, in turn, minimize the number of x-rays and tissue cores required to achieve a diagnostic biopsy, shorten procedure time, reduce patient anxiety, distress and discomfort, prevent complications such as bleeding into the biopsy site seen after multiple biopsy passes and ultimately reduce the morbidity and mortality associated with non-diagnostic and false-negative biopsies and the need for follow up surgical biopsy.
If 200,000 repeat biopsies were avoided, at a cost of $5,000 per biopsy (a conservative estimate and would be much higher for surgical biopsies), a billion dollars per year can be saved by the US healthcare system. The MIT Laser Biomedical Research Center, has recently performed pioneering studies to address this need by proposing, developing and validating Raman and diffuse reflectance spectroscopy as powerful guidance tools, due to their ability to provide exquisite molecular information with minimal perturbation.
Specifics of the technique
Stating the specifics of the technique developed by MIT, the team said that their research focuses on the development of Raman spectroscopy as a clinical tool for the real time diagnosis of breast cancer at the patient bedside. “We report for the first time development of a novel Raman spectroscopy algorithm to simultaneously determine microcalcification status and diagnose the underlying breast lesion, in real time, during stereotactic breast core needle biopsy procedures.”
In this study, Raman spectra were obtained ex vivo from fresh stereotactic breast needle biopsies using a compact clinical Raman system, modeled and analyzed using support vector machines to develop a single-step, Raman spectroscopy based diagnostic algorithm to distinguish normal breast tissue, fibrocystic change, fibroadenoma and breast cancer, with and without microcalcifications.
The developed decision algorithm exhibits a positive and negative predictive value of 100 percent and 96 percent, respectively, for the diagnosis of breast cancer with or without microcalcifications in the clinical dataset of nearly 50 patients.
Significantly, the majority of breast cancers diagnosed using this Raman algorithm are ductal carcinoma in situ (DCIS), the most common lesion associated with microcalcifications, which has classically presented considerable diagnostic challenges.
This study demonstrates the potential of Raman spectroscopy to provide real-time feedback to radiologists during stereotactic breast needle biopsy procedures, reducing non-diagnostic and false negative biopsies. Indeed, the proposed approach lends itself to facile assembly of a side-viewing probe that could be inserted into the central channel of the biopsy needle for intermittent acquisition of the spectra, which would, in turn, reveal whether or not the tissue to be biopsied contains the targeted microcalcifications.
Exar Corp., established 1971, is headquartered in Fremont, USA, and has design centers in Silicon Valley and Hangzhou, China. Louis DiNardo, president and CEO, Exar, said that the company’s strategic model is to serve high-growth markets with innovative value-added solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.
Exar offers solutions that includes high performance analog-mixed signal as well as data management solutions. Its current market focus is on networking and storage, industrial and embedded systems, and communications infrastructure. It is focusing on power management products, connectivity products and data management solutions.
Power management products include those for analog power management such as switching regulators, switching controllers, linear regulators, supervisory controllers, etc, For programmable power, Exar focuses on multiple output synchronous buck controllers.
Some of the products include POWER, the Exar Programmable PowerSuite 5.0. Recently, Calceda has been powering servers with the PowerXR technology.
For data compression and security, Exar is offering hardware acceleration and software solutions meant for compression and decompression, acceleration, encryption and decryption. There are high growth markets supporting social networking, industrial Internet and financial technology as well.
Exar’s Panther I is a first generation compression/security engine with the PCIe interface. The Panther II is a second generation compression and security engine with PCIe and FPGA interface.