As per James Stansberry, VP & GM Broadcast Products, Silicon Labs, there was the emergence of CMOS RF design in late 1990s. He was speaking at the Globalpress Electronics Summit 2013, being held in Santa Cruz, the US.
CMOS strengths can be maximised in low-cost/high-volume wafer processing, low-power and high density logic that scales with lithography, and switched device architectures enable high-performance ADCs and DACs. Large RAM arrays and NVM are also available.
CMOS weaknesses can be minimized if the noise level at given current (1/f noise), there are low Q integrated inductors, Ft still lags SiGe and GaAs at same power level, and there is lower dynamic range with shriking supply voltages.
There are design LNAs, mixers, VCOs, PLLs and ADCs to compensate for CMOS constraints. It is recommended to use digital logic to detect and correct RF and baseband performance deficiencies. Optimizing a CMOS receiver means to design for cost without power or performance compromise and leverage digital signal processing to optimize RF.
Silicon Labs’ multiband radio receiver solution allows the power of integration. It leads to over 80 percent BoM savings. No manual alignment is required. There is minimal rework and superior RF performance. The BoM cost = -$0.10. Silicon Labs will be introducing the Si468x FM digital radio next week.
Advancing digital radio market
The software-defined radio (SDR) is to support multiple digital radio standards. It also supports worldwide analog FM and RDS/RBDS. It is compatible with iBiquity and NRSC-5 standards for FM digital radio and also compatible with Eureka 147 DAB/DAB+.
It is flexible and cost effective, as the radio-on-a-chip solution is available in WLCSP and QFN packages. It supports module or on-board designs. Silicon Labs is looking to broadening digital radio penetration. It can be seen in handheld clock and tabletop radios and clocks, mobile phones, tablets, PMPs and PNDs, and boom boxes and mini/micro systems.
Magma Design Automation has introduced the Silicon One technology solutions for Magma users in India. This was announced by Rajeev Madhavan, chairman and CEO, Magma, on the sidelines of the MUSIC 2011 in Bangalore, India, this afternoon.
Silicon One aims at making silicon profitable, especially for Magma’s customers. It is a presentation of innovative solutions for advanced analog and digital design challenges. Magma outlined five technologies: Talus, Tekton, Titan, FineSim and Excalibur. The solutions work off a unified database for designing chips that combine analog, digital, memory, etc. Just about a week ago, Magma launched the global Silicon One seminar series in the US, Canada, Korea, China, Taiwan, Japan, Israel and Europe, from Sept. 20 to Nov. 10.
“We are making solutions that customers can use. The global EDA industry is currently worth $4.5-$5 billion today, growing at a rate of 10 percent.” As of now, 21 of the top 25 customers use Magma tools. It happens to be key EDA supplier to some household names in wireless.
Magma currently employs 696 people, of whom 77 percent are in application engineering or R&D. India has 220 (32 percent) employees as of now.
According to Madhavan, Silicon One is a platform of EDA solutions for emerging silicon. The three main pillars are: integration — with a unified data model comprising capacity, concurrent optimization and chip finishing; completeness — comprising full flow IP characterization, design implementation and design verification; and throughput — comprising concurrent analysis and verification.
Magma has built three categories of solutions. These are:
SoC/ASSP: Building killer applications with an entire SoC.
AMS: Building analog mixed signal chips for mobility market.
Memory: Building high-speed memory chips for consumer applications.
Madhavan added: “We are mapping Silicon One solutions to the market. We are touching every single point of the silicon. We are providing a series for platforms — such as digital design (Talus), analog verification (FineSim), analog design (Titan), digital sign-off (Tekton) and yield management (Excalibur). We have the opportunity to be a dominant yield management company.”
Recently, I received an update on Kotura’s latest initiatives in silicon photonics.
The transition from copper to optics is underway and promises to deliver data at the speed of light – not just through fiber optic cables but on computer chips. Leading this movement is silicon photonics innovator Kotura.
Kotura is headquartered in Monterey Park, CA with its own silicon CMOS fab and many resident PhDs. It has an extensive IP portfolio and over 60 granted patents. While the initial adoption of silicon photonics has been largely in the telecommunications industry, Kotura is taking its unique platform that integrates optics and electronics to broader markets that are seeking greater performance, bandwidth and energy efficiency.
Data centers, for instance, are being driven to provide more bandwidth at high performance levels and are consuming huge amounts of energy. Optical interconnect in data center networks promises relief to an industry that is destined for continued growth.
One of Kotura’s strengths, and a key to advancing its technology and speed- and energy-saving applications, has been a robust R&D program, funded by a mix of private industry and Federal Government sources such as the Defense Advanced Research Projects Agency (DARPA) and the Departments of Commerce (NIST) and Energy.
As for the market drivers, a variety of markets currently use silicon photonics. The telecom industry was an early adopter of the technology and has implemented it with great success. Now there is a movement to expand silicon photonics to other applications that require high bandwidth density, low power and small footprint connectivity. Data server farms, electric smart grid, supercomputing, and sensors for infrastructure are just a sampling of the applications that are well suited to benefit from silicon photonics.
Kotura has many partners in both the public and private sector, including several universities and departments of the US government.
Kotura maintains strong ties to a variety of associations including 10x10msa, CIAN, MIT Roadmapping, Optoelectronics Industry Development Association (OIDA), OSA, IEEE 802.3ba 40 Gb/s and 100 Gb/s Ethernet Standards Committee, Video Electronics Standards Association (VESA) and Silicon Photonics Alliance.
This is excellent news for all concerned. Silicon photonics is the way forward!
Xilinx Inc. announced the industry’s first stacked silicon interconnect technology. It proposes to deliver breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.
3D packaging approach
Xilinx has taken a 3D packaging approach that makes use of passive silicon-based interposers, microbumps and through-silicon vias (TSV) to deliver multi-die programmable platforms. As the interposer is passive, it does not dissipate any heat beyond what’s consumed by an FPGA die.
The stacked silicon interconnect technology offers 2X FPGA capacity advantage at each process node. It is a core part of Virtex-7 family. Also, the stacked silicon interconnect technology is supported by standard design flows.
Xilinx has been accelerating FPGA transition to the heart of the system. David L. Myron, senior manager, High Volume Products, Product and Solutions Management, Xilinx, revealed that a lot of Xilinx’s customers are doing FPGA starts rather than ASIC starts as that seems more viable. Customers are now asking for much more — over 2X today’s logic capacity, many more high-speed serial transceivers as well as processing elements, as well as much more internal memory to store data. “The challenge is delivering ‘more than Moore’,” he said.
Myron cited certain challenges. These include availability and capability — the largest FPGAs are only viable later in the life cycle. Power and bandwidth pose additional challeges. The traditional mitigation techniques are no longer adequate. “One of the trends we have seen is that while gate count has gone up at a certain rate, the I/Os have not,” he added. Hence, innovation is the need of the hour to meet capacity requirements.
The stacked silicon interconnect technology is addressing all of these challenges, meeting the needs of high bandwidth, low latency and low power. This Xilinx innovation offers massive number of low latency, die-to-die connections. Besides, there is no wasted I/O power.
For applications requiring high-transistor and logic density for high levels of computational and bandwidth performance, these 28nm platforms will deliver significantly higher capacities, resources and power savings than possible in a monolithic die approach. Read more…
Friends, is there a case for polysilicon manufacturing in India? Would like to hear from you!
This post is based on a discussion at Solarcon India 2010 on polysilicon manufacturing in India by Alok Nigam of Lanco Solar.
According to Nigam, there is considerable polysilicon market potential in India. The inevitable dependance on other Asian countries in the absence of any sort of domestic capacity will only worsen the balance of payments (BoP) situation.
Upstream integration will help derisk business. Even in the absence of policy (JN-NSM) support, the impact on system cost will be marginal.
Now, as per the current manufacturing trends, polysilicon production remains concentrated with the top six players holding 70-80 percent of market share and new, large players emerging in China.
Technology has also enabled cost improvements across value chains — such as increasing furnace/reactor size, use of diamond wire for slicing, efficiency gain in cells, economy of scale in modules, etc. More incremental capacity is said to be coming up in Asia, which includes players such as SunPower, MEMC, First Solar, etc. Read more…
Now then, this will make a very interesting read! Back in October 2007, I had discussed the timing and the need for a silicon wafer fab in India, in-depth, with Anil Gupta, managing director, India Operations, ARM.
We have come a long way since then! There was all the hype last year about SemIndia’s fab, which never really did happen, and eventually, BV Naidu moved on! Then came the rush to solar fabs. Recently, when I blogged on how a Qimonda buy could be good for India, I am told that it is really outrageous. No problem, it is merely a suggestion.
At times, I have got the feeling whether the Indian semiconductor industry is losing its way! However, when I see all around, it is hale and hearty, and business as usual — fabs or no fabs!
It was interesting to meet up again with Anil Gupta of ARM, and to find out what he thought about what I thought!
Starting with an old question, whether India has the capability to sustain or even build a product development ecosystem? Gupta said: “We need the following for this:
* Entrepreneurs committed to product development and willing to take that risk.
* Investors willing to take risk on product development companies.
* Consumption (this will happen as the economy improves any way).
* Deep enough technical/technological knowledge/know-how to put reasonably competent end products together (It exists. Examples like Sukam, Tejas and other are there).
Indian fab story dead and buried
Turning focus on fabs, is the Indian silicon wafer fab story completely dead and buried now? Gupta notes: “When TSMC says they are running at only 38 percent capacity, one can imagine what the rest of the fabs must be going through. In any case, the Indian fab story was a longer term story and the current economic climate actually makes it further and further remote. So yes, it is dead and buried now!”
Wow! India probably flattered to deceive! However, I am an optimist, and hope that one day, India will have its own silicon wafer fabs!
Gupta adds: “What worries me now is the glut of the solar/PV fabs. By the industry estimates, solar/PV is a viable option only when the price of oil is >$100 per barrel (oil is at $40 per barrel now). This means, there would be challenges for the solar cell industry too! One can only hope that the economy picks up growth soon enough and sends the price of oil higher so that solar becomes a viable option.”
Again, this is a concern I have as well. The rush toward solar is good, but then, is this what the Indian semiconductor industry really needs? Where’s all that talk of developing silicon and product companies? You simply cannot equate the two — semicon and solar! You can’t have a policy, and then ignore the main crux either, and simply go for the ones that are easily attainable! It does not project a good impression, or maybe, I am somehow wrong in my assessment. Hence, my feeling that the industry could be losing its way somewhere!
However, Gupta feels that’s not really the case! What has been working until now, still continues to work!! “Our strengths are design and verification. We will continue to be in demand for that. The other pastures we explore, there are a lot of uncertainties,” he adds.
“The challenge is to pick the right pasture where the grass remains green even in the summer. This is not easy to find and does require that we bet on some of them and learn through the experience,” he advises.
How can India really buzz?
What now needs to be done to get the semiconductor industry in India really buzzing? Surely, local consumption is key. Local consumption would hopefully foster electronic product innovation just like products by two-wheeler manufacturers and the Tata Nano.
“The current initiatives in the industry for rural applications are also quite interesting. I am optimistic that some good offerings will come out of this. While these may not be specifically from a “semiconductor” perspective, at least at the “system” level these would make sense,” says Gupta.
What India NOW offers to semicon world?
What does India NOW offer to the semicon world, in these times of a global recession?
The Indian economy is still mostly internal consumption oriented, as opposed to exports oriented. This is very different from the economies of island nations like Taiwan, Korea, and Japan, which are very heavily export oriented.
In a recession like the current one, these predominantly export-oriented economies experience a far greater crunch than the others. Thus, as long as products are being sold in Indian markets at the right price points, there would be consumption.
Gupta says, “This time around, the world would come out of recession mainly driven by Asian countries, India being one. People in the industry that I talk to tell me that as the worst is over in this crisis, and as things begin to pick up, India will once again be the beneficiary of a lot of work moving here. However, my personal view is somewhat different.
“I believe that the last round did witness this phenomenon mainly because it was the honeymoon period. But by now, the honeymoon period is over and the India centres of these companies are working hard to reach a level where they become “mission critical” to the businesses of their companies.
“The journey hasn’t been very easy for multiple reasons. And by now, the cost differentials also do not look as attractive as they did before. Hence, what work comes here would come only after a careful assessment and very selectively (not by leap of faith).”
I did blog about how Qimonda could be a good buy for starting a memory fab in India. You have all the facts in front of you! My question to the Indian semiconductor industry is: should we revive the call for having a silicon wafer fab in India, post SemIndia and post recession?
Cadence Design Systems Inc. recently announced its C-to-Silicon Compiler, said to be the next-generation of HLS (high-level synthesis) technology.
The C-to-Silicon Compiler is said to eliminate historical barriers to HLS adoption to deliver the quality of results and net productivity gains engineers need. It also produces RTL (register transfer level) with quality at or above the 90th percentile of manual RTL design, while increasing the engineering productivity up to 10X. HLS incidentally, reduces the manual effort required to produce RTL, thereby enabling designers to avoid syntax errors common in traditional methodologies.
I was very fortunate enough to be able to speak directly with Steve Svoboda, marketing director for system level design products, Cadence, in the US, last evening, on the C-to-Silicon Compiler.
According to Svoboda, this tool can accurately predict timing estimates. Logic synthesis ability is embedded into the tool. Cadence logic sysnthesis has been embedded inside HLS. HLS transforms C and C++ into RTL.
What can this product actually do for the EDA industry? He says it can actually take EDA up to a new level in terms of delivering additional productivity to designers.
“When design compiler and logic synthesis came, it was during the golden era of the semiconductor industry. Productivity was increasing rapidly. But the problem is, since the early 1990s, there has been no real change in the RTL design methodology. The only productivity increase has come out in form of design re-use,” he says.
“This (C-to-Silicon Compiler) could re-energize semiconductor and EDA industries by at least 10X times. About 20 years ago, there was 10X productivity increase. By having HLS, we can now close the gap and tackle the chips more effectively now.”
So, first up, will C-to-Silicon Compiler compete with custom design projects? Svoboda it won’t! Custom design projects typically utilize transistor-level design. C-to-Silicon is made to work within a standard ASIC design-flow.
Accelerate and improve verification
The C-to-Silicon Compiler will both accelerate and improve verification as well. The timing-approximate fast hardware models (FHMs) run 80-90 percent the speed of untimed C-models (or two-three orders of magnitude faster than RTL). This enables the hardware-software co-verification with greater timing accuracy.
The next question is: can people use third-party synthesis tools, along with the proprietary Cadence systhesis tool? Svoboda says that the C-to-Silicon Compiler outputs IEEE-standard Verilog RTL. Therefore, the output can go to any third-party synthesis tool. However, as the RTL output is generated using timing estimates from Cadence RTL Compiler, designers will get the best quality of results when using RTL Compiler for logic synthesis.
Will C-to-Silicon Compiler better predict performance and power? And if yes, has this cracked the low-power design issue? Svoboda adds that because of embedded logic synthesis, the C-to-Silicon Compiler can predict performance and (in principle) power better than other high-level synthesis tools.
He says: “Power estimation/optimization are key feature sets planned for upcoming releases of C-to-Silicon Compiler. We believe that those capabilities will enable the designers to create designs that are much better optimized for power, since design decisions with greatest power impact are made at the system-level.”
Finally, how does C-to-Silicon compiler handle hardware allocation and scheduling operations? The answer is, C-to-Silicon Compiler handles hardware allocation and scheduling using various proprietary algorithms and heuristics. Many of these are based on previous research at Cadence Berkeley Labs.
Svoboda notes: “One should note that the better quality of results/performance of C-to-Silicon is due primarily to its inherent ability to generate more accurate timing-estimates than other HLS tools. The higher accuracy timing estimates result from the embedding of logic synthesis within the HLS tool/process, which enables gathering of full-context gate-level information to derive the timing estimates.
“Other HLS approaches rely on pre-characterization of technology libraries, which is not accurate enough, because those gate level estimates are only nominal values, and do not take into account the full-context of the design (fan-in, fan-out, buffers, etc.)”
Lastly, what happens to ESL (electronic system-level) tools? He believes that this tool will help the ESL market.
Svoboda says: “We now have a methodology to do design creation in C++ and SystemC. For example, they do virtual prototyping, hardware-software co-design, etc. In the past, when engineers created designs, they had to re-design in C++, etc. Our tool creates the RTL automatically for them. So, this could re-energize the ESL market very well.”
It will be interesting to see what the other EDA firms such as Synopsys and Magma have in store!
Don’t be surprised if you wake up one day and read a headline that heralds the coming of age of Dubai as a silicon frontier! The government of Dubai has been efficiently and effectively taking the necessary steps required to make that happen. It has set up the Dubai Silicon Oasis Authority (DSOA) as the engine for propelling Dubai into the knowledge economy.
H.H. Sheikh Mohammed bin Rashid Al Maktoum Ruler of Dubai, Vice President and Prime Minister of the UAE, Ruler of Dubai, said, “Our vision is to make Dubai Silicon Oasis one of the world’s leading centers of advanced electronics innovation, design and development.”
Economy and business destination
Dubai boasts of a robust economy, the GDP being $53.8B in 2007. The GDP has a very low dependency on oil, which was >5 percent in 2006, a fact not well known to many. While it has a small population of just 1.42 million, people from other nationalities — a total of 185 — comprise a whopping 1.2 million or so.
Dubai is now counted among the world’s top financial centers, boasting of world-class infrastructure, state-of-the-art telecom, and already a home to 139 major Fortune 500 regional offices.
Dubai also boasts of the world’s fastest growing airport, which is located near Deira. A new airport, with six parallel runways, is under construction near Jebel Ali. Dubai also hast two seaports, including the world’s largest man made port in Jebel Ali.
The Dubai Metro project is also underway. If this is not enough to propel the city as a leading business destination, Dubai also has highly superior logistic facilities — all major cargo services operate out of here., besides reliable power and utilities, and state-of-the-art IT and telecom infrastructure.
Some major international investments in the UAE region make very interesting reading. For instance, Abu Dhabi has an 8.1 percent stake in Advanced Micro Devices (AMD). Abu Dhabi also has 4.9 percent stake in Citigroup. Dubai Holdings has major investments in Daimler AG (2 percent), EADS (3.12 percent), and Tussauds Group (20 percent). The DIFX has a major stake in both NASDAQ and OMX.
The UAE itself is a regional powerhouse. UAE ranks #28, highest in the Arab world, compared to Israel #19 and Egypt #63. It is also the second largest MENA market for PCs — 594K units vs. 684K for Saudi Arabia, as per IDC.
DSOA’s value propositions
The DSOA was set up to create a universally recognized state-of-the-art technology oasis by facilitating and promoting technology-based industries, and R&D, within a fully integrated community. DSO is a technology-centric free zone. The Dubai Silicon Oasis is spread over 7.2sqkm. In fact, Dr. Jihad Kiwan, director, DSOA, pointed out that the DSOA was large enough to fit in eight wafer fabs!
The DSOA offers multiple value propositions. In terms of financial incentives, it offers full repatriation of capital and profit, 100 percent ownership, zero corporate tax for 49 years, which is renewable, and most importantly, zero income tax for 49 years, also renewable.
If this isn’t enough, the DSOA offers lower cost operations for technology companies, besides subsidized staff accommodations for R&D engineers. Throw in stringent IP laws, direct investment and support the creation of the DSOA tenants’ business ecosystem, and you have the complete package.
The DSO is fast becoming a hub for technology R&D activities in the region, and is also the home of regional HQ of major electronics companies. It currently has 119 tenants, as of early May 2008.
The entire ecosystem is being built within the DSOA. It is an emerging residential area, and will also be home to RIT Dubai, BITS Pilani Dubai, and GEMS Smart School. Add to this theme parks, golf clubs, seven-star hotels, etc. It is more of a fully ‘integrated city” purpose built by the government of Dubai, where its residents can work, live, learn and play.
Silicon and other activities
A variety of activities are promoted at the DSOA. In the microelectronics domain, there are activities related to IC design, EDA tools, semiconductor manufacturing, semiconductor assembly & test, as well as photovoltaics (PV).
Other general activities, not covering the semiconductors, include IT and IT security, telecom equipment, electronic and computer hardware, software development and solutions, nanotechnology, consultancy and business development, logistics, as well as talent development and recruitment.
The DSOA also houses the German Business Park and the Rochester Institute of Technology (RIT), Dubai. It has also made alliances with Synopsys, the EDA powerhouse, the American University of Sharjah, UAE University, University of Sharjah, BITS Pilani Dubai and Khalifa University.
The key business benefits of aligning with the DSO include access to a regional pool of talent, zero tax policy, competitive operating costs, and access to a regional market of 2 billion people. It also offers diverse support for creating R&D centers of Excellence.
Dubai Circuit Design
The Dubai Circuit Design (DCD) is one of the tenants within the DSOA with a vision to be the regional leading force for chip design innovation. DCD aims to provide customers with predictable chip design services and create a collaborative environment for its skilled engineers, which fosters creativity and innovation, while empowering them with the DSOA’s state-of-the-art computing infrastructure.
The DCD incidentally has an alliance with Synopsys. It allows the DCD to have easy access to cutting-edge EDA tools, IP, wide range of resources, as well as Design Sphere Access (state-of-the-art data center).
The 10-member chip design team at the DCD comprises various nationalities -– India, Morocco, Tunisia, Egypt — has already taped out one 65nm design. The team itself comes from leading semiconductor companies, such as Intel, Texas Instruments, Qualcomm, Wipro and STMicro, with an average experience of eight to 10 years.
The design team is experienced in areas such as front-end design, back-end physical design, design flow methodology, design for testability (DFT), etc.
The DCD offers a variety of IC design services (RTL to GDSII), supporting all technology nodes — 65nm and below. It also has strong expertise in designing complex, multi-million gate, low power and performance-critical designs. DCD can also undertake foundry interface on behalf of the customers.
It also offers consultancy — on-site or from the design center. This includes areas such as complete DFT solution, physical design, timing/power signoff, physical verification, reliability verification and extraction, full-chip feasibility analysis and area reduction, IP integration, full-chip feasibility analysis and area reduction, etc.
The DCD design team has done an SMC (scalable metrics chip) implementation. This was done using TSMC’s 65nm low power (LP) technology. The encryption/decryption engine has ~ 8 million gates with 70 memory macros.
Other details of the project include dual core voltage (1.2v/0.96v) and IOs at 3.3v, wire bond design with 172 pads, 3.5×3.5 mm2 die size, 333Mhz/100Mhz design speed, as well as DFT (scan, ATPG, memory BIST, JTAG test interface).
We are now entering the sub-20nm era. So, will it be business as usual or is it going to be different this time? With DAC 2013 around the corner, I met up with John Chilton, senior VP, Marketing and Strategic Development for Synopsys to find out more regarding the impact of new transistor structures on design and manufacturing, 450mm wafers and the impact of transistor variability.
Impact of new transistor structures on design and manufacturing
First, let us understand what will be the impact of new transistor structures on design and manufacturing.
Chilton said: “Most of the impact is really on the manufacturing end since they are effectively 3D transistors. Traditional lithography methods would not work for manufacturing the tall and thin fins where self-aligned double patterning steps are now required.
“Our broad, production-proven products have all been updated to handle the complexity of FinFETs from both the manufacturing and the designer’s end.
“From the design implementation perspective, the foundries’ and Synopsys’ goal is to provide a transparent adoption process where the methodology (from Metal 1 and above) remains essentially the same as that of previous nodes where products have been updated to handle the process complexity.”
Given the scenario, will it be possible to introduce 450mm wafer handling and new lithography successfully?
According to Chilton: “This is a question best asked of the semiconductor manufacturers and equipment vendors. Our opinion is ‘very likely’.” The semiconductor manufacturers, equipment vendors, and the EDA tool providers have a long history of introducing new technology successfully when the economics of deploying the technology is favorable.
The 300nm wafer deployment was quite complex, but was completed, for example. The introduction of double patterning at 20nm is another recent example in which manufacturers, equipment vendors and EDA companies work together to deploy a new technology.
Impact of transistor variability and other physics issues
Finally, what will be the impact of transistor variability and other physics issues?
Chilton said that as transistor scaling progresses into FinFET technologies and beyond, the variability of device behavior becomes more prominent. There are several sources of device variability.
Random doping fluctuations (RDF) are a result of the statistical nature of the position and the discreteness of the electrical charge of the dopant atoms. Whereas in past technologies the effect of the dopant atoms could be treated as a continuum of charge, FinFETs are so small that the charge distribution of the dopant atoms becomes ‘lumpy’ and variable from one transistor to the next.
With the introduction of metal gates in the advanced CMOS processes, random work function fluctuations arising from the formation of finite-sized metal grains with different lattice orientations have also become important. In this effect, each metal grain in the gate, whose crystalline orientation is random, interacts with the underlying gate dielectric and silicon in a different way, with the consequence that the channel electrons no longer see a uniform gate potential.
The other key sources of variability are due to the random location of traps and the etching and lithography processes which produce slightly different dimensions in critical shapes such as fin width and gate length.
“The impact of these variability sources is evident in the output characteristics of FinFETs and circuits, and the systematic analysis of these effects has become a priority for technology development and IP design teams alike,” he added.