Recently, The Brattle Group came out with its report titled “The Employment Impacts of Proposed Tariffs on Chinese Manufactured Photovoltaic Cells and Modules”. Here are excerpts from the report.
At the request of the Coalition for Affordable Solar Energy (CASE), The Brattle Group has studied the employment impacts of a proposed trade restriction on Chinese-manufactured crystalline photovoltaic cells and modules.
This topic is timely, because the US Department of Commerce (DOC) is currently reviewing a petition that would lead to substantial tariffs on Chinese-produced photovoltaic cells and modules. Petitioners have requested tariffs up to 250 percent on Chinese-manufactured products in response to alleged government subsidies and below cost pricing.
In brief, we estimate that tariffs will slow the growth in domestic demand for photovoltaic systems by homeowners, commercial establishments and utilities, resulting in substantial job losses. We estimate jobs at risk under two tariff levels – 50 percent or 100 percent.
We find that a 50 percent tariff will shut the vast majority of Chinese imports out of the US market, and a 100 percent tariff will effectively block them altogether. We also estimate employment impacts accounting for two scenarios, a low scenario which assumes low demand elasticity and high supply elasticity, and a high scenario which reflects a high demand elasticity and a low supply elasticity. Read more…
Srini Rajam, CEO, Ittiam Systems presented the guest keynote at the CDNLive! 2011 in Bangalore, India, titled ‘Designing Systems to Thrive in Disruptive Trends’. According to him, key factors for design project success include scope definition, realistic targets, good estimation and right resources. Today, smart system design enables being a step ahead in the world of disruptive system demands.
The concergence decade saw an affordable convergence of media and functions. The world also moved from the PC in 2000 to the smartphone in 2010. There has also been a convergence of audio, video and communications. The SoC and system design require performance, quality and price to work in tandem.
In the imagination decade, we have come to expect electronics to do whatever we fancy. In the smart system design era, we have come to anticipate a future system that will also work perfectly today.
Today, we are in the world of IP video communication. First, everything is evolving. There have been advances in video technology, SoC and infrastructure. Technologies designed elsewhere are being brought in. There is a virtually infinite range in quality and price levels. The video communication system holds the key dynamics. The SoC, software and system have entered into a synergistic relationship.
For smart system design, there is a need to look at the big picture. Scaling down is easier than scaling up. Smart system is built to achieve efficiency in scale down. The reference platform is needed for the development roadmap.
For designing, the system may function as a module in other system. Also, critical components of the system may evolve outside. Parts of the system may also get replaced by the ecosystem. As for the SoC, there must be a roadmap enabling application software portability. There should be modular scaling with plug and play of IPs/components. Tools for hardware-software co-development must be available from the early stages.
All of this would enable you to being a step ahead in the world of disruptive system demands.
This fourth seminar on embedded systems, organized recently in Bangalore by EDN Asia, Singapore, Reed Business, was further testament to India’s already proven embedded might.
Welcoming the delegates, Kirtimaya Varma, editor-in-chief, EDN Asia, noted that Bangalore continues to be a city of overwhelming importance for EDN Asia. “We believe that this city is well on its way of evolving from the electronics design hub of India to the electronics design hub of the world. We always look forward to this seminar as an opportunity for us to interact with the local design industry in India.
“Notwithstanding the severe recession, ISA-IDC estimates that the embedded software revenue is poised to grow from about $6 billion in 2008 to $7.3 billion in 2009. While most industrial segments are laying off staff, the embedded software workforce is projected to rise from about 126,000 in 2008 to 150,000 in 2009. These figures show the inherent strength of the embedded design industry in India.
“However, most of the embedded software activities in India are at the lower end of the value chain. But for the last few years large Indian companies are moving towards the higher end activities in specific domains. This is expected to expand the embedded software market. Besides, the growing consumer and automotive markets and increased expenditures in telecom and defense will also contribute towards the growth of embedded in the coming years.”
There were a series of presentations, led by V.R.Venkatesh, senior VP, head of product engineering services, Wipro Technologies. The other tracks were:
* Debug embedded systems with industry’s most advanced Mixed Signal Scopes (MSO) — Venkat Prasad, Agilent Technologies
* Small yet Highly Functional – Keeping Your System Cost Low with Embedded ICs — Lou Kai Chee, Fujitsu Microelectronics Asia Pte Ltd
* Highest Quality MCU Portfolio Drives your Ideas to Business — Ravi Kishore Ivaturi, Infineon Technologies
* Introducing nanoWatt XLP MCUs for eXtreme Low Power — Kanad S. Joshi, Microchip Technology Inc.
* Low Power Flash FPGA Technologies — Jijeesh M, Actel Corp.
* Embedded Processing with Xilinx — Akshat Jain, Xilinx
Having represented EDN Asia for quite a number of years in the past, I was extremely pleased to be part of this show. Another reason, Kirti Varma of EDN Asia and yours truly — our association goes back a really long time — starting from 1991 at Electronics For You, New Delhi, through to Global Sources and later, Reed Business!
I hope to add more information on some of the tracks, time permitting!
I recently had the opportunity of meeting up with Nimish Modi, Senior Vice President, Research and Development, Front-End Group, Cadence Design Systems, along with Rahul Arya, Marketing Director, Cadence Design Systems (I) Pvt. Ltd.
Modi provided a perspective on how solutions from the EDA sector help the electronic design industry improve productivity, predictability and reliability of design processes, especially verification. Design verification is the process of ensuring that a chip design meets its specifications.
According to him, today’s product development ecosystem comprises of three driving forces — productivity, predictability and reliability. “We are clearly at the core of product development. We have a very strong breadth and depth. There is a layer of solutions we have integrated with our product offerings,” he added.
He highlighted that Cadence’s solutions consist of integrated point tools, as well as recommended use models. It also has a very strong services offering.
Focus on five key areas
Currently, Cadence is focusing on five key areas — systems, low power, enterprise verification, mixed signal and advanced nodes. “We have a solutions oriented approach across the board,” Modi said.
On systems, it is key to focus on gaining more productivity. Modi said: “This can be done by raising the level of abstraction. The technologies available to address ESL have been around for a while, each one addressing a piece of the puzzle. The need is there for seeing tremendous improvements in that. Here, Cadence’s C-to-Silicon Compiler comes in.”
“The other piece is — it has incremental synthesis capabilities. A third thing — it is connected to the downstream flow. This is the foundation of our systems strategy,” said Modi.
Coming to the systems design and verification strategy, the first component involves planning and management. “We have an enterprise manager,” he added. Cadence has been a leader in the hardware assisted verification with rich VIP/SpeedBridge portfolio. It has enabled a move to TLM driven design and verification flow. Cadence also delivers unique system power exploration, estimation and optimization flow. It provides unique hardware/software co-verification capabilities (Incisive Software eXtensions) as well.
Low power strategy
On Cadence’s low power strategy, Modi highlighted three components — implementation, verification and design. “The innovation was the ability to create a power format to capture the design intent. We are committed to providing flow operability as well. We want customers to make use of advanced power management techniques,” he added.
“We have the superior low power technology,” he claimed, referring to the Power Forward Initiative (PFI). “Look at technology — that is proven. The format is a means to the end. We are also working on providing more capabilities in the power exploration space. We are working under different aspects.
“You can do power analysis on the IP block; there’s C-to-Slicon, which has power as a function; multi-supply voltage will be a component of our synthesis solution. All of these vectors are driving the power exploration space. Seventy percent of chips’ power is determined at or before the RTL stage,” said Modi.
Cadence has a closed loop verification methodology. At each stage, you can go back and make sure you can be consistent with what’s there upfront.
Enterprise verification strategy
On enterprise verification, Cadence’s approach is plan-to-closure. Predictability — utilize executable plans and metrics that predict functional closure; productivity — effectively deploy methodolgy driven multispecialist flows. with VIP and multiproduct automation; and quality — reduce risk of functional bugs at tape-out at various project stages.
Modi added: “Our verification IP portfolio is also very critical. The depth of our portfolio is the broadest in the industry. In verfication, the actual TAM is growing. We are getting opportunities as well. Multi dimensions of enterprise verification are being taken care of by us.”
Interesting that all EDA companies have focused on verification! Why now and why not earlier? Modi said: “We’ve been in this area for a while. We have pioneered the new approaches. The goal is: how do you know it is good enough to hit the tapeout button? Our goal is to raise the confidence of customers.”
He added: “We are coming uo with a hybrid model. We are engaging with customers at this point of time. We came up with multi-language support in OVM. We have 30+ verification IP portfolios.”
Trends in complex SoCs
Today, it is largely a mixed signal world. Mixed signal IC revenue has been increasing faster than the rest of the industry. It is driven by applications, including wireless devices, consumer and DTV, and automotive.
Modi said: “There is a genuine need to support natively analog behavioral models in a digital centric verification environment. Mixed signal is a larger percentagre of area and effort.”
Coming down to advanced nodes, it is no surprise that Cadence definitely supports MCMM (multicorner and multimode). “It is part of our Encounter Digital Implementation System,” added Modi.
Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;) I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.
Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.
In that case, why are some companies STILL not knowing how to verify a chip?
He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.
“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”
How are companies trying to address the challenges?
Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.
* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.
* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.
* Verification environment re-use helps to cut down the time required to develop verification environments.
* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.
Cadence has the widest portfolio of tools to help companies meet verification challenges, including:
Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;
The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;
Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and
Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.
Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.
When should good verification start?
Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”
Are folks mistaking by looking at tools and not at the verification process itself?
He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.
Finally, there’s verification planning! What should be the ‘right’ verification path?
Verification planning needs to include:
* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.