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Busy period ahead for Indian semicon, solar! While, TI bids for Qimonda’s tools!!

Yes, looks like it!

First, on August 31, the India Semiconductor Association and the UK-TI would be signing an MoU. The next day, September 1, there is a presentation by Ministry of New and Renewable Energy and key officials on the government of India’s policies to the industry!

Next, on September 4, the DIT Secretary R. Chandrasekhar and the Additional Secretary, will be interacting with semiconductor companies in Bangalore.

Further on, September 16 is the day when the Union Minister for New and Renewable Energy, Dr Farooq Abdullah, will be interacting with a small group of industry leaders at a solar PV conclave in Hyderabad!

That’s quite a lot, within a span of 15-odd days! Must say, this augurs well for the Indian semicon and solar/photovoltaics industry.

Interestingly, a lot of the big events are focusing on solar. So, my hunch is that the Indian solar industry may have some serious announcements to make in the coming weeks. Should that happen, I hope to bring those to you, time permitting.

TI bids for Qimonda’s tools
Oh, by the way, there’s news all over the Internet about Texas Instruments (TI) placing a bid of $172.5 million for Qimonda’s 300mm production tools from its closed DRAM fab. While this highlights TI’s focus on building the world’s first 300mm analog fab, I can’t stop wondering, what would have happened had an Indian investor really bought Qimonda!

Are EDA tools a commodity?

I had the pleasure of attending the 20th International Conference on VLSI Design and 6th International Conference on Embedded Systems in Bangalore, and had the good fortune of meeting a range of top experts from these fields.

One panel discussion: “Are EDA technology/products becoming a commodity?”, particularly caught my attention. Speakers debated on whether commoditization of EDA tools was happening with little/no differentiation toward project success.

Dr. Anand Anandkumar, managing director, Magma India, also a good friend, elucidated that the semiconductor design industry cannot do a complex SoC without EDA. And if there’s no EDA, there’s no integration. “If you are a commodity, you cannot solve problems!”

Now EDA is a key driver for semiconductor design companies to achieve objectives of building more and more complex (SoCs). However, the overall market size of EDA industry [estimated at US $4 billion] remains a fraction of the overall semiconductor market size [estimated at US $240 billion].

Dr Anandkumar added there had been various paradigm shifts and problems. The EDA industry was in a way the IP partner with the semiconductor industry. However, he agreed that parts of the tools had been commoditized. The EDA industry had become a prisoner of its own business model.

Nevertheless, newer things have been racing forward. There are also a variety of conflicting problems. Understanding those problems could be a way of handling and solving complex designs. The part of taking over risks had been completely absent. There was little ownership in sharing risks, which needed to change.

From the perspective of consumer electronics eco-system, available EDA technology is often viewed as not being in sync with the expectations and requirements of various design teams. Claims of productivity and quality of results advantages from EDA teams can seem more like wishful thinking than reality to end users.

More so, related issues of quality, inter-operability of standard formats, usability and understanding of designer needs are other areas of ongoing concern. These are not necessarily new issues, so what were EDA companies and their customers doing to address them? Has the EDA industry been getting its proportional value out of the semiconductor industry? Would love to hear from you.

Home-grown EDA company provides innovative tools

Bangalore-based Softjin Technologies is an electronic design automation (EDA) company providing unique EDA solutions for the semiconductor industry. According to Kamal Aggarwal, VP-Marketing and Strategy, the company’s core-capability lies in developing innovative EDA tools for specific requirements of customers, such as semiconductor companies and other EDA product companies.

Softjin’s business model is a “hybrid” model, which is a mix of services and products. It also provides FPGA based system design services and design methodology services for customers.

Softjin’s current products are licensable EDA building blocks that can be used as part of proving an EDA solution to customers in post-layout and logic synthesis technology area within EDA.

Post the announcement of India’s historic semicon policy, Softjin expects to see more investments happening in the semiconductor manufacturing space. As the policy provides incentives for setting up semiconductor manufacturing units above a certain size, Aggarwal expects to see more big-ticket announcements emerging in near future.

Watch the Indian semicon space, guys, as the action heats up…

Set up strong methodology teams to create better verification infrastructure: Synopsys

Arindam Ghosh

Arindam Ghosh

This is the third installment on verification, now, taken up by Synopsys. Regarding the biggest verification mistakes today, Arindam Ghosh, director – Global Technical Services, Synopsys India, attributed these as:

* Spending no time on verification planning (not documenting what needs to be verified) and focusing more on running simulations or on execution.
* No or very low investment in building better verification environments (based on best/new methodologies and best practices); instead maintaining older verification environments.
* Compromising on verification completeness because of tape out pressures and time-to-market considerations.

Would you agree that many companies STILL do not know how to verify a chip?

He said that it could be true for smaller companies or start-ups, but most of the major semiconductor design engineers know about the better approaches/methodologies to verify their chips. However, they may not be investing in implementing the new methodologies for multiple reasons and may instead continue to follow the traditional flows.

One way to address these mistakes would be to set up strong methodology teams to create a better verification infrastructure for future chips. However, few companies are doing this.

Are companies realizing this and building an infrastructure that gets you business advantage? He added that some companies do realize this and are investing in building a better infrastructure (in terms of better methodology and flows) for verification.

When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment? Ghosh said that good verification starts as soon as we start designing and architecting the design. Verification leads should start discussing the verification environment components with the lead architect and also start writing the verification plan.

Are folks mistaking by looking at tools and not at the verification process itself? According to him, tools play a major role in the effectiveness of any verification process, but we still see a lot of scope in methodology improvements beyond the tools.

What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities? Ghosh said that there is no single, full-proof recipe for a ‘right’ verification path. It depends on multiple factors, including whether the design is a new product or derivative, the design application etc. But yes, it is very important to do comprehensive verification planning before starting the verification process.

Synopsys is said to be building a comprehensive, unified and integrated verification environment is required for today’s revolutionary SoCs and would offer a fundamental shift forward in productivity, performance, capacity and functionality.  Synopsys’ Verification Compiler provides the software capabilities, technology, methodologies and VIP required for the functional verification of advanced SoC designs in one solution.

Verification Compiler includes:
* Better capacity and compile and runtime performance.
* Next-generation static and formal technology delivering performance improvement and the capacity to analyze a complete SoC (Property checking, LP, CDC, connectivity).
* Comprehensive low power verification solution.
* Verification planning and management.
* Next-generation verification IP and a deep integration between VIP and the simulation engine, which in turn can greatly improve productivity.  The constraint engine is tuned for optimal performance with its VIP library. It has integrated debug solutions for VIP so one can do protocol-level analysis and transaction-based analysis with the rest of the testbench.
* Support for industry standard verification methodologies.
* X-propagation simulation with both RTL and low power simulations.
* Common debug platform with better debug technology having new capabilities, tight integrations with simulation, emulation, testbench, transaction debug, power-aware debug , hw/sw debug, formal, VIP and coverage.

Top five recommendations for verification
What would be Synopsys’ top five recommendations for verification?

* Spend a meaningful amount of time and effort on verification planning before execution.
* Continuously invest in building a better verification infrastructure and methodologies across the company for better productivity.
* Collaborate with EDA companies to develop, evaluate and deploy new technologies and flows, which can bring more productivity to verification processes.
* Nurture fresh talent through regular on and off-the-job trainings (on flows, methodologies, tools, technology).
* Conduct regular reviews of the completed verification projects with the goal of trying to improve the verification process after every tapeout through methodology enhancements.

Categories: Semiconductors

Cadence: Plan verification to avoid mistakes!

Apurva Kalia

Apurva Kalia

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there’s verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

Five recommendations for verification: Dr. Wally Rhines

Dr. Wally RhinesIt seems to be the season of verification. The Universal Verification Methodology (UVM 1.2) is being discussed across conferences. Dennis Brophy, director of Strategic Business Development, Mentor Graphics, says that UVM 1.2 release is imminent, and UVM remains a topic of great interest.

Biggest verification mistakes
Before I add Dennis Brophy’s take on UVM 1.2, I discussed with Dr. Wally Rhines, chairman and CEO, Mentor Graphics Corp. the intricacies regarding verification. First, I asked him regarding the biggest verification mistakes today.

Dr. Rhines said: “The biggest verification mistake made today is poor or incomplete verification planning. This generally results in underestimating the scope of the required verification effort. Furthermore, without proper verification planning, some teams fail to identify which verification technologies and tools are appropriate for their specific design problem.”

Would you agree that many companies STILL do not know how to verify a chip?

Dr. Rhines added: “I would agree that many companies could improve their verification process. But let’s first look at the data. Today, we are seeing that about 1/3 of the industry is able to achieve first silicon success. But what is interesting is that silicon success within our industry has remained constant over the past ten years (that is, the percentage hasn’t become any worse).

“It appears that, while design complexity has increased substantially during this period, the industry is at least keeping up with this added complexity through the adoption of advanced functional verification techniques.

“Many excellent companies view verification strategically (and as an advantage over their competition). These companies have invested in maturing both their verification processes and teams and are quite productive and effective. On the other hand, some companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.”

How are companies trying to address those?

According to him, the recent Wilson Research Group Functional Verification Study revealed that the industry is maturing its verification processes through the adoption of various advanced functional verification techniques (such as assertion-based verification, constrained-random simulation, coverage-driven techniques, and formal verification).  Complexity is generally forcing these companies to take a hard look at their existing processes and improve them.

Getting business advantage
Are companies realizing this and building an infrastructure that gets you business advantage?

He added that in general, there are many excellent companies out there that view verification strategically and as an advantage over their competition, and they have invested in maturing both their verification processes and teams. On the other hand, some other companies are struggling to figure out the entire SoC space and its growing complexity and verification challenges.

When should good verification start?
When should good verification start — after design; as you are designing and architecting your design environment?

Dr. Rhines noted: “Just like the design team is often involved in discussion during the architecture and micro-architecture planning phase, the verification team should be an integral part of this process. The verification team can help identify architectural aspects of the design that are going to be difficult to verify, which ultimately can impact architectural decisions.”

Are folks mistaken by looking at tools and not at the verification process itself? What can be done to reverse this?

He said: “Tools are important! However, to get the most out of the tools and ensure that the verification solution is an efficient and repeatable process is important. At Mentor Graphics, we recognize the importance of both. That is why we created the Verification Academy, which focuses on developing skills and maturing an organization’s functional verification processes.”

What all needs to get into verification planning as the ‘right’ verification path is fraught with complexities?

Dr. Rhines said: “During verification planning, too many organizations focus first on the “how” aspect of verification versus the “what.” How a team plans to verify its designs is certainly important, but first you must identify exactly what needs to be verified. Otherwise, something is likely to slip through.

“In addition, once you have clearly identified what needs to be verified, it’s an easy task to map the functional verification solutions that will be required to productively accomplish your verification goals. This also identifies what skill sets will need to be developed or acquired to effectively take advantage of the verification solutions that you have identified as necessary for your specific problem.”

How is Mentor addressing this situation?

Mentor Graphics’ Verification Academy was created to help organizations mature their functional verification processes—and verification planning is one of the many excellent courses we offer.

In addition, Mentor Graphics’ Consulting provides customized solutions to technical challenges on real projects with real schedules. By helping customers successfully integrate advanced functional verification technologies and methodologies into their work flows, we help ensure they meet their design and business objectives.

Five recommendations for verification
Finally, I asked him, what would be your top five recommendations for verification?

Here are the five recommendations for verification from Dr. Rhines:

* Ensure your organization has implemented an effective verification planning process.

* Understand which verification solutions and technologies are appropriate (and not appropriate) for various classes of designs.

* Develop or acquire the appropriate skills within your organization to take advantage of the verification solutions that are required for your class of design.

* For the SoC class of designs, don’t underestimate the effort required to verify the hardware/software interactions, and ensure you have the appropriate resources to do so.

* For any verification processes you have adopted, make sure you have appropriate metrics in place to help you identify the effectiveness of your process—and identify opportunities for process improvements in terms of efficiency and productivity.

Semicon industry needs to keep delivering value: Anil Gupta

Anil Gupta

Anil Gupta

In 2013, the global semiconductor industry had touched $306 billion or so. Sales had doubled from $100 billion to $200 billion in six years — from 1994 to 2000. It was enterprise sales that was driving this. It has taken 14 years to move past $300 billion, said Anil Gupta, managing director, Applied Micro Circuits India Pvt Ltd, at the UVM 1.2 day.

This time, consumption of semiconductors is not only around enterprise, but social networks as well. Out of the $306 billion, logic was approximately $86 billion, memory was $67 billion, and micro was $58 billion. We, as consumers, are starting to play a huge role.

However, the number of large players seem to be shrinking. Mid-size firms, like Applied Micro, are said to be struggling. Technology is playing an interesting role. There is a very significant investment in FinFETs. It may only get difficult for all of us. Irrespective, all of this is a huge barrier to the mid- to small-companies. Acquisitions are probably the only route, unless you are in software.

In India, we have been worried for a while, whether the situation will be a passing phase. We definitely will have a role to play. From an expertise perspective, thanks to our background, we have been a poor nation. For us, the job is the primary goal. We need to think: how do we deliver value? We have to try and keep creating value for as long as possible.

As more and more devices actually happen, many other things are also happening. An example for devices is power. We still have a fair number of years ahead where there will be opportunities to deliver value.

What’s happening between hardware and software? The latter is in demand. Clearly, there is a trend to make the hardware a commodity. However, hardware s not going away! Therefore, the opportunity for us to deliver value is huge.

Taking the tools to make something, is critical. UVM tools are critical. But, somewhere along the way, we seem to stop at that. We definitely need to add value. UVM’s aim is to make things re-usable.

Don’t loose your focus while doing verification. Think about the block, the subsystem and the top. You need to and will discover and realize how valuable it is to find a bug, before the tape out of the chip.

Are we at an inflection point in verification?

synopsysAre we at an inflection point in verification today? Delivering the guest keynote at the UVM 1.2 day, Vikas Gautam, senior director, Verification Group, Synopsys, said that today, mobile and the Internet of Things are driving growth. Naturally, the SoCs are becoming even more complex. It is also opening up new verification challenges, such as power efficiency, more software, and reducing time-to-market. There is a need to shift-left to be able to meet time-to-market goal.

The goal is to complete your verification as early as possible. There have been breakthrough verification innovations. System Verilog brought in a single language. Every 10-15 years, there has been a need to upgrade verification.

Today, many verification technologies are needed. There is a growing demand for smarter verification. There is need for much upfront verification planning. There is an automated setup and re-use with VIP. There is a need to deploy new technologies and different debug environments. The current flows are limitimg smart verification. There are disjointed environments with many tools and vendors.

Synopsys has introduced the Verification Compiler. You get access to each required technology, as well as next-gen technology. These technologies are natively integrated. All of this enables 3X verification productivity.

Regarding next gen static and formal platforms, there will be capacity and performance for SoCs. It should be compatible with implementation products and flows. There is a comprehensive set of applications. The NLP+X-Prop can help find tough wake-up bug at RTL. Simulation is tuned for the VIP. There is a ~50 percent runtime improvement.

System Verilog has brought in many new changes.  Now, we have the Verification Compiler. Verdi is an open platform. It offers VIA – a platform for customizing Verdi. VIA improves the debug efficiency.

Global semicon industry trends in 2014: Analog Devices

Sam Fuller

Sam Fuller

I recently met Sam Fuller, CTO, Analog Devices, and had an interesting conversation. First, I asked him about the state of the global semicon industry in 2013.

Industry in 2013
He said: “Due to the uncertainties in the global economy in the last couple of years, the state of the global semiconductor industry has been quite modest growth. Because of the modest growth, there has been a buildup in demand. As the global economies begin to be more robust going forward, we expect to see more growth.”

Industry in 2014?
How does Analog Devices see the industry going forward in 2014? What are the five key trends?

He added: “I would talk about the trends more from an eco-system and applications perspective. Increased capability on a single chip: Given all the advances to Moore’s law, the capability of a chip has increased considerably in all dimensions and not just performance, be it the horsepower we see in today’s smartphones or the miniaturization and power consumption of wearable gadgets that were on show this year at CES.

“In Analog Devices’ case, as we are focused on high performance signal processing, we can put more of the entire signal chain on a single die. For our customers, the challenge is to provide their customers a more capable product which means a more complex product, but with a simpler interface.

“A classic example is our AD9361 chip, which is a single chip wideband radio transceiver for Software Defined Radio (SDR). It is a very capable ASSP (Application Specific Standard Products) as well as RF front end with a wide operating frequency of 70 MHz to 6 GHz.

“This chip, coupled with an all-purpose FPGA, can build a very flexible SDR operating across different radio protocols, wide frequency range and bandwidth requirements all controlled via software configuration. It finds a number of applications in wireless communication infrastructure, small cell Base stations as well as a whole range of custom radios in the industrial and aerospace businesses.”

Now, let’s see the trends for 2014!

More collaboration with customers: There is a greater emphasis on understanding customers’ end applications to provide a complete signal chain, all in a System on a Chip (SoC) or a System in a package (SiP). The relationship with our customers is changing as we move more towards ASSPs focused with few lead customers for target markets and target applications. While this has already been ongoing in the consumer industry with PCs and laptops, customers in other vertical markets like healthcare, automotive and industrial are and will collaborate more with semiconductor companies like Analog Devices to innovate at a solutions level.

More complete products: We have evolved from delivering just the silicon at a component level to delivering more complete products with more advanced packaging for various 3D chips or multi-die within a package. Our solutions now have typically much more software that makes it easier to configure or program the chips. It is a solution that is a combination of more advanced silicon, advanced packaging and more appropriate software.

With providing the complete solution, the products are more application specific and hence, the need for more collaboration with customers. For example, there may be one focused on Software Defined Radio, one for motor control, and one for vital signs monitoring for consumer health that we have launched recently.

We need it to be generic enough that multiple customers can use it, but it needs to be as tailored as possible to the customers’ needs for specific market segments. While because of the volume and standardization, availability of complete reference designs in the consumer world has been the norm, other market segments are demanding more complete products not-withstanding the huge variation in protocols and applications.

Truly global industry: The semiconductor and electronics industry has become truly global, so multiple design sites around the globe collaborate to create products. For example for Analog Devices, one of our premier design sites is our Bangalore product design center where we quite literally developed our most complex and capable chips. At the same time our customers are also global.

We see large multinational companies like GE, Honeywell, Cisco, Juniper, ABB, Schneider and many of our top strategic customers globally doing substantial system design work in Bangalore along with a multitude of India design houses. Our fastest growing region is in Asia, but we have substantial engagement with customers in North America and Europe. And our competition is also global, which means that the industry is ever moving faster as the competition is global.

Smarter design tools: The final trend worth talking about is the need for smarter design tools.  As our products and our customers’ products become more complex and capable, there have to be rapidly developing design tools, for us to design them.

This cannot be done by brute force but by designing smarter and better tools. There is a lot of innovation that goes on in developing better tool suites. There is also ever more capable software that caters to a market moving from 100s of transistors to literally billions of transistors for an application.

FinFETs delivering on promise of power reduction: Synopsys

Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry.

Rich Goldman

Rich Goldman

Global semicon in sub 20nm era
How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the history of mankind is not for the faint of heart. Keeping up with Moore’s Law has always required significant investment and ingenuity.

“The sub-20nm era brings additional challenges in device structures (namely FinFETs), materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over the revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception.

“Semiconductor companies focused on mobile and the Internet of Things are also thriving as their market quickly expands. Semiconductor companies who dominate their space in such segments as automotive, mil/aero and medical are also doing quite well, while non-leaders find rough waters.”

Performance of FinFETs
Have FinFETs gone to below 20nm? Also, are those looking for power reduction now benefiting?

He added that 20nm was a pivotal point in advanced process development. The 20nm process node’s new set of challenges, including double patterning and very leaky transistors due to short channel effects, negated the benefits of transistor scaling.

To further complicate matters, the migration from 28nm to 20nm lacked the performance and area gains seen with prior generations, making it economically questionable. While planar FET may be nearing the end of its scalable lifespan at 20nm, FinFETs provide a viable alternative for advanced processes at emerging nodes.

The industry’s experience with 20nm paved the way for an easier FinFET transition. FinFET processes are in production today, and many IC design companies are rapidly moving to manufacture their devices on the emerging 16nm and 14nm FinFET-based process geometries due to the compelling power and performance benefits. Numerous test chips have taped out, and results are coming in.

“FinFET is delivering on its promise of power reduction. With 20nm planar FET technologies, leakage current can flow across the channel between the source and the drain, making it very difficult to completely turn the transistor off. FinFETs provide better channel control, allowing very little current to leak when the device is in the “off” state. This enables the use of lower threshold voltages, resulting in better power and performance. FinFET devices also operate at a lower nominal voltage supply, significantly improving dynamic power.”
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