Busy period ahead for Indian semicon, solar! While, TI bids for Qimonda’s tools!!

Yes, looks like it!

First, on August 31, the India Semiconductor Association and the UK-TI would be signing an MoU. The next day, September 1, there is a presentation by Ministry of New and Renewable Energy and key officials on the government of India’s policies to the industry!

Next, on September 4, the DIT Secretary R. Chandrasekhar and the Additional Secretary, will be interacting with semiconductor companies in Bangalore.

Further on, September 16 is the day when the Union Minister for New and Renewable Energy, Dr Farooq Abdullah, will be interacting with a small group of industry leaders at a solar PV conclave in Hyderabad!

That’s quite a lot, within a span of 15-odd days! Must say, this augurs well for the Indian semicon and solar/photovoltaics industry.

Interestingly, a lot of the big events are focusing on solar. So, my hunch is that the Indian solar industry may have some serious announcements to make in the coming weeks. Should that happen, I hope to bring those to you, time permitting.

TI bids for Qimonda’s tools
Oh, by the way, there’s news all over the Internet about Texas Instruments (TI) placing a bid of $172.5 million for Qimonda’s 300mm production tools from its closed DRAM fab. While this highlights TI’s focus on building the world’s first 300mm analog fab, I can’t stop wondering, what would have happened had an Indian investor really bought Qimonda!

Are EDA tools a commodity?

I had the pleasure of attending the 20th International Conference on VLSI Design and 6th International Conference on Embedded Systems in Bangalore, and had the good fortune of meeting a range of top experts from these fields.

One panel discussion: “Are EDA technology/products becoming a commodity?”, particularly caught my attention. Speakers debated on whether commoditization of EDA tools was happening with little/no differentiation toward project success.

Dr. Anand Anandkumar, managing director, Magma India, also a good friend, elucidated that the semiconductor design industry cannot do a complex SoC without EDA. And if there’s no EDA, there’s no integration. “If you are a commodity, you cannot solve problems!”

Now EDA is a key driver for semiconductor design companies to achieve objectives of building more and more complex (SoCs). However, the overall market size of EDA industry [estimated at US $4 billion] remains a fraction of the overall semiconductor market size [estimated at US $240 billion].

Dr Anandkumar added there had been various paradigm shifts and problems. The EDA industry was in a way the IP partner with the semiconductor industry. However, he agreed that parts of the tools had been commoditized. The EDA industry had become a prisoner of its own business model.

Nevertheless, newer things have been racing forward. There are also a variety of conflicting problems. Understanding those problems could be a way of handling and solving complex designs. The part of taking over risks had been completely absent. There was little ownership in sharing risks, which needed to change.

From the perspective of consumer electronics eco-system, available EDA technology is often viewed as not being in sync with the expectations and requirements of various design teams. Claims of productivity and quality of results advantages from EDA teams can seem more like wishful thinking than reality to end users.

More so, related issues of quality, inter-operability of standard formats, usability and understanding of designer needs are other areas of ongoing concern. These are not necessarily new issues, so what were EDA companies and their customers doing to address them? Has the EDA industry been getting its proportional value out of the semiconductor industry? Would love to hear from you.

Home-grown EDA company provides innovative tools

Bangalore-based Softjin Technologies is an electronic design automation (EDA) company providing unique EDA solutions for the semiconductor industry. According to Kamal Aggarwal, VP-Marketing and Strategy, the company’s core-capability lies in developing innovative EDA tools for specific requirements of customers, such as semiconductor companies and other EDA product companies.

Softjin’s business model is a “hybrid” model, which is a mix of services and products. It also provides FPGA based system design services and design methodology services for customers.

Softjin’s current products are licensable EDA building blocks that can be used as part of proving an EDA solution to customers in post-layout and logic synthesis technology area within EDA.

Post the announcement of India’s historic semicon policy, Softjin expects to see more investments happening in the semiconductor manufacturing space. As the policy provides incentives for setting up semiconductor manufacturing units above a certain size, Aggarwal expects to see more big-ticket announcements emerging in near future.

Watch the Indian semicon space, guys, as the action heats up…

Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”

On-chip networks: Future of SoC design

Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.

John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage – saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.

Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.

For the record, there are several SoC integration challenges that need to be addressed, such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.

SGN exceeds requirements
SGN met the tablet performance requirement with fabric frequency of 1066MHz. It has an efficient gate count of 508K gates. There are features such as an advanced system partitioning, security and I/O coherency. There is support for system concurrency as well as advanced power management.

Sonics offers system IP solutions such as SGN, a router based NoC solution, with flexible partitioning and VC (Virtual Channel) support. The frequency is optimized with credit based flow control.

SSX/SLX is message based crossbar/ShareLink solutions based on interleaved multi-channel technology. It has target based QoS with three arbitration levels. The SonicsExpress is for power centric clock domain crossing. There is sub-system re-use and decoupling. The MemMax manages and optimizes the DRAM efficiency while maintaining system QoS. There is run-time programmability for all traffic types. The SonicsConnect is a non-blocking peripheral interconnect.

Focusing light on breast cancer diagnostics

A team of scientists at the Massachusetts Institute of Technology (MIT), comprising principally of Dr. Ishan Barman, Dr. Narahara Chari Dingari and Dr. Jaqueline Soares, and their clinical collaborators at University Hospitals, Cleveland have developed the Raman scattering-based concomitant diagnosis of breast cancer lesions and related micro-calcifications.

Let’s find out more about this new breast cancer research done by the team at MIT.

Early detection necessary!
According to MIT, one in eight women in the US will suffer from breast cancer in her lifetime and breast cancer is the second leading cause of cancer death in women. Worldwide, breast cancer accounts for 22.9 percent of all cancers (excluding non-melanoma skin cancers) in women. In 2008, breast cancer caused 458,503 deaths worldwide (13.7 percent of cancer deaths in women).

Core needle biopsy.

Therefore, technological advancements for its early detection and subsequent treatment can make a significant impact by preventing patient morbidity and mortality and reducing healthcare costs, and are thus of utmost importance to society. Currently, mammography followed by stereotactic breast biopsy serves as the most promising route for screening and early detection of cancer lesions.

Nearly 1.6 million breast biopsies are performed and roughly 250,000 new breast cancers are diagnosed in the US each year. One of the most frequent reasons for breast biopsy is microcalcifications seen on screening mammography, the initial step in early detection of breast cancer. Microcalcifications are micron-scale deposits of calcium minerals in breast tissue that are considered one of the early mammographic signs of breast cancer and are, therefore, a target for stereotactic breast needle biopsy.

However, despite stereotactic guidance, needle biopsy fails to retrieve microcalcifications in one of five breast biopsy patients. In such cases, the resulting breast biopsies are either non-diagnostic or false-negative, thereby, placing the patient at risk and potentially necessitating a repeat biopsy, often as a surgical procedure.

There is an unmet clinical need for a tool to detect microcalcifications in real time and provide feedback to the radiologist during the stereotactic needle biopsy procedure as to whether the microcalcifications seen on mammography will be retrieved or the needle should be re-positioned, without the need to wait for a confirmatory specimen radiograph.

Such a tool could enable more efficient retrieval of microcalcifications, which would, in turn, minimize the number of x-rays and tissue cores required to achieve a diagnostic biopsy, shorten procedure time, reduce patient anxiety, distress and discomfort, prevent complications such as bleeding into the biopsy site seen after multiple biopsy passes and ultimately reduce the morbidity and mortality associated with non-diagnostic and false-negative biopsies and the need for follow up surgical biopsy.

If 200,000 repeat biopsies were avoided, at a cost of $5,000 per biopsy (a conservative estimate and would be much higher for surgical biopsies), a billion dollars per year can be saved by the US healthcare system. The MIT Laser Biomedical Research Center, has recently performed pioneering studies to address this need by proposing, developing and validating Raman and diffuse reflectance spectroscopy as powerful guidance tools, due to their ability to provide exquisite molecular information with minimal perturbation.

Specifics of the technique
Stating the specifics of the technique developed by MIT, the team said that their research focuses on the development of Raman spectroscopy as a clinical tool for the real time diagnosis of breast cancer at the patient bedside. “We report for the first time development of a novel Raman spectroscopy algorithm to simultaneously determine microcalcification status and diagnose the underlying breast lesion, in real time, during stereotactic breast core needle biopsy procedures.”

Microcalcification..

In this study, Raman spectra were obtained ex vivo from fresh stereotactic breast needle biopsies using a compact clinical Raman system, modeled and analyzed using support vector machines to develop a single-step, Raman spectroscopy based diagnostic algorithm to distinguish normal breast tissue, fibrocystic change, fibroadenoma and breast cancer, with and without microcalcifications.

The developed decision algorithm exhibits a positive and negative predictive value of 100 percent and 96 percent, respectively, for the diagnosis of breast cancer with or without microcalcifications in the clinical dataset of nearly 50 patients.

Significantly, the majority of breast cancers diagnosed using this Raman algorithm are ductal carcinoma in situ (DCIS), the most common lesion associated with microcalcifications, which has classically presented considerable diagnostic challenges.

This study demonstrates the potential of Raman spectroscopy to provide real-time feedback to radiologists during stereotactic breast needle biopsy procedures, reducing non-diagnostic and false negative biopsies. Indeed, the proposed approach lends itself to facile assembly of a side-viewing probe that could be inserted into the central channel of the biopsy needle for intermittent acquisition of the spectra, which would, in turn, reveal whether or not the tissue to be biopsied contains the targeted microcalcifications.

Tensilica to expand Cadence IP footprint in SoCs

Chris Rowan.

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.

Embedded systems trends and developer opportunities

Herb Hinstorff.

Today, the world is transitioning from independent devices to  connected systems. Intel has been inside the embedded systems market for over 35 years, having developed 270+ CPUs and SoCs as well as 100+ chipsets.

Herb Hinstorff, director of Marketing, Developer Products Division, Intel Software, said that Intel has been engaged at all levels of the solution stack. He was speaking at the 13th Global Electronics Summit at Santa Cruz, USA.

There are tools to deliver on developer needs, such as debuggers, analyzers, compilers and libraries. There are tools to provide the deep system-level insights into power, reliability and performance.

On the debuggers side, they increase system and device stability and reliability. There is an efficient system, SoC-wide defect analysis and ultra-fast system-wide tracing for software debug. There is an integrated application level debugger. Overall, it speeds system bring-up and development. Analyzers focus on boosting reliability, power efficiency and performance, enabling differentiated designs, system-wide analysis and deep insights.

Compilers go on to optimize performance and efficiency. There is the industry-leading C/C++ compiler. It boosts system and application performance on Intel Atom, Core and Xeon processors. Compilers also take advantage of the multicore to boost performance.

There are libraries for performance and efficiency. Software building blocks increase the developer productivity and boost performance. There are specialized testing functions that handle signal processing, data processing, complex math operations and multimedia processing. Besides, there is future-proof software investments. The libraries provide an easy way to take advantage of the multicore capabilities to boost performance.

The Intel System Studio is an integrated software tool suite that provides deep, system-wide insights to help accelerate time-to-market, strengthen system reliability, and boost power effiency and performance. The JTAG interface has system and application code running Linux.

There is a continued broadening of the OS support, and a broader range of tools to match the expanding SoC capabilities. There is more extensive software based training and simulation, as well as market-specific libraries and APIs.

Given that the market is transitioning from independent devices to connected systems, more capable SoC platforms and complex software stacks require deeper and broader system-level insights and optimizations. Embedded developers can take advantage of the Intel System Studio to accelerate the time-to-market, strengthen system reliability, and boost power efficiency and performance of the Intel architecture-based embedded and mobile systems.

Embedded software: Next revolution in EDA

Dr. Wally Rhines.

There is a key lesson that Mentor Graphics made while trying to deliver solutions that were right for software and hardware developers. The lesson was: tailor the software to the discipline! Make it as similar to their environment as possible!!

Delivering his speech at the ongoing 13th Global Electronics Summit in Santa Cruz, USA, Dr. Wally Rhines, chairman and CEO, Mentor Graphics, said that 15 years of acquisitions taught Mentor how to think and behave as an embedded software company.

Open systems requires active engagement in software committees. Each open source project has some form of governance to manage contributions, release plans, etc. There is a community peer selection process for each open source project. About 50 Mentor Embedded Sourcerers are actively involved in the open source and Android communities.

There is a need to take the advantage of knowing both worlds. Mentor’s Sourcery CodeBench is an embedded C/C++ development tool based on open-source standards. Sourcery CodeBench is a complete development environment for embedded C/C++ development on ARM, Coldfire, MIPS, Power, X86, and other architectures. You can install, flash and debug in minutes!

Sourcery CodeBench
Sourcery CodeBench is now the semiconductor industry’s leading embedded toolchain. There is an integrated development environment. It has the GNU compiler (GCC) and optimization tools. It allows debugging and analysis, libraries and QEMU simulator.

There are about ~15,000 downloads per month. There have been ~150,000 downloads and 300 releases per year.

E450EDL – European 450mm equipment demo line

Malcolm Penn, chairman and CEO, Future Horizons, sent me the Enable 450 newsletter. The goal of the Enable 450 is: Co-ordination Action to enable an effective European 450 mm Equipment and Materials Network. Here, I am presenting a bit about the E450EDL – European 450mm Equipment demo line.

Malcolm Penn

The aim of the ENIAC E450EDL key enabling technology pilot project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition that started with the ENIAC JU EEMI450 initiative and proceeded with subsequent projects funded with public money, amongst others NGC450, SOI450, EEM450PR.

The demo line resulting from this project will be such that it will enable first critical process module development by combining imec infrastructure with tools remaining at the site of the manufacturers (distributed pilot line). Multi-site processing will allow partners to participate in the world first 450mm integration studies and will be enabled by the controlled exchange of 450mm wafers between different sites.

The consortium comprises 41 members (from 11 different European countries) with many SMEs and research institutes. The project is organized in five technical work packages and a work package on management and co-ordination.

In the work package on integration and wafer processing first critical modules will be developed and will demonstrate the feasibility of processing on 450mm wafers. The main objective in the work package on lithography is to develop a wafer stage test-rig, which
can be implemented into the pilot line system. In the work package on front end equipment several tools will be developed such as a plasma ion implant module, a plasma dry etch module, a RTP system and a single wafer cleaning system.

Furthermore, in the dedicated work package on metrology 450mm metrology tool types will be developed for amongst others dielectric film thickness and composition measurements, defect inspection, defect review and analysis, optical critical dimensions (CD), overlay (mask and wafer) and 3D metrology.

Finally, from the work package on wafer handling and automation a set of equipment will be provided to support the demo line operations, and facilitate the R&D dedicated to process and metrology modules.

The project will last 36 months beginning on 1st of October 2013. The budget has been given at €204.6 million of which the ENIAC JU will fund €30.8 million. This project is still considering new members so if you are interested please contact ASML.