Xilinx Inc. has announced of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support.
Neeraj Varma, director-Sales, India, Xilinx, said: “We are enabling All Programmable and smarter systems. We are using smart IP. We are aligning to produce smarter systems. We are helping customers to differentiate their products faster.
“In future, we will go with concurrent nodes with FPGAs, SoCs and 3D ICs. As per our estimates, 28nm will have a very long life. We shipped the 20nm device in early Nov. 2013. It complements 28nm or new high-performance architectures. 16nm complements 20nm with FinFET, multiprocessing, memory.”
Strategy execution has kept Xilinx a generation ahead. As of Dec. 2013, its 20nm portfolio is available to customers. There are two major announcements from Xilinx.
* Xilinx 20nm All Programmable UltraScale portfolio now available with ASIC-class architecture and ASIC-strength design solution.
* Xiilinx doubles industry’s highest capacity device to 4.4 mn logic, delivering density adantage, a full generation ahead.
KINTEX UltraSCALE – XCKU035, 040, 060, 075, 100, 115.
VIRTEX UltraSCALE – XCVU065, 080, 095, 125, 145, 160.
There is a family migration path. There is scalability for derivative applications. You can leverage PCB investment across platforms. It is future-proof with migration path to 16nm. For making these happen, Xilinx is using the TSMC 20SoC.
Varma added, “We have increased the logic cells in Kintex and Virtex, and added 100G Ethenet blocks and 150G Interlaken blocks.”
The second announcement – highest density in FPGAs in industry. The XCVU440 is the largest in the industry by 4X, a full generation ahead, and uses 50M equivalent ASIC gates. Xilinx is delivering an ASIC-class advantage through silicon, tools and methodology.
There is UltraSCALE ASIC-class architecture, and ASIC-class capabilities. There is also the Vivado ASIC-strength design suite.
UltraFAST is the design methodology. UltraSCALE will support networking, digital video and wireless.
Interconnect bottlenecks impede next generation performance.
* Routing delay dominates overall delay.
* Clock skew consumes more timing margin.
* Sub-optimal CLB packing reduces performance and utilization.
Varma added: “We have solved these issues – as UltraSCALE re-architects the core. There is 90 percent utilization now with maximum performance. We added next-generation routing, ASIC-like clocking – have clocks by segment, and logic cell packing.
“Block-level innovations optimize critical paths for massive bandwidth and processing. We are going to support DDR4, and there will be a lot more security features.”
The Vivado design suite accelerates productivity. Analytical placer solves the interconnect issue.
UltraSCALE apps include:
VIRTEX: 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G Muxponder, ASIC prototyping.
KINTEX: 4×4 mixed mode radio, 100G traffic manager NIC, super high-vision processing, 256-channel ultrasound, 48-channel T/R radar processing.
Xilinx Inc. has taped-out the first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture. It is said to be the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. Xilinx implemented the industry’s first ASIC-class programmable architecture called UltraScale.
These milestones expand on Xilinx’s industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite. Xilinx already has several firsts in the 28nm space, such as:
* First 28nm tape-out.
* First All Programmable SoC.
* First All Programmable 3D IC.
* First SoC-strength design suite.
Neeraj Varma, director-Sales, India, said that Xilinx’s global market share in the 28nm portfolio was 65 percent in March 2013. With the launch of the industry’s first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture, there are improvements such as 1.5-2x performance and integration, and a year ahead of the competition. It handles massive I/O bandwidth, massive memory bandwidth, massive data flow and routing, and fastest DSP processing. The architecture will scale — from monolithic to 3D IC, planar to FinFET, and ASIC-class performance.
The UltraSCALE architecture points to high performance smarter systems. For example, 1Tps in OTN networking, 8K in digital video, LTE-A in wireless communications, and digital array in radar. There will be requirements for massive packet processing over 400 Gbps wire-speed, massive data flow over 5Tbps, as well as massive I/O and memory bandwidth over 5Tbps, and DSP performance over 7 TMACs.
The mandate for ASIC-class programmable architecture is to remove bottlenecks for massive data flow and smart processing, high throughput with low latency, and efficient design closure with greater than 90 percent utilization without performance degradation. These are the benefits of applying leading edge ASIC techniques in a fully programmable architecture.
ASIC-like clocking maximizes performance margin for highest throughput. UltraSCALE ASIC-like clocking enables clock placement virtually anywhere on the die, making the clock skew problem go away. Also, highly optimized critical paths remove bottlenecks in DSP and packet processing. There is greatly enhanced DSP processing, high-speed memory cascading, and hardened IP for I/O intensive functions.
Next generation power management features also enable a leap in performance. The process node is up to 35 percent static at 20nm. There are more buffers for granular or coarse clock gating. Block RAM is dynamic power gating, hardened cascading. For transceivers, there are architectural optimizations. There is efficient packing and utilization of the logic fabric. For DSP, there are wider multipliers and fewer blocks per function. As for memory, there is DDR4, which operates at 1.2v vs.1.5v, voltage scaling.
The Xilinx KINTEX UltraSCALE will power 4×4 mixed-mode radios, 100G traffic manager NICs, super high-vision processing, 256-channel ultrasound and 48-channel T/R radar processing. The Xilinx VIRTEX UltraSCALE will power 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G muxponder and ASIC prototyping.
Xilinx worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The Xilinx Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in Q4-2013.
STMicroelectronics has introduced the STM32L advanced ultra-low-power Cortex-M3 based MCU platform.
Built on cutting-edge proprietary process – robustness, it is part of a wide 32-bit product portfolio. The MCU platform is based on the just-enough energy concept and has an all inclusive package applications.
STM32L 32- to 128-Kbyte products are entering full production in the second half of March 2011. It is part of the industry’s largest ARM Cortex-M 32-bit microcontroller family with six STM32 families. STMicroelectronics is developing the STM32L portfolio up to 384 Kbytes of embedded memory. The STM32L is also Continua ready for its USB peripheral driver.
STM32L’s robustness has been derived from an automotive qualified process. It is all inclusive for ultra-low-power applications, and comes with hardware integrated features and software library packages. STM32L also has a ‘just-enough energy concept’, which includes undervolting, user controlled and an innovative architecture, all of this for less than 1 µA.
ST’s ultra-low-power EnergyLite platform features ST’s 130nm ultra-low-leakage process technology. It makes use of shared technology, architecture and peripherals. The company’s ultra-low-power portfolio for 2011 will be in production second half of March 2011. Many others will also be in production in the second half of April 2011. In fact, there will be over 100 part numbers from 4- to 384-Kbyte flash, and from 20 to 144 pins.
STM32L is based on ultra-low-power architecture, which is all inclusive for ultra low power applications. It also features ultra-low voltage, with power supply down to 1.8 V with BOR and also down to 1.65 V without BOR.The analog functional can be down to 1.8 V and the reprogramming capability can be down to 1.65 V.
STM32L is also flexible and secure, featuring +/- 0.5 percent internal clock accuracy when trimmed by RTC oscillator. It has up to five clock sources and has the MSI to achieve very low power consumption at seven low frequencies.
It also feattures dynamic voltage scaling in Run mode. The voltage scaling optimizes the product efficiency. User selects a mode (voltage scaling) according to external VDD supply, DMIPS performance required and maximum power consumption. It features the energy saving mode as well, down to 171 µA/DMIPS from Flash in Run mode. Read more…
STMicroelectronics recently launched the STM32L EnergyLite ultra-low-power MCUs. I caught up with Vinay Thapiyal, technical marketing manager, MCU’s, ST India, to learn more.
The highlights of this series of MCUs include a commitment for ultra-low power — the EnergyLite platform is common for 8-bit (STM8L) and 32-bit (STM32L) MCUs. Also, it is strong on pure energy efficiency, with high performance combined with ultra low power, i.e., high high energy saving. Finally, the ultra low power member in STM32 portfolio enriches both the STM32 ultra-low-power EnergyLite platform and the STM32 portfolio.
According to Thapliyal, STMicroelectronics has been involved in the MCU market for a long time. Off late, it has started focusing on the STM32 — the ARM Cortex based MCU and the STM8 — for 8-bit family. “We have started converging our old families into these two domains,” he added.
The STM32F is the foundation of the STM32 family. STM32F is a family of low power MCUs based on the 32-bit ARM Cortex M3 architecture.
The STM8 is a family of MCUs based on ST’s propritetary atchitecture. The STM32L is STMicroelectronics’ ultra low power family mainly used for portable and very low power applications.
The ultra-low-power EnergyLite platform, featuring the STM32L and the STM8L is based on STMicroelectronics’ 130 nm ultra-low-leakage process technology. They share common technology, architecture and peripherals. The STM8, which was launched in 2009, has caught on very fast. It is a high performance, low cost MCU.
He added that STMicroelectronics started with 130nm technology, and low pin count and low flash on STM8, while higher memory and high pin count is available on the STM32. Read more…
Measuring performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future
There is this really great story from IBM Research Labs that I simply have to seed here for my readers.
IBM’s scientists have created a method to measure the performance of carbon nanotubes as building blocks for ultra-tiny computer chips of the future. Of course, you can also read it on IBM Research Lab’s site as well as on CIOL’s semicon site.
IBM scientists have measured the distribution of electrical charges in tubes of carbon that measure less than 2nm in diameter, 50,000 times thinner than a strand of human hair.
This novel technique, which relies on the interactions between electrons and phonons, provides a detailed understanding of the electrical behavior of carbon nanotubes, a material that shows promise as a building block for much smaller, faster and lower power computer chips compared to today’s conventional silicon transistors.
Phonons are the atomic vibrations that occur inside material, and can determine the material’s thermal and electrical conductivity. Electrons carry and produce the current. Both are important features of materials that can be used to carry electrical signals and perform computations.
The interaction between electrons and phonons can release heat and impede electrical flow inside computer chips. By understanding the interaction of electrons and phonons in carbon nanotubes, the researchers have developed a better way to measure their suitability as wires and semiconductors inside of future computer chips.
In order to make carbon nanotubes useful in building logic circuitry, scientists are pushing to demonstrate their high speed, high packing density and low power consumption capabilities as well as the ability to make them viable for potential mass production.
Dr. Phaedon Avouris, IBM Fellow and lead researcher for IBM’s carbon nanotube efforts, said: “The success of nanoelectronics will largely depend on the ability to prepare well characterized and reproducible nano-structures, such as carbon nanotubes. Using this technique, we are now able to see and understand the local electronic behavior of individual carbon nanotubes.”
To date, researchers have been able to build carbon nanotube transistors with superior performance, but have been challenged with reproducibility issues. Carbon nanotubes are sensitive to environmental influences.
For example, their properties can be altered by foreign substances, affecting the flow of electrical current and changing device performance. These interactions are typically local and change the density of electrons in the various devices of an integrated circuit, and even along a single nanotube.
Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.
Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.
Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.
“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”
When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.
Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.
The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.
Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.
Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.
FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?
Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.
Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.
Texas Instruments has been a leader in DLP or digital light processing, a type of projector technology that uses a digital micromirror device. Kent Novak, senior VP, DLP Products, Texas Instruments (TI) mentioned that DLP became the no. 1 supplier of MEMS technology in 2004.
The DLP pico projectors business started in 2009. Now, pico is going into gaming systems, etc. In 2011, it went into the cinema industry. In India, out of 10,000 screens, close to 7,000 are now digital. In 2012, new DLP development kit was launched allowing developers to embed the DLP chip into non-traditional applications in new markets. In 2013, TI started working on DLP automotive chips.
He said: “DLP is an array of millions of digital micromirrors. We ship around 45 million devices. We see India as a growth opportunity for cimemas. In DLP front projection business, we have 60 percent share in India. Only 5 percent of Indian classrooms have projectors, making room for growth.”
In low power pico projection, TI has 95 percent market share in India for standalone pico projection. A phone with pico projection was launched in India with iBall at 35 lumen.
DLP technology is available in India in:
Industrial: Machine vision can improve quality control in the Indian manufacturing sector.
Medical: Intelligent illumination systems for cost effective blood analysis.
Safety: Cost effective, accurate chemical analysis of food and industrial.
Automotive: Infotainment and safety solution being qualified.
DLP in automotive displays has several applications, such as wide field of view head up display (HUD) – app available by 2016, free shape interactive active console – app available by 2017, and smart headlights. Some other features include:
* High image quality: consistent contrast, brightness over lamp.
* Full, deep, accurate cover over lifetime.
* Easily enlarges larger display areas.
* High power efficiency.
* DLP technology automatically reduces reflection.
New market opportunities
There are said to be several new opportunities for DLP. These are in:
Industrial: Machine vision, spectroscopy, interactive display, 3D printing, intelligent lighting, digital light exposure.
Infotainment: Mobile phones, tablets, camcorders, laptops, mobile projection, ultra slim TVs.
Gaming: Dual console gaming, interactive gaming, near eye display.
Digital signage: Interactive surface, storefront interactive, retail engagement.
Automotive: Head up display, interactive display, intelligent lighting.
Medical: Spectroscopy, 3D printing, intelligent lighting.
TI has DLP LightCrafter family of evaluation modules. It enables faster development cycles for end equipment requiring smalll form factor, lower cost and intelligent, high-speed pattern display. The DLP LightCrafter 4500 features the 0.45 WXGA chipset. The DLP chip can enable new and innovative intelligent display apps. If your solution uses, programs or senses light, DLP could be a fit.
DLP catalog offers programmable, ultra-high speed pattern. “DLP is light source agnostic. We use whatever’s most efficient for brightness,” he added.
Yesterday evening, the Indian Cabinet Committee on Economic Affairs has approved setting up of Information Technology Investment Region (ITIR) near Hyderabad.
The Phase I of this project will be from 2013 to 2018 and Phase II will be from 2018 to 2038. The Government of Andhra Pradesh has delineated an area of 202 sq. kms. for the proposed ITIR in three clusters/ agglomerations viz.:
(i) Cyberabad Development Area and its surroundings,
(ii) Hyderabad Airport Development area and Maheshwaram in the south of Hyderabad, and
(iii) Uppal and Pocharam areas in eastern Hyderabad. The ITIR will be implemented in two phases.
Next, the Government of India finalized the setting up of a ‘Ultra-Mega Green Solar Power Project’ in Rajasthan in the SSL (Sambhar Salts Ltd, a subsidiary of Hindustan Salts Ltd – a Central Public Sector Enterprise under the Department of Heavy Industry, Ministry of Heavy Industries & Public Enterprises) area close to Sambhar Lake, about 75 kms from Jaipur.
Further, India was recognized as ‘Authorizing Nation’ under the international Common Criteria Recognition Arrangement (CCRA) to test and certify electronics and IT products with respect to cyber security. India has become the 17th nation to earn this recognition.
Then again, the ‘HTML 5.0 Tour in India’ has now reached Hyderabad.
Also, India has offered to help Cuba develop its renewable energy resources. This has been conveyed to Marino Murillo, vice president of the Republic of Cuba at Havana, by Dr. Farooq Abdullah, Minister of New and Renewable Energy, during his trip to Cuba.
All of this is really brilliant stuff!
At least, I have never seen or heard about so much activity happening, especially in the electronics and solar PV sectors. One sincerely hopes that all of these initiatives will allow India to come to the forefront of the global electronics industry.
The spark seems to be coming back to the India electronics industry, after a very, very long wait! It is hoped that this stays on!!