Here is the concluding part of my conversation with Synopsys’ Rich Goldman on the global semiconductor industry.
Global semicon in sub 20nm era
How is the global semicon industry performing after entering the sub 20nm era? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, said that driving the fastest pace of change in the history of mankind is not for the faint of heart. Keeping up with Moore’s Law has always required significant investment and ingenuity.
“The sub-20nm era brings additional challenges in device structures (namely FinFETs), materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over the revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception.
“Semiconductor companies focused on mobile and the Internet of Things are also thriving as their market quickly expands. Semiconductor companies who dominate their space in such segments as automotive, mil/aero and medical are also doing quite well, while non-leaders find rough waters.”
Performance of FinFETs
Have FinFETs gone to below 20nm? Also, are those looking for power reduction now benefiting?
He added that 20nm was a pivotal point in advanced process development. The 20nm process node’s new set of challenges, including double patterning and very leaky transistors due to short channel effects, negated the benefits of transistor scaling.
To further complicate matters, the migration from 28nm to 20nm lacked the performance and area gains seen with prior generations, making it economically questionable. While planar FET may be nearing the end of its scalable lifespan at 20nm, FinFETs provide a viable alternative for advanced processes at emerging nodes.
The industry’s experience with 20nm paved the way for an easier FinFET transition. FinFET processes are in production today, and many IC design companies are rapidly moving to manufacture their devices on the emerging 16nm and 14nm FinFET-based process geometries due to the compelling power and performance benefits. Numerous test chips have taped out, and results are coming in.
“FinFET is delivering on its promise of power reduction. With 20nm planar FET technologies, leakage current can flow across the channel between the source and the drain, making it very difficult to completely turn the transistor off. FinFETs provide better channel control, allowing very little current to leak when the device is in the “off” state. This enables the use of lower threshold voltages, resulting in better power and performance. FinFET devices also operate at a lower nominal voltage supply, significantly improving dynamic power.”
What are the top five trends likely to rule the semicon industry in 2014 and why? Rich Goldman, VP, corporate marketing and strategic alliances, Synopsys, had this to say.
FinFETs will be a huge trend through 2014 and beyond. Semiconductor companies will certainly keep us well informed as they progress through FinFET tapeouts and ultimately deliver production FinFET processes.
They will tout the power and speed advantages that their FinFET processes deliver for their customers, and those semiconductor companies early to market with FinFETs will press their advantage by driving and announcing aggressive FinFET roadmaps.
IP and subsystems
As devices grow more complex, integrating third-party IP has become mainstream. Designers recognize as a matter of course that today’s complex designs benefit greatly from integrating third-party IP in such areas as microprocessors and specialized I/Os.
The trend for re-use is beginning to expand upwards to systems of integrated, tested IP so that designers no longer need to redesign well-understood systems, such as memory, audio and sensor systems.
Internet of Things/sensors
Everybody is talking about the Internet of Things for good reason. It is happening, and 2014 will be a year of huge growth for connected things. Sensors will emerge as a big enabler of the Internet of Things, as they connect our real world to computation.
Beyond the mobile juggernaut, new devices such as Google’s (formerly Nest’s) thermostat and smoke detector will enter the market, allowing us to observe and control our surrounding environment remotely.
The mobile phone will continue to subsume and disrupt markets, such as cameras, fitness devices, satellite navigation systems and even flashlights, enabled by sensors such as touch, capacitive pattern, gyroscopic, accelerometers, compasses, altimeters, light, CO, ionization etc. Semiconductor companies positioned to serve the Internet of Things with sensor integration will do well.
Systems companies bringing IC design in-house
Large and successful systems companies wanting to differentiate their solutions are bringing IC specification and/or design in house. Previously, these companies were focused primarily on systems and solutions design and development.
Driven by a belief that they can design the best ICs for their specific needs, today’s large and successful companies such as Google, Microsoft and others are leading this trend, aided by IP reuse.
Advanced designs at both emerging and established process nodes
While leading-edge semiconductor companies drive forward on emerging process nodes such as 20nm, others are finding success by focusing on established nodes (28nm and above) that deliver required performance at reduced risk. Thus, challenging designs will emerge at both ends of the spectrum.
Part II of this discussion will look at FinFETs below 20nm and 3D ICs.
I had interacted with Dr. Ajoy Bose, CEO of Atrenta, some months ago. It was a pleasure to meet up with Piyush Sancheti, VP of Marketing recently. First, I asked him about the outlook for EDA in 2014.
Outlook for EDA
Piyush Sancheti said: “EDA does not look that attractive from growth point. However, you cannot do SoC designs without EDA. Right now, EDA’s focus is on implementation. The re-use of IP has been doing the rounds for many years. Drivers for SoCs are mobile and Internet of Things. The design cycle for those markets are very short – about three months. EDA business is shifting to IP re-use. The focus is now toward design aggregation.
“We will have done roughly 66 percent of business – net new — on existing customers. There is an industry shift toward doing more on the front end. EDA growth will come from IP-SoC involvement.
“Sub-20nm has challenges. ST says FT-SoI is the way to go. Complexity of process plays a big role, and the amount of chips you put in will also increase. In 14/16nm, we have an investment going on in 3D design. We are extending our 2D tool into 3D tool. We are also investing in the IP qualification. We have standardized a set of design rules in RTL. There are about 30 companies in the TSMC ecosystem.
“Our main focus is IP enablement. SoC acceptance is another key aspect. Our company focus is IP-enablement for SoCs. IP qualification ensures that it meets guidelines. Second, acceptance and making sure all IPs fit in the blocks. Third, integration. We already have this technology and it is driving the business.”
What’s Atrenta’s take on 3D design? Sancheti replied: “The industry has been slow as 3D designs are not yet to a point of business success. Focus on monolithic 3D-ICs will be a paradigm shift for the semicon industry. For mainstream commercial design, 20nm is still mainstream, but 14/16nm does not look mainstream, as of now. Process node is not necessarily a driver of innovation. EDA as an industry will remain in single digit growth.”
How will EDA move into the embedded software space?
Sancheti said: “We’ve looked into that market. But, the price point is significantly lower. Over time, it could be a strategic area for us. Over time, embedded software development and chip design will co-mingle.”
ESL is where the future of EDA lies. Still true? He added that the future of EDA is going up. It has to head toward integration of embedded software and chip development. However, ESL is not the only viable option.
Atrenta has 220 people in India, about 10 people in Bangalore and 200 in Noida. Sushil Gupta runs the India operations. It has tie-ups with IIT Delhi and IIT Kharagpur as well. Atrenta sees lot of scope for work with the Indian start-ups.
The year 2014 is expected to be a major year for the global semiconductor industry. The industry will and continue to innovate!
Apparently, there are huge expectations from certain segments such as the so-called Internet of Things (IoT) and wearable electronics. There will likely be focus on the connected car. Executives have been stating there could be third parties writing apps that can help cars. Intel expects that technology will be inspiring optimism for healthcare in future. As per a survey, 57 percent of people believe traditional hospitals will be obsolete in the future.
Some other entries from 2013 include Qualcomm, who introduced the Snapdragon 410 chipset with integrated 4G LTE world mode for high-volume smartphones. STMicroelectronics joined ARM mbed project that will enable developers to create smart products with ARM-based industry-leading STM32 microcontrollers and accelerate the Internet of Things.
A look at the industry itself is interesting! The World Semiconductor Trade Statistics Inc. (WSTS) is forecasting the global semiconductor market to be $304 billion in 2013, up 4.4 percent from 2012. The market is expected to recover throughout 2013, driven mainly by double digit growth of Memory product category. By region, all regions except Japan will grow from 2012. Japan market is forecasted to decline from 2012 in US dollar basis due to steep Japanese Yen depreciation compared to 2012.
WSTS estimates that the worldwide semiconductor market is predicted to grow further in 2014 and 2015. According to WSTS, the global semiconductor market is forecasted to be up 4.1 percent to $317 billion in 2014, surpassing historical high of $300 billion registered in 2011. For 2015, it is forecasted to be $328 billion, up 3.4 percent.
All product categories and regions are forecasted to grow positively in each year, with the assumption of macro economy recovery throughout the forecast period. By end market, wireless and automotive are expected to grow faster than total market, while consumer and computer are assumed to remain stagnant.
Now, all of this remains to be seen!
Earlier, while speaking with Dr. Wally Rhines of Mentor, and Jaswinder Ahuja of Cadence, both emphasized the industry’s move to 14/16nm. Xilinx estimates that 28nm will have a very long life. It also shipped the 20nm device in early Nov. 2013.
In a 2013 survey, carried out by KPMG, applications markets identified as most important by at least 55 percent of the respondents were: Mobile technology – 69 percent; Consumer – 66 percent; Computing – 63 percent; Alternative/Renewal Energy – 63 percent; Industrial – 62 percent; Automotive – 60 percent; Medical – 55 percent; Wireline Communications – 55 percent.
Do understand that there is always a line between hope and forecasts, and what the end result actually turns out to be! In the meantime, all of us continue to live with the hope that the global semiconductor will carry on flourishing in the years to come. As Brian Fuller, Cadence, says, ‘the future’s in our hands; let’s not blow it!’
The WordPress.com stats helper monkeys prepared a 2013 annual report for this blog. Thanks a lot, WordPress!
Here’s an excerpt:
The Louvre Museum has 8.5 million visitors per year. This blog was viewed about 73,000 times in 2013. If it were an exhibit at the Louvre Museum, it would take about 3 days for that many people to see it.
I was pointed out to a piece of news on TV, where a ruling chief minister of an Indian state apparently announced that he could make a particular state of India another Silicon Valley! Interesting!!
First, what’s the secret behind Silicon Valley? Well, I am not even qualified enough to state that! However, all I can say is: it is probably a desire to do something very different, and to make the world a better place – that’s possibly the biggest driver in all the entrepreneurs that have come to and out of Silicon Valley in the USA.
If you looked up Wikipedia, it says that the term Silicon Valley originally referred to the region’s large number of silicon chip innovators and manufacturers, but eventually, came to refer to all high-tech businesses in the area, and is now generally used as a metonym for the American high-technology sector.
So, where exactly is India’s high-tech sector? How many Indian state governments have even tried to foster such a sector? Ok, even if the state governments tried to foster, where are the entrepreneurs? Ok, an even easier one: how many school dropouts from India or even smal-time entrepreneurs have even made a foray into high-tech?
Right, so where are the silicon chip innovators from India? Sorry, I dd not even hear a word that you said? Can you speak out a little louder? It seems there are none! Rather, there has been very little to no development in India, barring the work that is done by the MNCs. Correct?
One friend told me that Bangalore is a place that can be Silicon Valley. Really? How?? With the presence of MNCs, he said! Well, Silicon Valley in the US does not have MNCs from other countries, are there? Let’s see! Some companies with bases in Silicon Valley, listed on Wikipedia, include Adobe, AMD, Apple, Applied Materials, Cisco, Facebook, Google, HP, Intel, Juniper, KLA-Tencor, LSI, Marvell, Maxim, Nvidia, SanDisk, Xilinx, etc.
Now, most of these firms have setups in Bangalore, but isn’t that part of the companies’ expansion plans? Also, I have emails and requests from a whole lot of youngsters asking me: ‘Sir, please advice me which company should I join?’ Very, very few have asked me: ‘Sir, I have this idea. Is it worth exploring?’
Let’s face the truth. We, as a nation, so far, have not been one to take up challenges and do something new. The ones who do, or are inclined to do so, are working in one of the many MNCs – either in India or overseas.
So, how many budding entrepreneurs are there in India, who are willing to take the risk and plunge into serious R&D?
It really takes a lot to even conceive a Silicon Valley. It takes people of great vision to build something of a Silicon Valley, and not the presence of MNCs.
Just look at Hsinchu, in Taiwan, or even Shenzhen, in China. Specifically, look up Shenzhen Hi-Tech Industrial Park and the Hsinchu Science Park to get some ideas.
Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.
Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.
Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.
“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”
When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.
Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.
The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.
Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.
Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.
FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?
Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.
Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.