Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.
The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.
At Cadence, the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.
What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.
On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.
Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI).
Complexity is growing exponentially and signoff is the bottleneck. There is an increasing design complexity. Low power is important across markets — from smartphones to datacenters. Time to market remains critical as well. Feature-rich devices are growing the design size.
Timing closure schedule and complexity have been increasing. In fact, up until now, timing closure solutions are said to have not kept pace with design complexity. The number of timing views are increasing with each new process node. The increased margins make timing closure very difficult. Exponential growth in design size and complexity are stretching the analysis capacity. Time in signoff closure has been increasing up to 40 percent of the design flow at 20nm.
The Tempus timing signoff solution is big on performance, accuracy and closure. For performance, it facilitates massively parallelized computation, is scalable to 100s of CPUs and there are optimized data structures. It allows up to 10X faster path-based analysis (PBA) and advanced process modeling for accuracy. Finally, for closure, it provides up to 10X reduction in closure time, is placement and routing aware and offers unlimited MMMC capacity.
Tempus offers an unprecedented performance, and handles 100s of millions of cells flat! It has an innovative hierarchical/incremental analysis. For design closure, the multi-mode, multi-corner (MMMC) is distributed or concurrent. There is physically aware optimization, such as graph- or path-based. The PBA is a detailed view of timing based on slew propagation.
With Tempus, Cadence is solving the design complexity challenge by eliminating the signoff bottleneck and enabling customers to meet power, performance and time-to-market goals.
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.
How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.
Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.
The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.
IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.
Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.
The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.
Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash.
With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto infotainment and home applications.
The Tensilica IP also complements industry-standard processor architectures, providing application-optimized subsystems to increase differentiation and get to market faster. Finally, over 200 licensees, including system OEMs and seven of the top 10 semiconductor companies, have shipped over 2 billion Tensilica IP cores.
Talking about the rationale behind Cadence acquiring Tensilica, Pankaj Mayor, VP and head of Marketing, Cadence, said: “Tensilica fits and furthers our IP strategy – the combination of Tensilica’s DPU and Cadence IP portfolio will broaden our IP portfolio. Tensilica also brings significant engineering and management talent. The combination will allow us to deliver to our customers configurable, differentiated, and application-optimized subsystems that improve time to market.”
It is expected that the Cadence acquisition will also see the Tensilica dataplane IP to complement Cadence and Cosmic Circuits’ IP. Cadence had acquired Cosmic Circuits in February 2013.
What are the possible advantages of DPUs over DSPs? Does it mean a possible end of the road for DSPs?
As per Mayor, DSPs are special purpose processors targeted to address digital signaling. Tensilica’s DPUs are programmable and customizable for a specific function, providing optimal data throughput and processing speed; in other words, the DPUs from Tensilica provide a unique combination of customized processing, plus DSP. Tensilica’s DPUs can outperform traditional DSPs in power and performance.
So, what will happens to the MegaChips design center agreement with Tensilica? Does it still carry on? According to Mayor, right now, Cadence and Tensilica are operating as two independent companies and therefire, Cadence cannot comment until the closing of the acquisition, which is in 30-60 days.
Happy new year to everyone! Here is an outlook for the electronics and semiconductors sectors in 2013, provided by Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems (India) Pvt Ltd. (Thanks a lot, Pallavi).
First, the past year, 2012, in review.
Globally, 2012 has been a challenging year for the semiconductor industry with the economic slump in Europe and the US. However, the long term outlook remains positive, with Gartner reporting that the growth in the electronics and semiconductor industries will outpace world GDP growth till 2016.
In India, the ambiguity around the telecom market, traditionally the biggest consumer of semiconductor equipment, was the main handicap to growth. On the positive side, the passing of the National Policy on Electronics (NPE) in 2012 promises a much-needed fillip to the electronics ecosystem. In 2013 we expect to see a positive impact in terms of home-grown electronics thanks to the provisions of the Policy.
Worldwide technology trends in 2013
User experience is the driving force behind many of the semiconductor design trends that we will see in 2013 and beyond. Consumers are demanding devices on which games, music, cameras, internet, and other apps all run simultaneously and seamlessly. As a result, mobility, application-driven design, video, cloud and security, all of which enable an enhanced user experience, are the drivers of the electronics and semiconductor world today.
Mobility is the single biggest driver for the semiconductor industry. The pervasiveness of mobility does not only affect the telecommunications industry, but also entertainment, home electronics, automotive and medical electronics.
For example, cutting edge mobile solutions in the healthcare field include devices that can monitor blood pressure and blood sugar levels remotely, and then transmit the readings to the physician for diagnosis and treatment; in the automotive sector, in-vehicle infotainment is expected to be the next big thing and end-consumers can look forward to real-time traffic reports, weather information, and entertainment options from next-generation cars.
Mobility has fundamentally altered how we produce and consume information. In the future, we can expect that devices will go one step further and actually interact intelligently with the user – we see the first steps of that with Apple’s Siri software.
Mobility has also created a completely new market for applications that enable a more interactive and satisfying user experience. It is via applications that system companies differentiate themselves and stand apart from the competition. The need to have applications on all kinds of devices is posing unique challenges to the semiconductor and EDA companies.
Whereas traditionally the hardware (silicon) was built first and then the software was added later, now developing the software and designing the hardware are becoming a parallel process. This gives rise to new EDA technologies that enable early software development using software models of system hardware long before silicon is ready. We will see this new way of designing continue to be a challenge going into 2013.
Per reports from Cisco, video will soon drive more than 90 percent of all global traffic on the Internet. As more and more entertainment and collaboration tools are launched, bandwidth-hungry video traffic will drive growth both in the end consumer market (mobile platforms) and the enterprise space (networking industry).
The cloud is closely intertwined with the growth in mobility – it is the cloud of network servers and backbone equipment that deliver the content and value to all mobile devices. For every 600 smart phones and every 120 tablets, one dedicated server is needed. With the demand for mobiles showing accelerated growth, the need for cloud computing technologies will be another key driver for the semiconductor industry.
Security underpins our information age. The vast amount of data residing in mobile platforms and cloud architectures is extremely vulnerable. As we move into 2013, we foresee a sharper focus on securing data and critical infrastructure from theft and hacker attacks.
How will 2013 turn out to be for the global semiconductor industry? Will there be growth for the global EDA industry? Importantly, how will the Indian semiconductor industry perform in 2013? I asked Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems India these questions.
Outlook for global semicon industry in 2013
First, how is the outlook for global semiconductor industry in 2013 going to be? Ahuja said: “The long term outlook for the semiconductor industry remains positive, with mobility and cloud computing being the key drivers. The global economy is forecast to grow around 4 percent annually through 2016, according to an April 2012 report from the International Monetary Fund (IMF).
“In its June 2012 report, Gartner predicted growth in electronics and semiconductor industries to outpace that of the world GDP growth, at 5½ percent annually to approach $2 trillion for electronics and 6 percent annually for semiconductors through 2016. So, the semiconductor industry outlook remains very positive overall.
“In the near term, multiple challenges will need to be weathered with respect to the global economic climate, especially in European markets. The JP Morgan/GSA Semiconductor Index of Leading Indicators points to a soft semiconductor industry in 2013. However, there are lot of new products in the mobile and tablet space that are driving demand, such as the iPhone 5, Microsoft Surface, and Samsung Galaxy S III.
“The China semiconductor space is emerging as a key market for semiconductor company revenue, and forecasts predict that it will show rapid annual growth rate. The consolidation and M&A activities that we are seeing in the global semiconductor industry also indicate a positive outlook for the upcoming year.
“In India as well, the semiconductor industry will continue to see growth. The injection of funds and other support outlined in the National Policy on Electronics will provide an impetus to home-grown design and manufacturing, which should start gaining traction in 2013.”
Five trends for 2013
What would be the three or five trends likely to be visible in 2013? Ahuja said Cadence sees five big trends that will drive growth in the near and long term. These are: mobility, application driven design, video, cloud and security.
Probably, the most pervasive change in electronics recently has been mobility. When we talk about mobility, it’s just not about smart phones or tablets, but any kind of device which is mobile. Within the mobile space, software applications help system manufacturers and vendors differentiate themselves and stand apart from the competition. The need to have apps on all kinds of devices is driving rapid growth, as well as placing new demands on EDA companies.
The entertainment industry will be the key driver for video, and as the year progresses, we will continue to see more and more products and solutions introduced to tap into the demand. For the semiconductor industry, video will drive growth both in the end consumer market (mobile platforms) and the enterprise space (networking industry).
In many ways, the backbone to mobility is the cloud. With its network servers and infrastructure, the cloud is what delivers much of the content and value to all of those mobile devices. Statistics show that we need one server for every 600 smart phones and one for every 120 tablets. So there is a big need for data centers which can provide support for all the computing and back-end operations.
Security of data in mobile devices and the cloud will continue to be a challenge in the near future. There will be renewed calls to develop products that can protect critical infrastructure and sensitive information from security breaches.
Cadence Design Systems Inc. has released the Allegro/OrCAD 16.6 that provides unmatched, scalable design solutions addressing technology challenges.
Allegro is meant for simple to more complex boards, for the geographically dispersed design teams. They also cater to the personal productivity needs for start-ups and small to medium companies. It provides high-speed, power aware SI, HDI managed design environments, that is meant for medium to large enterprises.
Allegro, Sigrity and OrCAD – major themes of Allegro PCB 16.6
The major themes of Allegro PCB 16.6 include the first ECAD collaborative environment for work-in-progress (WiP) PCB design using Microsoft SharePoint. It accelerates the timing closure for high-speed interfaces such as DDRx. There is support for advanced miniaturization techniques that embed passive and active components on inner layers of a PCB.
Regarding the percentage of enhanced miniaturization capabilities for embedding dual-sided and vertical components, Hemant Shah, product marketing director, Allegro PCB and FPGA Products, Cadence, said: “Components with dual-sided contacts offer customers the ability to connect to the components pins through the layer above or through the layer below. This provides routing flexibility. It also allows customers who want redundant connections on inner layers.”
There can be accelerated design implementation through flexible PCB team design capability. Leveraging GPUs for faster display, you can pan and zoom on dense PCBs, enabling greater design productivity.
Typical product creation environment includes the best-in-class hardware design environment for implementation, analysis and compliance sign-off. The design team collaboration capability encompasses design-chain partners. Design data can be integrated into corporate systems to manage cost and quality, and provide visibility. It allows on-time release into manufacturing to build products.
Allegro, OrCAD and Sigrity ensure product creation with the best-in-class PCB design environment. Design team collaboration and productivity is integrated at the PCB. Design data integration is done into corporate systems to manage cost and quality. There is on-time release into manufacturing to build products. Allegro, OrCAD and Sigrity are helping create market leading products.
Users can create the first ECAD collaborative environment using Microsoft SharePoint. Design creation and collaboration trends include geographically distributed teams, increase in outsourcing (OEMs-ODMs), product life cycle management tools are not designed/targeted for managing work-in-progress data. For every design engineer, there are 3X-5X collaborators, reviewers, etc.
The Allegro Design workbench integrates seamlessly to SharePoint 2010. The Team Design Authoring cockpit facilitates design data in and out of SharePoint providing WiP design data management. There is block level check-in, check-out, etc. SharePoint is already deployed in many companies. It is scalable from single server to cloud environment. It has rich platform for power users to configure and developers to customize.
By creating the first ECAD collaborative environment, users can reduce the product creation time by up to 40 per cent. Chances of first pass failure are also reduced from 25 per cent to 1 per cent. Users can accelerate the timing closure on high-speed, multi-Gigabit signals.
Cadence Design Systems recently introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers.
Rahul Deokar, product management director, said: “We are addressing designer challenges in – high performance design, giga-scale design and advanced node design. The first challenge is the PPA – power performance and area. Next challenge is to handle giga-scale designs with efficient turnaround time. The third key challenge is fast time-to-market on advanced 28nm/20nm design.”
With this latest release, Cadence provides the industry’s best PPA. Second, it is providing 1 billion gates on designer desktops. Third, it provides the fastest path to 20nm digital design. In the new announcement, there are three new technologies – GigaOpt + CCOpt, GigaFlex, and 20nm double patterning.
Cadence has introduced “GigaOpt” – a common optimization engine that unifies physical synthesis and optimization. GigaOpt provides designers globally optimal results across the front-end and back-end of the design flow. And that results in the benefit of the industry’s best PPA for high-performance design. GigaOpt has been designed from scratch to be multi-threaded, which makes it ultra fast and ultra scalable.
Another innovation, CCOpt, is the first and only technology in EDA to unify clock tree synthesis and physical optimization. CCOpt is now an integral part of the Encounter flow accelerating design closure with the best PPA. CCOpt facilitates:
* 10 percent improvement in design performance and total power.
* 30 percent reduction in clock power and area.
* 30 percent reduction in IR drop.
The Encounter flow now allows 1 billion gates to be enabled on the designer’s desktops. This is done with the new GigaFlex abstraction technology. It is the first and only technology in EDA that enables flexible, accurate abstraction adaptable to the flow stage. There is 10X capacity and TAT gains on 100 million+ instance designs. GigaFlex abstraction technology allows accurate, early physical modeling, concurrent top-and-block interface optimization, and concurrent hierarchical closure and late-stage ECO. Read more…