Archive

Archive for the ‘EDA tools’ Category

Cadence Quantus solution meets 16nm FinFET challenges


Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET.

So, what’s the uniqueness about the Cadence Quantus QRC extraction solution?

Quantus

Quantus

KT Moore, senior group director – Product Marketing, Digital and Signoff Group, Cadence Design Systems, said: “There are several parasitic challenges that are associated with advanced node designs — especially FinFET – and it’s not just about tighter geometries and new design rules. We can bucket these challenges into two main categories: increasing complexity and modeling challenges.

“The number of process corners is exploding, and for FinFET devices specifically, there is an explosion in the parasitic coupling capacitances and resistances. This increases the design complexity and sizes. The netlist is getting bigger and bigger, and as a result, there is an increase in extraction runtimes for SoC designs and post-layout simulation and characterization runtimes for custom/analog designs.

“Our customers consistently tell us that, for advanced nodes, and especially for FinFET designs, while their extraction runtimes and time-to-signoff is increasing, their actual time-to-market is shrinking and putting an enormous amount of pressure on designers to deliver on-time tapeout. In order to address these market pressures, we have employed the massively parallel technology that was first introduced in our Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution to our next-generation extraction tool, Quantus QRC Extraction Solution.

“Quantus QRC Extraction Solution enables us to deliver up to 5X better performance than competing solutions and allows scalability of up to 100s of CPUs and machines.”

Support for FinFET features
How is Quantus providing significant enhancements to support FinFET features?

Parasitic extraction is at the forefront with the introduction of any new technology node. For FinFET designs, it’s a bit more challenging due to the introduction of non-planar FinFET devices. There are more layers to be handled, more RC effects that need to be modeled and an introduction of local interconnects. There are also secondary and third order manufacturing effects that need to modeled, and all these new features have to be modeled with precise accuracy.

Performance and turnaround times are absolutely important, but if you can’t provide accuracy for these devices — especially in correlation to the foundry golden data — designers would have to over-margin their designs and leave performance on the table.

Best-in-class accuracy
How can Cadence claim that it has the ‘tightest correlation to foundry golden data at TSMC vs. competing solutions’? And, why 16nm only?

According to Moore, the foundry partner, TSMC, asserts that Quantus QRC Extraction Solution provides best-in-class accuracy, which was referenced in the recent press announcement:

“Cadence Quantus QRC Extraction Solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.”

FinFET structures present unique challenges since they are non-planar devices as opposed to its CMOS predecessor, which is a planar device. We partnered with TSMC from the very beginning to address the modeling challenges, and we’ve seen many complex shapes and structures over the year that we’ve modeled accurately.

“We’re not surprised that TSMC has recognized our best-in-class accuracy because we’re the leader in providing extraction solutions for RF designs. Cadence Quantus QRC Extraction Solution has been certified for TSMC 16nm FinFET, however, it’s important to note that we’ve been certified for all other technology nodes and our QRC techfiles are available to our customers from TSMC today.”

Cadence: Plan verification to avoid mistakes!


Apurva Kalia

Apurva Kalia

Following Mentor Graphics, Cadence Design Systems Inc. has entered the verification debate. ;)  I met Apurva Kalia, VP R&D – System & Verification Group, Cadence Design Systems. In a nutshell, he advised that there needs to be proper verification planning in order to avoid mistakes. First, let’s try to find out the the biggest verification mistakes.

Top verification mistakes
Kalia said that the biggest verification mistakes made today are:
* Verification engineers do not define a structured notion of verification completeness.
* Verification planning is not done up front and is carried out as verification is going along.
* A well-defined reusable verification methodology is not applied.
* Legacy tools continue to be used for verification; new tools and technologies are not adopted.

In that case, why are some companies STILL not knowing how to verify a chip?

He added: “I would not describe the situation as companies not knowing how to verify a chip. Instead, I think a more accurate description of the problem is that the verification complexity has increased so much that companies do not know how to meet their verification goals.

“For example, the number of cycles needed to verify a current generation processor – as calculated by traditional methods of doing verification – is too prohibitive to be done in any reasonable timeframe using legacy verification methodologies. Hence, new methodologies and tools are needed. Designs today need to be verified together with software. This also requires new tools and methodologies. Companies are not moving fast enough to define, adopt and use these new tools and methodologies thereby leading to challenges in verifying a chip.”

Addressing challenges
How are companies trying to address the challenges?

Companies are trying to address the challenges in various ways:
* Companies at the cutting edge of designs and verification are indeed trying to adopt structured verification methodologies to address these challenges.

* Smaller companies are trying to address these challenges by outsourcing their verification to experts and by hiring more verification experts.

* Verification acceleration and prototyping solutions are being adopted to get faster verification and which will allow companies to do more verification in the same amount of time.

* Verification environment re-use helps to cut down the time required to develop verification environments.

* Key requirements of SoC integration and verification—including functionality, compliance, power, performance, etc.—are hardware/software debug efficiency, multi-language verification, low power, mixed signal, fast time to debug, and execution speed.

Cadence has the widest portfolio of tools to help companies meet verification challenges, including:

Incisive Enterprise Manager, which provides hierarchical verification technology for multiple IPs, interconnects, hardware/software, and plans to improve management productivity and visibility;

The recently launched vManager solution, a verification planning and management solution enabled by client/server technology to address the growing verification closure challenge driven by increasing design size and complexity;

Incisive Enterprise Verifier, which delivers dual power from tightly integrated formal analysis and simulation engines; and

Incisive Enterprise Simulator, which provides the most comprehensive IEEE language support with unique capabilities supporting the intent, abstraction, and convergence needed to speed silicon realization.

Are companies building an infrastructure that gets you business advantage? Yes, companies are realizing the problems. It is these companies that are the winners in managing today’s design and verification challenges, he said.

Good verification
When should good verification start?

Kalia noted: “Good verification should start right at the time of the high level architecture of the design. A verification strategy should be defined at that time, and an overall verification plan should be written at that time. This is where a comprehensive solution like Incisive vManager can help companies manage their verification challenges by ensuring that SoC developers have a consistent methodology for design quality enhancements.”

Are folks mistaking by looking at tools and not at the verification process itself?

He addded that right tools and methodology are needed to resolve today’s verification challenges. Users need to work on defining verification methodologies and at the same time look at the tools that are needed to achieve verification goals.

Verification planning
Finally, there’s verification planning! What should be the ‘right’ verification path?

Verification planning needs to include:

* A formal definition of verification goals;
* A formal definition of coverage goals at all levels – starting with code coverage all the way to functional coverage;
* Required resources – human and compute;
* Verification timelines;
* All the verification tools to be used for verification; and
* Minimum and maximum signoff criteria.

India’s evolving importance to future of fabless: Dr. Wally Rhines

February 3, 2014 2 comments

Dr. Wally RhinesIf I correctly remember, sometime in Oct. 2008, S. Janakiraman, then chairman of the India Semiconductor Association, had proclaimed that despite not having fabs, the ‘fabless India” had been shining brightly! Later, in August 2011, I had written an article on whether India was keen on going the fabless way! Today, at the IESA Vision Summit in Bangalore, Dr, Wally Rhines repeated nearly the same lines!

While the number of new fabless startups has declined substantially in the West during the past decade, they are growing in India, said Dr. Walden C. Rhines, chairman and CEO, during his presentation “Next Steps for the Indian Semiconductor Industry” at the ongoing IESA Vision Summit 2014.

India has key capabilities to stimulate growth of semiconductor companies, which include design services companies, design engineering expertise and innovation, returning entrepreneurs, and educational system. Direct interaction with equipment/systems companies will complete the product development process.

Off the top 50 semicon companies in 2012, 13 are fabless and four are foundries. The global fabless IC market is likely to grow 29 percent in 2013. The fabless IC revenue also continues to grow, reaching about $78.1 billion in 2013.  The fabless revenue is highly concentrated with the top 10 companies likely to account for 64 percent revenue in 2013. As of 2012, the GSA estimates that there aere 1,011 fabless companies.

The semiconductor IP (SIP) market has also been growing and is likely to reach $4,774 million by 2020, growing at a CAGR of 10 percent. The top 10 SIP companies account for 87 percent of the global revenue. Tape-outs at advanced nodes have been growing. However, there are still large large opportunities in older technologies.

IoT will transform industry
It is expected that the Internet of Things (IoT) will transform the semiconductor industry. It is said that in the next 10 years, as many as 100 billion objects could be tied together to form a “central nervous system” for the planet and support highly intelligent web-based systems. As of 2013, 1 trillion devices are connected to the network.

Product differentiation alone makes switching analog/mixed-signal suppliers difficult. Change in strategy toward differentiation gradually raises GPM percentage.

India’s evolving importance to future of fabless
Now, India ranks among the top five semiconductor design locations worldwide. US leads with 507, China with 472, Taiwan with 256, Israel with 150, and India with 120. Some prominent Indian companies are Ineda, Saankhya Labs, Orca Systems and Signal Chip (all fabless) and DXCorr and SilabTech (all SIP).

India is already a leading source of SIP, accounting for 5.3 percent, globally, after USA 43 percent and China 17.3 percent, respectively. It now seems that India has been evolving from design services to fabless powerhouse. India has built a foundation for a fabless future. It now has worldwide leadership with the most influential design teams in the world.

Presently, there are 1,031 MNC R&D centers in India. Next, 18 of the top 20 US semiconductor companies have design centers in India. And, 20 European corporations set up engineering R&D centers in India last year. India also has the richest pool of creative engineering resources and educational institutions in the world. The experience level of Indian engineers has been increasing, but it is still a young and creative workforce. There is also a growing pool of angel investors in India, and also in the West, with strong connections to India.

So, what are the key ingredients to generate a thriving infrastructure? It is involvement and expertise with end equipment. Superb product definition requires the elimination of functional barriers. He gave some examples of foreign “flagged” Indian companies that produced early successes. When users and tool developers work in close proximity, “out-of-the-Box” architectural innovations revolutionize design verification.

What does it take to create Silicon Valley!

December 29, 2013 1 comment

I was pointed out to a piece of news on TV, where a ruling chief minister of an Indian state apparently announced that he could make a particular state of India another Silicon Valley! Interesting!!

First, what’s the secret behind Silicon Valley? Well, I am not even qualified enough to state that! However, all I can say is: it is probably a desire to do something very different, and to make the world a better place – that’s possibly the biggest driver in all the entrepreneurs that have come to and out of Silicon Valley in the USA.

If you looked up Wikipedia, it says that the term Silicon Valley originally referred to the region’s large number of silicon chip innovators and manufacturers, but eventually, came to refer to all high-tech businesses in the area, and is now generally used as a metonym for the American high-technology sector.

So, where exactly is India’s high-tech sector? How many Indian state governments have even tried to foster such a sector? Ok, even if the state governments tried to foster, where are the entrepreneurs? Ok, an even easier one: how many school dropouts from India or even smal-time entrepreneurs have even made a foray into high-tech?

Right, so where are the silicon chip innovators from India? Sorry, I dd not even hear a word that you said? Can you speak out a little louder? It seems there are none! Rather, there has been very little to no development in India, barring the work that is done by the MNCs. Correct?
hsinchuOne friend told me that Bangalore is a place that can be Silicon Valley. Really? How?? With the presence of MNCs, he said! Well, Silicon Valley in the US does not have MNCs from other countries, are there? Let’s see! Some companies with bases in Silicon Valley, listed on Wikipedia, include Adobe, AMD, Apple, Applied Materials, Cisco, Facebook, Google, HP, Intel, Juniper, KLA-Tencor, LSI, Marvell, Maxim, Nvidia, SanDisk, Xilinx, etc.

Now, most of these firms have setups in Bangalore, but isn’t that part of the companies’ expansion plans? Also, I have emails and requests from a whole lot of youngsters asking me: ‘Sir, please advice me which company should I join?’ Very, very few have asked me: ‘Sir, I have this idea. Is it worth exploring?’

Let’s face the truth. We, as a nation, so far, have not been one to take up challenges and do something new. The ones who do, or are inclined to do so, are working in one of the many MNCs – either in India or overseas.

So, how many budding entrepreneurs are there in India, who are willing to take the risk and plunge into serious R&D?

It really takes a lot to even conceive a Silicon Valley. It takes people of great vision to build something of a Silicon Valley, and not the presence of MNCs.

Just look at Hsinchu, in Taiwan, or even Shenzhen, in China. Specifically, look up Shenzhen Hi-Tech Industrial Park and the Hsinchu Science Park to get some ideas.

How’s global semicon industry performing in sub-20nm era?


Early this month, I caught up with Jaswnder Ahuja, corporate VP and MD, Cadence Desiign Systems India. With the global semiconductor industry having entered the sub-20nm era, there are a lot of things happening, and Cadence is sure to be present.

Performance in sub-2onm era
First, let’s see how’s the global semiconductor industry performing after entering the sub-20nm era.

Jaswinder Ahuja

Jaswinder Ahuja

Ahuja replied: “Increased demand for faster, smaller, low-power chips continues to drive the geometry shrink as one of the ways to manage the low-power, higher performance goals in smaller form factors—in other words, PPA is driving the move to advanced node design.

“At Cadence, we are seeing a lot of interest in the wireless space, which includes smartphones, tablets, and consumer devices. In this market, you must support different standards, the device must be really fast, it must have Internet access, and all this must be done at lower power so the that it does not drain the battery. We’re also seeing interest for advanced nodes in other segments such as computing and graphics processors.”

When speaking of advanced nodes, let’s also try and find out what Cadence is doing in helping achieve 10X faster power integrity analysis and signoff.

Cadence Voltus IC power integrity Solution is a full-chip, cell-level power signoff tool that provides accurate, fast, and high-capacity analysis and optimization technologies to designers for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration (EM) constraints and violations.

The Voltus solution includes innovative technologies such as massively parallel execution, hierarchical architecture, and physically aware power grid analysis and optimization. Beneficial as a standalone power signoff tool, Voltus IC Power Integrity Solution delivers even more significant productivity gains when used in a highly integrated flow with other key Cadence products, providing the industry’s fastest design closure technology.

Developed with advanced algorithms and a new power integrity analysis engine with massively parallel execution, Voltus IC Power Integrity solution:
* Performs 10X faster than other solutions on the market.
* Supports very large designs—up to one billion instances—with its hierarchical architecture.
* Delivers SPICE-level accuracy.
* Enhances physical implementation quality via physically aware power integrity optimization.

Supported by major foundries and intellectual property (IP) providers, Voltus IC Power Integrity Solution has been validated and certified on advanced nodes processes such as 16nm FinFET and included in reference design flows such as for 3D-IC technology. Backed by Cadence’s rigorous quality control and product release procedures, the Voltus solution delivers best-in-class signoff quality on accuracy and stability for all process nodes and design technologies.

FinFETs to 20nm – are folks benefiting?
It is common news that FinFETs have gone to 20nm and perhaps, lower. Therefore, are those folks looking for power reduction now benefiting?

Ahuja replied that FinFETs allow semiconductor and systems companies to continue to develop commercially viable chips for the mobile devices that are dominating the consumer market. FinFETs enable new generations of high-density, high-performance, and ultra-low-power systems on chip (SoCs) for future smart phones, tablets, and other advanced mobile devices. Anyone who adopts FinFET technology will reap the benefits.

Foundry support for FinFETs will begin at 16nm and 14nm. In April of this year, Cadence announced a collaboration with ARM to implement the industry’s first ARM Cortex-A57 processor on TSMC’s 16nm FinFET manufacturing process. At ARM TechCon 2012, Cadence announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM’s FinFET process technology.
Read more…

Dr. Wally Rhines: Watch out for 14/16nm technologies in 2014!


Dr. Wally RhinesIt is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. The last time I met him was at Santa Cruz, USA, during a global electronics forum in April this year. First, I asked him regarding the outlook for the global semiconductor industry in 2014, as well as the EDA industry.

Outlook for global semicon industry in 2014
Dr. Rhines said: “The outlook for the global semicon industry in 2014 is modestly positive. Most analysts will see single digiit growth. In memory, we have short supply vs. demand. While we had consolidation of the wireless industry, we still have volumes of handsets, tablets, etc. In the US, tablets are said to be the biggest growth area during Xmas.

“When you look at any product, you look at what more can it do. You look at more and more features that can be added. We have speciallization in ARM-based chips. There are enough change dynamics that show demand. The iPad bridged the gap between the portable PC and phone. The infrastructure of apps has now made a huge infrastructure. If you are dependant on apps, there can be a differentiator.

“Wearable electronics is another great opportunity. However, it is still a small market. The electronic watch is interesting. We are in an era where there are some things that are key, and some require figuring out. There will be more and more need for specific devices, rather than only applications in future. The same thing was with the PC, which went from custom to specific needs.”

In that case, how is the global semiconductor industry performing having entering the sub 20nm era?

He said that 2014 is going to be a big year. There will be releases of 14/16nm technologies. This will be the year when customers will be doing tests. There are companies in all regions of the world that will be doing such stuff.

Have FinFETs gone to 20nm? Are those looking for power reduction now benefiting?

Dr. Rhines said: “The big advantage is leakage. FinFET dramatically impacts current leakage. Now, attention will shift to dynamic power. It will once again be predominantly the consumer of power in large chips.

Outlook for EDA industry
Now, let’s see what’s the outlook for the global EDA industry in 2014.

Dr. Rhines said: “Whenever you create new technologies, you will need EDA. So, EDA will grow. New designs will also need EDA. There will be new EDA tools. EDA is now addressing thermal and stress issues in verification and design. Caliber PERC is our main product here. The upgrades are good for EDA. There are new things they have to adopt, in these tools.”

Let’s talk a bit about embedded. Mentor released the new version of Sourcery CodeBench. What does it stand to gain?

Raghu Panicker, sales director, Mentor Graphics India said the Sourcery CodeBench is a real-time operating system (RTOS). That product is gaining momentum. Large MNC customers like Qualcomm are adopting this. Among small firms, there are medical, energy meter companies that are handling it as well.

Dr. Rhines added that Sorcery CodeBench is indicative of a trend – it is very open source based. It is now 20,000 downloads a month, so that is a big community.

Next is there any scope for the growth of biomems and optical telecom industry?

He said that both areas are interesting. Biomems are still a fairly small market. It is going to be evolutionary. As for optical telecom, over the last year or two, all participants have gone into a silent mode. Mentor is working with a number of customers.

Five trends to rule in 2014
Now, it was quiz time. First, the top five trends in the EDA industry during 2014. Dr. Rhines said:
* Growth of emulation for verification. The market is growing at over CAGR of 25 percent. Emulation is really big. It will be a big game changer for EDA.
* 16/14nm.
* Continued pressure on power as we go to FinFETs.
* Power reduction.
* Yield analysis for 14/16nm. A near range can be security.

Now, the top five trends for semiconductors in 2014! Dr. Rhines mentioned these as:
* Move to 14/16nm and cost.
* Growth in hybrid functions is another trend.
* Basic IoT.
* Security – how you verify designs.
* Continued commoditization of wireless apps.
Read more…

Higher levels of abstraction growth area for EDA

September 1, 2013 2 comments

Dr. Ajoy Bose

Dr. Ajoy Bose

San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.

I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”

There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.

Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.

How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.

“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”

How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.

On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.

Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth.  Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry.  At a macro level, the consumer sector will drive a lot of the growth ahead.  For EDA, the higher levels of abstraction is where the growth will be.”

Moore’s Law good for 14nm, and probably, 10nm: Dr. Wally Rhines


Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?

Dr. Wally Rhines.

Dr. Wally Rhines.

Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”

Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?

According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.

He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.

“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”

Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?

“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”

What will be the impact of transistor variability and other physics issues?

As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Read more…

Global semiconductor companies delivering platforms: Jaswinder Ahuja, Cadence


Jaswinder Ahuja.

Jaswinder Ahuja.

Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.

The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.

At Cadence,  the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.

What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.

On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.
Read more…

Cadence Tempus accelerates timing analysis and closure by weeks!


Cadence Design Systems Inc. has announced the Tempus timing signoff solution. It facilitates ground-breaking signoff timing analysis and closure. The new technology accelerates timing analysis and closure by weeks. It is said to be up to 10X faster than competing solutions. Tempus has also been endorsed by Texas Instruments (TI).

TempusComplexity is growing exponentially and signoff is the bottleneck. There is an increasing design complexity. Low power is important across markets — from smartphones to datacenters. Time to market remains critical as well. Feature-rich devices are growing the design size.

Timing closure schedule and complexity have been increasing. In fact, up until now, timing closure solutions are said to have not kept pace with design complexity. The number of timing views are increasing with each new process node. The increased margins make timing closure very difficult. Exponential growth in design size and complexity are stretching the analysis capacity. Time in signoff closure has been increasing up to 40 percent of the design flow at 20nm.

Come Tempus!
The Tempus timing signoff solution is big on performance, accuracy and closure. For performance, it facilitates massively parallelized computation, is scalable to 100s of CPUs and there are optimized data structures. It allows up to 10X faster path-based analysis (PBA) and advanced process modeling for accuracy. Finally, for closure, it provides up to 10X reduction in closure time, is placement and routing aware and offers unlimited MMMC capacity.

Tempus offers an unprecedented performance, and handles 100s of millions of cells flat! It has an innovative hierarchical/incremental analysis. For design closure, the multi-mode, multi-corner (MMMC) is distributed or concurrent. There is physically aware optimization, such as graph- or path-based. The PBA is a detailed view of timing based on slew propagation.

With Tempus, Cadence is solving the design complexity challenge by eliminating the signoff bottleneck and enabling customers to meet power, performance and time-to-market goals.

%d bloggers like this: