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Semicon West 2014: SEMI World Fab forecast report


Fabs

Fabs

Christian Gregor Dieseldorff, senior analyst, Industry Research & Statistics  Group at SEMI, presented the SEMI World Fab Forecast at the recently held Semicon West 2014, as part of the SEMI/Gartner Market Symposium on July 7.

Scenarios of fab equipment spending over time has been  20-25 percent in 2014, and 10-15 percent in 2015. At this time, worldwide fab equipment spending is about same in 1H14 vs 2H14. As for fab construction projects, 2013 was a record year with over $9 billion.

New fabs: construction spending (front end cleanrooms only!)
2013: record year with over $9 billion.
2014: -22 percent to -27 percent (~$6.6 billion)
2015: -22 percent to -30 percent (~$5 billion +/-).

Fab equipment spending front end (new and used)
2014: 20 percent to 25 percent (~$35 billion to $36 billion) – if $35 billion, then third largest on record.
2015: 10 percent to 15 percent (~$40 billion) – if $40 billion, then largest in record.

Installed capacity for front end fabs (without discretes)
2014: 2 to 3 percent
2015: 3 to 4 percent
Future outlook beyond 2015: less than 4 percent.

SEMI World Fab Forecast report status and activity outlined that there were 1,148 front end facilities (R&D to HVM) active and future. Also,
* There are 507 companies (R&D to HVM).
* Including 249 LEDs and Opto facilities active and future.
* There are 60 future facilities starting HVM in 2014 or later.
* Major investments (construction projects and/or equipping): 202 facilities in 2014, 189 facilities in 2015.

A slow down of fab closures is expected from 2015 to 2018 for 200mm fabs and 150mm fabs.

Three things in Indian semicon: Vinay Shenoy


Vinay Shenoy

Vinay Shenoy

There have been a variety of announcements made by the Government of India in the last one year or so. In the pre-90s period, the country showed just 1 percent GDP growth rate. It was adverse to FDI and had a regulated market. All of this led to deregulation under the late PM, PV Narasimha Rao.

The Indian government was averse to foreign investment, which was opened up around 1994. Since then, we have seen 6-8 percent growth, said Vinay Shenoy, MD, Infineon Technologies (India). He was delivering the keynote at the UVM 1.2 day, being held in Bangalore, India.

Around 1997, India signed the ITA-1 with the WTO. Lot of electronic items had their import duty reduced to zero. It effectively destroyed the electronics manufacturing industry in India. We were now reduced to being a user of screwdriver technology. In 1985, the National Computer Policy, and in 1986, the National Software Policy, were drafted. The government of India believed that there existed some opportunities. The STPI was also created, as well as 100 percent EoUs. So far, we have been very successful in services, but have a huge deficit on manufacturing.

We made an attempt to kick off semicon manufacturing in 2007, but that didn’t take off for several reasons. It was later revived in 2011-12. Under the latest national policy of electronics, there have been a couple announcements – one, setting up of two semicon fabs in India. The capital grant – nearly 25-27 percent — is being given by the government. It has provided a financial incentive – of about $2 billion.

Two, electronics manufacturing per se, unless it is completely an EoU, the semicon industry will find it difficult to survive. There is the M-SIPS package that offers 25 percent capital grant to a wide range of industries.

Three, we have granted some incentives for manufacturing. But, how are you going to sell? The government has also proposed ‘Made in India’, where, 30 percent of the products will be used within India. These will largely be in the government procurements, so that the BoM should be at least 30 percent from India. The preferential market policy applies to all segments, except defense.

Skill development is also key. The government has clearly stated that there should be innovation-led manufacturing. The government also wants to develop PhDs in selected domains. It intends to provide better lab facilities, better professors, etc. Also, young professors seeking to expand, can seek funding from the government.

TSMC promotes small IP companies. Similarly, it should be done in India. For semicon, these two fabs in India will likely come up in two-three years time. “Look at how you can partner with these fabs. Your interest in the semicon industry will be highly critical. The concern of the industry has been the stability of the tax regime. The government of India has assured 10 years of stable tax regime. The returns will come in 10-15 years,” added Shenoy.

The government has set up electronics manufacturing clusters (EMC). These will make it easy for helping companies to set up within the EMC. The NSDC is tying up with universities in bringing skill-sets. The industry is also defining what skills will be required. The government is funding PhDs, to pursue specialization.

Round-up 2013: Best of semiconductors, electronics and solar


Virtex UltraScale device.

Virtex UltraScale device.

Friends, here’s a review of 2013! There have been the usual hits and misses, globally, while in India, the electronics and semiconductor industries really need to do a lot more! Enjoy, and here’s wishing everyone a Very Happy and Prosperous 2014! Be safe and stay safe!!

DEC. 2013
What does it take to create Silicon Valley!

How’s global semicon industry performing in sub-20nm era?

Xilinx announces 20nm All Programmable UltraSCALE portfolio

Dr. Wally Rhines: Watch out for 14/16nm technologies in 2014!

Outlook 2014: Xilinx bets big on 28nm

NOV. 2013
Indian electronics scenario still dull: Leaptech

Connecting intelligence today for connected world: ARM

India poses huge opportunity for DLP: TI

SEMICON Europa 2013: Where does Europe stand in 450mm path?

OCT. 2013
Apple’s done it again, wth iPad Air!

IEF 2013: New markets and opportunities in sub-20nm era!

SEPT. 2013
ST intros STM32F4 series high-performance Cortex-M4 MCUs

Great, India’s having fabs! But, is the tech choice right?

G450C

G450C

Now, India to have two semicon fabs!

Higher levels of abstraction growth area for EDA

AUG. 2013
Moore’s Law could come to an end within next decade: POET

What’s happening with 450mm: G450C update and status

300mm is the new 200mm!

JULY 2013
Xilinx tapes-out first UltraScale ASIC-class programmable architecture

JUNE 2013
EC’s goal: Reach 20 percent share in chip manufacturing by 2020!
Read more…

What does it take to create Silicon Valley!

December 29, 2013 1 comment

I was pointed out to a piece of news on TV, where a ruling chief minister of an Indian state apparently announced that he could make a particular state of India another Silicon Valley! Interesting!!

First, what’s the secret behind Silicon Valley? Well, I am not even qualified enough to state that! However, all I can say is: it is probably a desire to do something very different, and to make the world a better place – that’s possibly the biggest driver in all the entrepreneurs that have come to and out of Silicon Valley in the USA.

If you looked up Wikipedia, it says that the term Silicon Valley originally referred to the region’s large number of silicon chip innovators and manufacturers, but eventually, came to refer to all high-tech businesses in the area, and is now generally used as a metonym for the American high-technology sector.

So, where exactly is India’s high-tech sector? How many Indian state governments have even tried to foster such a sector? Ok, even if the state governments tried to foster, where are the entrepreneurs? Ok, an even easier one: how many school dropouts from India or even smal-time entrepreneurs have even made a foray into high-tech?

Right, so where are the silicon chip innovators from India? Sorry, I dd not even hear a word that you said? Can you speak out a little louder? It seems there are none! Rather, there has been very little to no development in India, barring the work that is done by the MNCs. Correct?
hsinchuOne friend told me that Bangalore is a place that can be Silicon Valley. Really? How?? With the presence of MNCs, he said! Well, Silicon Valley in the US does not have MNCs from other countries, are there? Let’s see! Some companies with bases in Silicon Valley, listed on Wikipedia, include Adobe, AMD, Apple, Applied Materials, Cisco, Facebook, Google, HP, Intel, Juniper, KLA-Tencor, LSI, Marvell, Maxim, Nvidia, SanDisk, Xilinx, etc.

Now, most of these firms have setups in Bangalore, but isn’t that part of the companies’ expansion plans? Also, I have emails and requests from a whole lot of youngsters asking me: ‘Sir, please advice me which company should I join?’ Very, very few have asked me: ‘Sir, I have this idea. Is it worth exploring?’

Let’s face the truth. We, as a nation, so far, have not been one to take up challenges and do something new. The ones who do, or are inclined to do so, are working in one of the many MNCs – either in India or overseas.

So, how many budding entrepreneurs are there in India, who are willing to take the risk and plunge into serious R&D?

It really takes a lot to even conceive a Silicon Valley. It takes people of great vision to build something of a Silicon Valley, and not the presence of MNCs.

Just look at Hsinchu, in Taiwan, or even Shenzhen, in China. Specifically, look up Shenzhen Hi-Tech Industrial Park and the Hsinchu Science Park to get some ideas.

IEF 2013: New markets and opportunities in sub-20nm era!

October 15, 2013 1 comment

Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.

Liam BritnellLiam Britnell, European manager and Research Scientist, Bluestone Global Tech (BGT) Materials spoke on Beyond Graphene: Heterostructures and Other Two-Dimensional Materials.

The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.

I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.

I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.

Jean-Rene Lequepeys, VP Silicon Components, CEA-Leti, spoke on  Advanced Semiconductor Technologies Enabling High-Performance Jean-Rene Lequepeysand Energy Efficient Computing.

The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.

To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.

To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.

Andile NgcabaAndile Ngcaba, CEO, Convergence Partners, spoke on Semiconductor’s Power and Africa – An African Perspective.

This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.

Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.

This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.

What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.

It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.

Jo De Boeck, senior VP and CTO, IMEC, discussed Game-Changing Technology Roadmaps For Lifescience. Jo De Boeck

Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.

New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
Read more…

Now, India to have two semicon fabs!

September 12, 2013 10 comments

Finally, the Government of India has approved the establishment of a semiconductor wafer fab (fab) in India!

This is indeed heart warming news, especially for the Indian semiconductor and electronics industries. For years, India has been trying to get at least one fab up and running! Now, the dream is about to be realized!

Speaking from China, an ecstatic BV Naidu, chairman and managing director, Sagitaur Ventures, co-chairman, Karnataka ICT Grioup and former president, India Semiconductor Association (ISA) said: “This is really a fantastic news for the Indian semiconductor industry. The government has been trying to achieve this since 2008. The announcement goes as a strong signal to global community.”

Pradip Dutta, corporate VP and MD, Synopsys, said: “It is a momentous decision for the semiconductor industry and by extension the electronics industry for our country. It should lead to a level playing field for the local manufacturers and mitigate some of the disability factors. I sincerely hope the industry reacts positively to this news and this leads to a vibrant local IC design industry.”

Raghu Panicker, sales director, Mentor Graphics India, added: “For years, India has been trying to get at least one fab up and running! This has indeed been a long awaited news. Finally its not ONE, but TWO. The fabs would fuel the growth of semicon start up’s and electronics industry as a whole. It is a big step forward for the overall ESDM inititaive by IESA and government.”

Jaypee Group, IBM and Tower form one consortium. HSMC, STMicroelectronics and a Malaysian company are said to be part of the other consortium.

300mm is the new 200mm!


300mm fabs.

Buyers of 300mm fabs.

300mm is the new 200mm, said GlobalFoundries’ David Duke, during a presentation titled ‘Used Equipment Market’ at the recently held Semicon West 2013 in San Francisco, USA. Used semiconductor equipment sourcing and sales is a very interesting challenge.

Qimonda, Spansion, Powerchip and ProMOS had jumpstarted the market. Now, there is a broadening user base. There is an unexpected uptake by analog and power device producers to achieve economies of scale. There has been legacy logic scaling. Also, the 200mm fabs are being upgraded to 300mm with used equipment. Many 300mm tools can “bridge” to 200mm easily.

Parts tools are seeding the ecosystem. Third parties are also able to support refurb as well as tool moves. However, we need more! Software licensing is becoming a smaller hurdle. There has been no over-supply yet!

So, what are the ‘rough’ rules of thumb for 300mm? First, there are approximately 1,500 individual tools in the open market. Few sellers know the values as the market is still developing. Twenty percent of the transactions drive 80 percent of sales. Today, the number of 300mm buyers is around  1/10th the number of 200mm buyers!

Lithography has been the biggest difference. Leading edge DRAM is far more expensive in lithography. Lithography has seen the most dramatic financial effects with explosive pricing in technology (immersion) and the need for capacity (two-three critical passes vs. one with dual/triple gate patterning. As of now, financial shocks and bankruptcies are the main drivers for used 300mm.

Next, 200mm is now the new 150mm! The 200mm OEM support is starting to dry up. It is nearly impossible to compete in productivity vs. 300mm. Oversupply is causing values to stay suppressed. The only bright spot being: there is still strong demand for complete fabs. The 200mm market split is roughly by 40 percent Asia and 60 percent rest of the world.

So, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV.

That brings me to India! What are they doing about fabs over here? This article has enough pointers as to what should be done. Otherwise, the world is already moving to 450mm fabs! Am I right?

Why do we need 450mm wafers?


Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

Mike Bryant.

Mike Bryant.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.
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IMEC’s 450mm R&D initiative for nanoelectronics ecosystem


Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.

IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&D pilot line will enable full 450mm process capability for advanced nodes by early 2017.

Source: IMEC, Belgium.

Source: IMEC, Belgium.

Scaling
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture.

Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.

IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.

IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.

With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.
Read more…

IEF 2012: Turning recession into opportunity!

October 22, 2012 1 comment

Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:

Mojy Chian

Mojy Chian

Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.': Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.

Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.

With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.

John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.': The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total

John Holt

John Holt

chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.

This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.

These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.

Rudy Lauwereins

Rudy Lauwereins

Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space': As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.

Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.

As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.
Read more…

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