Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.
This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.
It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.
In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.
Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.
The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:
Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.
Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.
Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.
Roger de Keersmaecker, IMEC, Belgium, presented on IMEC’s 450mm R&D initiative in support of the nanoelectronics ecosystem at the Semicon Europa event in Dresden, Germany. IMEC has prepared an integrated 450mm R&D initiative. This will present an innovation engine supporting the global nanoelectronics ecosystem.
IMEC will play a key role in the acceleration of 450mm equipment development by timely installation of alpha/beta-demo tools for early learning, in an industry-relevant technology flow and ensuring patterning capability by early 2016. The 450mm R&D pilot line will enable full 450mm process capability for advanced nodes by early 2017.
Logic device scaling slows down and ‘interim’ nodes are likely to be introduced. Disruptive devices are needed beyond 10nm. NAND flash is migrating from 2D floating gate to 3D SONOS device architecture.
Emerging memories are being introduced at 1x nm node. The parallel system scaling path done using 3D TSV technology is established and slowly gaining in momentum. Die cost is also exploding. There is an increasing need for an innovation pipeline, early design/technology co-optimization and cost reduction.
IMEC announced the opening of 300mm CR expansion on June 8, 2010. The cleanroom expansion is 450mm ready. There is 1,200m2 extra clean room space, and ready for EUV. Fab 1 is a 200mm pilot line and 5200 m2 CR (1750 m2 Class 1), with 24/7 continuous operation. Fab 2 is a 300mm pilot line with ball room, clean sub-fab, and 3200 m2 + 1200 m2 CR, also in 24/7 continuous operation.
IMEC started engineering new 450mm clean room in 2012. It has plans to stat constructing the clean room in 2013 and complete by 2015. The Flemish Minister of Innovation, Ingrid Lieten, announced to invest in the building of imec’s 450mm clean room facilities.
With the combination of a state-of-the-art 300mm clean room and the transition to 450mm, imec will be able to keep on delivering its partners topnotch research on (sub)-10nm devices enabling the future growth of the global nanoelectronics industry.
Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:
Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.
Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.
With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.
John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total
chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.
This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.
These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.
Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.
Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.
As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.
The other day, I was engaged in an interesting discussion regarding the Indian semiconductor industry. The obvious question: can fabless semiconductor take India to the top?
Well, it all depends on the definition of ‘top’! Does it mean the role of India-based semiconductor companies as a percentage of the semiconductor market globally? Or, do we take India as a system/gadget maker and thus, as a percentage of that market??
Fabrication is increasingly expensive, much involved and the actual global fabrication players (i.e. those who (also) own a fabrication plant) are declining and will be about three to four companies, and about 10, if we include all off those Chinese fabs.
And, India continues to slip back in having a ((proper) fab!
Now, India’s contributions to global electronics and semiconductors will continue to increase as the MNC subsidiary companies’ hub, and not quite as India-based companies, who are coming out with something that will shake the world in terms of that chip(s)!
If India has domestically consuming gadgets, that are more India specific, that could need devices available less outside. For that purpose alone, a local fab could be essential. However, such requirements appear less each day!
So, yes! Fabless semiconductor could be the way forward for India, in terms of contribution to its economy. However, in terms of India becoming a global player through such chips conceptualized in India, for India and the world, the chance is lesser, for now!
Well, hasn’t the Indian semiconductor industry been shouting ‘fabless’ from the rooftops for some years now? Let us see how India has progressed so far!
One, in terms of having local fab, the answer is NO! Two, in terms of increasing its percentage of contribution to global semiconductors, electronics from India, YES, an increasing role and value (though these are embedded software too).
In terms of having India-based companies working toward developing chips, YES again, in terms of smaller, analog, components that are crucial (like Cosmic Circuits), and YES, in terms of having IP-based companies (like Innovative Logic India for USB3.0) and, YES in terms of increasing service companies.
Many more companies are coming up, and some started directly here in India, such as Apsconnect, Techvulcan, etc. In terms of the actual solutions, YES again, as we have developed solutions in medical, automation, etc.
However, the answer to the question remains NO in terms of having chips come out of India, as yet!
Now, what happens to the fab-lite strategy? Well, it continues, globally. From an India perspective, it is actually in a way, validation of the earlier belief. There is less direct importance to manufacturing from themselves, but more about the actual value add they do OR can do.
Now, given this situation, let us also look at the key growth drivers in Indian electronics, especially, since we are talking about fabless and fab-lite.
The obvious one is to develop solutions for the India market. It is likely that these can be for outside markets as well. This ability will actually make India develop solutions for global markets. Also, these are not semiconductors per se, but, (embedded) solutions based on them.
The above situation can slowly lead to a fabrication and manufacturing ecosystem in India. India should also try to position itself at the higher end of the solutions, markets, services, etc., so that its value contribution can be much more.
Friends, is there a way out of the current situation that India finds itself?
Actually, this is normal process of growth in the chosen path. India continues to think about low end, less (or no) risk options of services. There is only so much growth, revenue, profit possible in those areas unless one goes up the market.
India has not done that as it could be, as an ecosystem in all. India should focus on its own internal requirements. That could mean growth and an increasing role for India, globally, as well!
Besides manufacturing, the big issue lies in marketing of such products. A senior statesman from a leading Indian electronics firm once asked me, “How will India compete in marketing of these products compared to the Chinese or Taiwanese manufacturers, who have more than 30 years of experience in these industries?”
How one wishes that India had at least two wafer fabs by now, what with the technology nodes constantly upping their ante. Even if someone does decide to put up a fab, it will be extremely expensive and has to be cutting-edge. However, as I said, one should never give up hope!
And then, there is the Modified Special Incentive Package Scheme (M-SIPS).
The newly announced M-SIPS is long awaited and much needed. The key is to now turn this ‘gazette notification’ into implementation, by the regulators, and utilisation by the industry.
It is understandable that the government can only do so much, particularly, under the given circumstances. With that kept in mind, this is a yet another good start! Hopefully, instead of just commenting on this policy, the industry sincerely works to benefit from it by properly utilizing it.
Why just think of digitalization of TV! The number of set-top boxes required across the country will be huge! Or, think of electrification of roads all over India. The number of LEDs required are likely to be massive. These are just two examples of the many possible. The Indian electronics industry needs to move fast, and now!
Hasn’t all of this been very easy to say, difficult to manage!
According to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp., while fabless startups have declined substantially in the West during the past decade, they are growing in India.
Given the time required to grow large fabless companies in the past, India should not be discouraged by current progress. India has key capabilities to stimulate growth of fabless companies, such as:
* Design services companies.
* Design engineering expertise and innovation.
* Returning entrepreneurs.
* Educational system.
Semiconductor frustrations abound! I recall a discussion in mid-2005 where an industry expert mentioned that fabless was the way forward for the Indian industry! Between then and now, fabs were supposed to come up, but they failed. Nevertheless, one must not give up hope!
As of now, there seems to be too much focus on services, multinational company dominance, perceived lack of progress, perceived lag compared to China, lack of foundry infrastructure, and no clear dominant indigenous Indian company.
Of the top 50 semiconductor companies in 2011, 12 are fabless and four are foundries. Fabless IC revenue has been growing at 17 percent CAGR since 1997 and will continue to grow. Even the fabless market has been gaining in the overall market. However, the fabless revenue is said to be highly concentrated. He added that the leading fabless companies specialize and average ~23 years since formation. Also, the VC funding for fabless semiconductor companies has been declining in the West. As for the number of fabless companies, the GSA put it at 1,200 companies, at the end of 2010.
According to Dr. Rhines, the semiconductor IP market would grow to about $3,707 million by 2015, at a CAGR of 14 percent. The leading semicon IP players specialize and average 22 years in business (similar to fabless).
Now, India is said to be among the top five semiconductor design locations worldwide (SIP + fabless + design services). Also, India is a leading source of semicon IP, accounting for 5.3 percent globally. From the looks of it, India seems to have built a foundation for a fabless future. India can well become the next great fabless incubator! Read more…
Malcolm Penn, chairman and CEO, Future Horizons, asked the question at the SEMI ISS2011 Europe event at Grenoble, France, early this week: Whether this is the time to rethink the industry assumptions?
For instance, fabs have no strategic value, until you haven’t got one and lost control of your business. ASPs will keep on falling, just like house prices kept on rising? The semicon industry growth rate has slowed to ’7 percent per annum, which is only possible if ASPs keep falling 4 percent given an 11 percent unit growth.
Foundry wafers will always be cheap and freely available, just like cheap debt, right? Multiple sources will keep the foundries ‘honest’, since it is assumed that multi-sourcing at 20/22nm is going to be ‘interesting‘. It is also OK to focus on more than Moore competence, as today’s ‘More Moore’ is tomorrow’s ‘More Than Moore’.
Industry fundamental #1 – Economy: This was NOT a recession, someone turned off the lightsPre-Lehman, the chip industry was in very good shape. There was strong unit demand, and no excess inventory.There was limited wafer fab capacity, and no overspend/cutting back. Next, the ASPs were recovering, although, structurally driven. However, the strong global world economy was being deliberately slowed. The money really stopped moving in the post-Lehmann crash!
The economic coupling Is statistically weak. The economy is just one part of the equation. The chip industry marches to its own drum as well.
Industry fundamental #2: Unit demand: The Moore’s Law giveth and taketh away! Long-term average ICs/wafers grow only very slowly. There are more complex ICs counter balance die shrinks (1-2 percent productivity gain). Besides, 9-10 percent new capacity is needed to match the 11 percent average IC unit growth.
Industrial fundamental #3: Fab capacity: Let’s look at the IC manufacturing fundamentals — four quarter minimum lag from decision to impact.
* Total equipment capex = 85 percent of the total capex
* Wafer fab capex = 70 percent total equipment capex
* Order today = Wafer fab capex one quarter later* Wafer fab capex = Additional capacity two quarters later
* Additional capacity = IC units out one quarter later.
Pig cycles and cobwebs will keep happening due to long supply-side lead times (4 Months – production / 2 Years – fabs / 5+ years – design).
The fab capacity is still seriously tight. The Q4-10 status is still down 7.5 percent vs. Q3-08 peak. Also, the first relief happened in Q4-10 (from Q3/Q4-09’s spend) following six flat quarters.
The IC wafer fab capacity for Q3/Q4-09 spend, was equal to +80k ws/w In Q4-10. The 2010 spend was equal to ~400k ws/w additional by Q4-11? The wafer fab capex is still running ‘fab tight!’ Here are some more pointers:
* Not yet overheating, despite 140 percent 2010 growth.
* 2010 spend same as 2006; 10 percent lower than 2007 and 80 percent of 2000’s all time peak.
* Q1-11 book to bill <1; slowing Q2-11 sales.
* 2011 up between 5-15 percent, still within ‘safe haven’ region.
* TSMC thunders on with capex up 30 percent sales up 22 percent; the leadership gap up. Read more…
Right then, folks! This is my last post for 2010, on my favorite topic – semiconductors. If 2009 was one of the worst, if not, the worst year ever for semiconductors, 2010 seems to be the best year for this industry, what with the analyst community forecasting that the global semicon industry will surpass the $300 billion mark for the first time in its history!
Well, here’s a look at the good, the bad and the ugly, if available for otherwise what has been an excellent year, which is in its last hours, for semiconductors. Presenting a list of posts on semiconductors that mattered in 2010.
Future research directions in EDA: Dr. Prith Banerjee @ VLSID 2010 — This was quite an entertaining presentation!
Indian semicon industry: Time for paradigm shift! — When will that shift actually happen?
ISA Vision Summit 2010: Karnataka Semicon Policy 2010 unveiled; great opportunity for India to show we mean business! — So far, the Karnataka semicon policy has flattered to deceive! I’m not surprised, though!
Indian electronics and semiconductor industries: Time to answer tough questions and find solutions — Reminds me of the popular song from U2 titled — “I still haven’t found what I’m looking for”!
What should the Indian semicon/electronics industry do now? — Seriously, easy to say, difficult to manage (ESDM)! Read more…
I came across an article titled “Global Semiconductor Companies Turn to India for Growth” published on India Knowledge@Wharton. Isn’t this reason why global semiconductor companies enter a specific market in the first place — to grow their own markets and regions? So, why should it be different with India?
India is very well known globally for its talent, chip design capabilities (especially in the Indian arms of the global semicon firms) and as the world’s embedded bastion!
This particular article is brilliantly written, and kudos the author. The clinching paragraph is tucked away at the end, starting with: “None of the global players, however, is currently looking at setting up a semiconductor fabrication plant, or “fab,” in India.”
What’s happened up until now in the Indian semicon industry? If one were to look at the Special Incentive Package Scheme (SIPS), which was introduced back in Sept. 2007 by the government of India, it was geared toward encouraging investments for setting up semicon fabs, and other micro and nanotechnology manufacturing industries in India!
It also defined the “ecosystem units” as units, other than a fab unit, for manufacture of semiconductors, displays including LCDs, OLEDs, PDPs, any other emerging displays; storage devices; solar cells; photovoltaics; other advanced micro and nanotechnology products; and assembly and test of all the above products.
Next, the government of India’s thrust on solar/PV, via the Jawaharlal Nehru National Solar Mission (JN-NSM), has at least ensured the country’s solar/PV future.
What has happened since all of these policies? Really, nothing much, at least from the perspective of the Indian semicon industry. If it has, at least, I am unaware, and my apologies for this ignorance.
Of course, solar/PV seems to be going from strength to strength! Recently, NTPC Vidyut Vyapar Nigam Ltd (NVVN) put out the list of selected solar projects under the JN-NSM Phase 1, Batch 1. But that’s another story!
On this very blog, there are several posts that speak of India’s ability or inability to build a fab. At first, folks said that semicon fabs were on their way in India, and that the story isn’t disappearing. However, somewhere along the line, that particular vision took a beating and fabs simply disappeared from the Indian semicon radar! Read more…