Archive for the ‘FPGA design software’ Category

FPGA design heads to the cloud!

December 6, 2012 3 comments

Han Hua Ng

Harn Hua Ng

Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company’s go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.

Since pay-as-you-go business models are rare in the semiconductor industry, we went through several steps, of which the first was to better understand the market, the available tools and stake-holders:
* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?

With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns – security, accessibility and cost.

“Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes Plunify
view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market.”

How can the on-demand cloud computing platform dramatically accelerate chip design workflows? According to Harn Hua Ng, one  immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in three months’ worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.

Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).

With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.
Read more…

Xilinx announces first stacked silicon interconnect technology

October 28, 2010 2 comments

Xilinx Inc. announced the industry’s first stacked silicon interconnect technology. It proposes to deliver breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.

3D packaging approach

L-R: Xilinx's Dave Myron, Suresh Ramalingam and Neeraj Varma discuss the first stacked silicon interconnect technology.

L-R: Xilinx's Dave Myron, Suresh Ramalingam and Neeraj Varma discuss the first stacked silicon interconnect technology.

Xilinx has taken a 3D packaging approach that makes use of passive silicon-based interposers, microbumps and through-silicon vias (TSV) to deliver multi-die programmable platforms. As the interposer is passive, it does not dissipate any heat beyond what’s consumed by an FPGA die.

The stacked silicon interconnect technology offers 2X FPGA capacity advantage at each process node. It is a core part of Virtex-7 family. Also, the stacked silicon interconnect technology is supported by standard design flows.

Xilinx has been accelerating FPGA transition to the heart of the system. David L. Myron, senior manager, High Volume Products, Product and Solutions Management, Xilinx, revealed that a lot of Xilinx’s customers are doing FPGA starts rather than ASIC starts as that seems more viable. Customers are now asking for much more — over 2X today’s logic capacity, many more high-speed serial transceivers as well as processing elements, as well as much more internal memory to store data. “The challenge is delivering ‘more than Moore’,” he said.

Myron cited certain challenges. These include availability and capability — the largest FPGAs are only viable later in the life cycle. Power and bandwidth pose additional challeges. The traditional mitigation techniques are no longer adequate. “One of the trends we have seen is that while gate count has gone up at a certain rate, the I/Os have not,” he added. Hence, innovation is the need of the hour to meet capacity requirements.

The stacked silicon interconnect technology is addressing all of these challenges, meeting the needs of high bandwidth, low latency and low power. This Xilinx innovation offers massive number of low latency, die-to-die connections. Besides, there is no wasted I/O power.

For applications requiring high-transistor and logic density for high levels of computational and bandwidth performance, these 28nm platforms will deliver significantly higher capacities, resources and power savings than possible in a monolithic die approach. Read more…

Altera expands low-cost Cyclone FPGA series

November 3, 2009 1 comment

Altera's Cyclone IV FPGA.Altera Corp. has introduced the Cyclone IV FPGAs, thereby expanding the success of the low-cost Cyclone series.

The Cyclone IV GX is said to be the lowest cost, lowest power FPGAs with transceivers, and the Cyclone IV E has helped it extend the lead in combining low cost, low power, and high functionality. Simultaneously, Altera also extended its transceiver portfolio leadership.

The Cyclone IV FPGA family offers two variants. Cyclone IV GX devices have up to 150K logic elements (LEs), up to 6.5-Mbits of RAM, up to 360 multipliers, and up to eight integrated 3.125-Gbps transceivers supporting mainstream protocols including Gigabit Ethernet (GbE), SDI, CPRI, V-by-One and Cyclone IV GX has hard IP for PCI Express (PCIe).

According to Jennifer Lo, Senior Marketing Manager, Altera, the company is pushing bandwidth limits in cost-sensitive markets and products — specifically, smartphones, wireless communications, industrial Ethernet, broadcast and 3D displays.

There is said to be a huge demand from Latin America, Asia, etc., specifically in wireless. Altera is providing a low cost, low power solution. Next, the trend is also moving from 2D to 3D displays. In broadcast it is moving to high bandwidth, in order to support HD video.

Easier for designers to debug FPGA designs
With the new Cyclone IV, will it become easier for designers to debug FPGA designs, especially when looking at the hardware and software aspects? Lo said that ease of use has always been a focus for low-end products for Altera.

“To that end, with Cyclone IV FPGA’s, like other Cyclone series, we strive to provide reference designs, design examples, development boards to customers to jump-start their design. With respect to debugging, we don’t see any particular differences between Cyclone IV and previous Cyclone generations.

“However, with more training, both fundamental trainings offered free on-line and more in-depth instructor-led trainings are available to help customers get accustomed with the Altera design methodology and use of our Industry-leading development software,” she added.

Altera had introduced the Cyclone III LS FPGA development kit, as well as shipments of industry’s first FPGAs with integrated 11.3-Gbps transceivers. How are all of these going to help Altera overall, given that Q3 saw a 3 percent increase; and help boost FPGA sales?

Lo added: “FPGAs usually have a longer design cycle (at least a few months before prototyping and another few months till mass production. With the recent few product additions, Altera is in a technology leadership position that we are all very proud of and confident that we will be able to reap the results of in the near future.” Read more…

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