FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.
There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.
Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).
Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.
In addressing power/performance challenges, 20SoC is said to be the quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC process is the first 32Gbps transceivers that are operating in 20nm silicon.
Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate
surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.
Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.
Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.
Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.
To find out more about how are Xilinx’s solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: “Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the VivadoTM Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.
“Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.
“Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp.”
Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?
According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.
Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.
How are the solutions going to address the challenges with ASICs and ASSPs?
He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.
Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.
ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.
Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company’s go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.
Since pay-as-you-go business models are rare in the semiconductor industry, we went through several steps, of which the first was to better understand the market, the available tools and stake-holders:
* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?
With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns – security, accessibility and cost.
“Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes
view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market.”
How can the on-demand cloud computing platform dramatically accelerate chip design workflows? According to Harn Hua Ng, one immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in three months’ worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.
Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).
With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.
Xilinx Inc. has announced the Vivado Design Suite. It enables an IP and system centric next generation design environment. Especially meant for the next decade of ‘All-Programmable’ devices, it also accelerates the integration and implementation up to 4X. And, why now? That’s because the all-programmable devices enable programmable systems ‘integration.
There are system integration bottlenecks, such as design and IP re-use, integrating algorithmic and RTL level IP, mixing DSP, embedded, connectivity and logic, and verification of blocks and “systems”.
There are implementation bottlenecks as well, such as hierarchical chip planning, multi-domain and multi-die physical optimization, predictable ‘design’ vs. ‘timing’ closure, and late ECOs and rippling effect of changes.
Vivado accelerates productivity up to 4X. The design suite elements include an integrated design environment, has a shared scalable data model, is scalable to 100 million gates, and debug and analysis. It shares design information between implementation steps that ensures fast convergence and timing closure. This enables highly efficient memory utilization. Also, it is scalable to future families, that are greater than 10 million logic cells (100 million gates) and enables cross-probing across the entire design.
Vivado also enables packaging designs into system-level IP for re-use. You can share IP within your team, project or company. Any 3rd party IP is delivered with a common look and feel. You can re-use IP at any point in the implementation process. The IP can be source, placed, or placed and routed.
Moshe Gavrielov, president and CEO, Xilinx Inc. was in Hyderabad, India to inaugurate Xilinx India’s new, expanded India site at Hi-Tech city. The new Hyderabad site is a 131,000 square-foot office building — more than 2X the size of the previous site. It is equipped with engineering labs for end-to-end development and has a larger, energy-efficient data center. It also has facilities for customer and employee events.
This site is Xilinx’s largest R&D centre outside of US headquarters. Pivotal to record-fast delivery of 28nm technologies, it has a stellar worldwide technical support team. Xilinx has been committed to be the first to process nodes. It is pioneering 3-D IC technology and leading edge processing sub-systems. It is also offering programmable analog/mixed signal solutions as well as system to IC tools and IP to enable silicon.
Gavrielov said that Xilinx’s business drivers have been the programmable imperative, relentless system integration and an insatiable intelligent bandwidth. The programmable imperative has further accelerated. For instance, 28nm = 2X 45nm cost. Insatiable bandwidth has now expanded to Latin America. It is said to be almost 2x the size of the US market. There has been 20 percent growth in mobile subscribers and 318 percent growth in Facebook users.
There has been insatiable bandwidth across India as well, while bandwidth is also said to be growing in Africa. Some of the trends driving insatiable intelligent bandwidth include extreme bandwidth – which has seen 5X growth in five years, smart vision, ubiquitous computing and embedded security. Read more…
Xilinx Inc. has announced its first Zynq-7000 Extensible Processing Platform (EPP) shipments to customers. It showcased the first public demonstration of a Zynq-7000 EPP at the ARM European Technical Conference, in Paris, France. where attendees saw the device running a Linux-based application. Xilinx has recently started shipping Zynq, to at least three customers.
The Zynq-7000 family is the world’s first EPP. It combines an industry-standard ARM dual-core Cortex-A9 MPCore processing system with Xilinx 28nm unified programmable logic architecture. This processor-centric architecture delivers a complete embedded processing platform that offers developers ASIC levels of performance and power consumption, the flexibility of an FPGA and the ease of programmability of a microprocessor.
Dave Tokic, senior director, partner Ecosystems and Alliances, said the company had made a number of investments. It has adopted a two-pronged approach: focusing on how it developed the ecosystem, and what it could do by itself. ”We need a tool flow applicable across all customers. Our technologies are enabling much more complex designs. We are also raising the bar for the EDA providers. We do provide early access to our tools, etc.”
Tokic added that the company has also invested a lot in training and certification in India. “Our partners are some very good companies. We have 24 members in our program. Eight of those are certified members.” Some of the partner companies include Wipro, TCS, Corel, Mistral, CMC, GDA Technologies (L&T), Mechatronics, etc.
Lawrence Getman, VP of Processing Platforms, added that Xilinx has been seeing how to potentially leverage a cloud. “We are continuing to develop the IP ecosystem. We are also looking to engage expert service needs.”
Commenting on developments, Getman said that Xilinx’s Virtex-7 series FPGAs are based on the high performance low power (HPL) process by TSMC. Xilinx wants to foster more collaborative approach in future for acquiring and working with customers.
Lattice Semiconductor Corp. has introduced the low-cost and low-power ECP4 FPGAs. These feature 6Gbps SERDES in low cost wire-bond packages, powerful DSP blocks and hard IP-based communication engines for cost- and power-sensitive wireless, wireline, video, and computing markets.
The LatticeECP4 FPGA family features high performance, low power in low cost 65nm process, making a great FPGA family even better. Lower cost, high yield 65nm process is ideal for mid-range FPGAs. There has been an extensive use of wire-bond packaging. The FPGAs have CDR capable I/Os that lower customers’ implementation cost. The POWER sysDSP minimizes multipliers and LUTs, and enables high bandwidth in a small area. There is also a 10X area reduction by use of hardened MACO communication engines.
The ECP4 features lower power architecture. It is optimized for mid-density devices, and not based on high-density high overhead platform. Modified logic/routing power ratio helps achieve higher performance with modest dynamic power increase. It also features higher bandwidth and performance.
As it is, the FPGA boasts 10X more efficient hard MACO engines. Besides, it has 7X more DSP processing capability, 2X faster SERDES (6G), 66 percent more LUTs, 50 percent higher LVDS performance, 42 percent more memory and 33 percent higher DDR3 I/O performance.
Diamond 1.4 beta design software is available for select customers, especially those who jumpstart cost-effective platform designs. The ECP4 device samples will be available in 1H 2012, and the ECP4 production devices will be available in 2H 2012. Read more…
Altera Corp. has introduced SoC FPGAs that integrates an ARM processor with the FPGA. The SoC FPGAs are said to deliver reduced board space, power and system costs, as well as increased performance. Altera also launched the FPGA industry’s first Virtual Target that enables immediate device-specific application software development prior to hardware availability.
The ARM-based FPGAs integrate 28-nm Cyclone V and Arria V FPGA fabric, a dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect into a single chip. The Cyclone V and Arria V SoC FPGAs further extend the portfolio’s reach into the embedded processing market. Embedded developers needs include increased system performance, reducing system power, and reducing board size as well as system cost. ARM + Altera = SoC FPGAs.
The SoC FPGA family highlights include the dual-core ARM Cortex-A9 MPCore processor, which includes hard memory controller, peripherals and high-bandwidth interconnect. Altera’s 28-nm FPGA fabric involves the Cyclone V SoC FPGA the and Arria V SoC FPGA, respectively. ARM’s ecosystem and Altera’s hardware development flow is also featured in the form of the Quartus II software and Qsys system integration tool. These SoC FPGAs are also said to have a proven virtual prototyping methodology in the form of SoC FPGA Virtual Target for device-specific software development.
The ARM processor has been combined with hard IP. The SoC FPGA uses the dual-core ARM Cortex-A9 MPCore processor that features 800 MHz per core (industrial grade), NEON media processing engine, single/double precision floating point unit (FPU), 32-KB/32-KB L1 caches per core and ECC-protected 512-KB shared L2 cache. The hard IP features multi-port memory controller with ECC, such as DDR2/3, mobile DDR, LPDDR2, as well as QSPI, NAND flash, NOR flash memory controller with ECC, and a wide range of common peripherals.
The advanced 28nm low-power (28LP) FPGA fabric is the optimal choice for addressing today’s power- and cost-constrained applications and boasts the lowest absolute power. The hard IP features up to three memory controllers with ECC, variable precision DSP technology, up to two hard PCIe Gen 2 x4 and high-speed transceivers operating up to 10 Gbps. Read more…
Today, Lattice Semiconductor Corp. announced the official inauguration of Lattice India in a ribbon cutting ceremony in Koramangala, Bangalore, that included Lattice president and CEO, Darin G. Billerbeck, and Lattice India GM, Sidhartha (Sid) Mohanty.
Billerbeck noted: “We build mostly custom built products, and in future, we would be building more low cost products. We are now restructuring the company. In fact, we just completed our strategic long-term roadmap (SLR).
He added: If you look at India, we develop low-cost applications over here. It also helps in giving us better communications with customers. It is now an option for India to do hardware design. Some of our products will stay on 65nm for a long time.”
In FPGAs, Lattice is strong on the ECP3 family, a third generation high value FPGA, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device.
The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces,
powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power process technology.
Billerbeck noted that some of the ECP3 and ECP4 products will stay on the 65nm line. “ECP3 is already in production, while the ECP4 will be next. ECP5 family will come out in the next two years from now, and focus on 28nm.”
He noted: “We are not in an ‘arms race’ with the likes of Intel. Xilinx, etc. Our focus: We want to win in the low power. Our value proposition is in low power and communication spaces. We also want to be innovative.”
According to him, Altera had a great last year. Even Xilinx can bounce back. Lattice also has much more cash. It can do acquisitions now, if it so wishes. “People are now looking at new growth opportunities in smaller companies, so that’s a great opportunity. Our software team is very good. The guy in San Jose is very good.” Read more…
Xilinx Inc. announced the industry’s first stacked silicon interconnect technology. It proposes to deliver breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density, as well as tremendous levels of computational and bandwidth performance.
3D packaging approach
Xilinx has taken a 3D packaging approach that makes use of passive silicon-based interposers, microbumps and through-silicon vias (TSV) to deliver multi-die programmable platforms. As the interposer is passive, it does not dissipate any heat beyond what’s consumed by an FPGA die.
The stacked silicon interconnect technology offers 2X FPGA capacity advantage at each process node. It is a core part of Virtex-7 family. Also, the stacked silicon interconnect technology is supported by standard design flows.
Xilinx has been accelerating FPGA transition to the heart of the system. David L. Myron, senior manager, High Volume Products, Product and Solutions Management, Xilinx, revealed that a lot of Xilinx’s customers are doing FPGA starts rather than ASIC starts as that seems more viable. Customers are now asking for much more — over 2X today’s logic capacity, many more high-speed serial transceivers as well as processing elements, as well as much more internal memory to store data. “The challenge is delivering ‘more than Moore’,” he said.
Myron cited certain challenges. These include availability and capability — the largest FPGAs are only viable later in the life cycle. Power and bandwidth pose additional challeges. The traditional mitigation techniques are no longer adequate. “One of the trends we have seen is that while gate count has gone up at a certain rate, the I/Os have not,” he added. Hence, innovation is the need of the hour to meet capacity requirements.
The stacked silicon interconnect technology is addressing all of these challenges, meeting the needs of high bandwidth, low latency and low power. This Xilinx innovation offers massive number of low latency, die-to-die connections. Besides, there is no wasted I/O power.
For applications requiring high-transistor and logic density for high levels of computational and bandwidth performance, these 28nm platforms will deliver significantly higher capacities, resources and power savings than possible in a monolithic die approach. Read more…