The SEMI/Gartner Market Symposium was held Semicon West 2014 at San Francisco, on July 7. Am grateful to Ms. Becky Tonnesen, Gartner, and Ms Agnes Cobar, SEMI, for providing me the presentations. Thanks are also due to Ms Deborah Geiger, SEMI.
Dean Freeman, research VP, Gartner, outlined the speakers:
• Sunit Rikhi, VP, Technology and Manufacturing Group, GM, Intel Custom Foundry Intel, presented on Competing in today’s Fabless Ecosystem.
• Bob Johnson, VP Research, Gartner, presented the Semiconductor Capital Spending Outlook.
• Christian Gregor Dieseldorff, director Market Research, SEMI, presented the SEMI World Fab Forecast: Analysis and Forecast for Fab Spending, Capacity and Technology.
• Sam Wang, VP Research Analyst, Gartner, presented on How Foundries will Compete in a 3D World.
• Jim Walker, VP Research, Gartner, presented on Foundry versus SATS: The Battle for 3D and Wafer Level Supremacy.
• Dr. Dan Tracy, senior director, Industry Research & Statistics, SEMI, presented on Semiconductor Materials Market Outlook.
Let’s start with Sunit Rikhi at Intel.
As a new player in the fabless eco-system, Intel focuses on:
* The value it brings to the table.
* How it delivers on platforms of capability and services.
* How it leverage the advantages of being inside the world’s leading Integrated Device Manufacturer (IDM)
* How it face the challenges of being inside the world’s leading IDM.
Intel has leadership in silicon technologies. Transistor performance per watt is the critical enabler for all. Density improvements offset wafer cost trends. Intel currently has ~3.5-year lead in introducing revolutionary transistor technologies.
In foundry capabilities and services platforms, Intel brings differentiated value on industry standard platforms. 22nm was started in 2011, while 14nm was started in 2013. 10nm will be starting in 2015. To date, 125 prototype designs have been processed.
Intel offers broad capability and services on industry standard platforms. It also has fuller array of co-optimized end-to-end services. As for the packaging technology, Intel has been building better products through
multi-component integration. Intel has also been starting high on the yield learning curve.
Regarding IDM challenges, such as high-mix-low-volume configuration, Intel has been doing configuration optimization in tooling and set-up. It has also been separating priority and planning process for customers. Intel has been providing an effective response for every challenge.
Some of Intel Custom Foundry announced customers include Achronix, Altera, Microsemi, Netronome, Panasonic and Tabula.
FPGAs serve highly diverse applications. Tailored devices are serving diverging market needs. According to Vince Hu, VP Product & Corporate Marketing, Altera Corp., next-generation portfolio involves an ideal mix of process technologies.
There is greater diversity and capabilities for the broadest range of applications. Finally, Altera has added the 55nm EmbFlash that extends Altera’s tailored approach. Hu was speaking at the 13th Globalpress Electronics Summit being held in Santa Cruz, USA.
Addressing needs of higher-volume systems is key. Industrial and automotive systems tend to be cost sensitive, low power and limited in broad areas. There is an increased pressure to innovate leading to a strong demand for programmable solutions with enhanced features. Altera is expanding the capabilities of non-volatile programmable logic devices (PLDs).
Altera is also bolstering high-volume system solutions. TSMC leading-edge embedded flash technology is a device tailored for high-volume applications. It adds more functionality to non-volatile PLDs. It also re-inforces Altera’s commitment to high-volume applications.
In addressing power/performance challenges, 20SoC is said to be the quickest path to next-generation process. It is tailored for a range of performance and bandwidth-critical applications. There is up to 60 percent lower power vs. 28nm. One of the latest results with 20SoC process is the first 32Gbps transceivers that are operating in 20nm silicon.
Currently, high-end applications are pushing the envelope. Intel’s 14nm tri-gate is said to be a game changer for FPGAs. Tri-gate
surrounds channel on the three sides. It increases channel performance and reduces power. Tri-gate is a proven, second- generation technology. The 14nm tri-gate maintains the Moore’s Law.
Driving toward 400G OTN systems
Altera has acquired OTN IP provider TPACK. It accelerates the company’s OTN roadmap and builds on the Avalon acquisition in 2010. OTN IP, combined with high-performance silicon, positions Altera for continued growth in the high-end networking market.
Tailored devices are now serving diverging market needs. It is an extension of Altera’s tailored approach. There are even greater diversity and capabilities, serving the broadest range of applications. A mixture of application-specific IP provides even greater tailored solutions. Altera is mixing the advanced FinFET process, traditional HKMG planar process and embedded flash technology.
Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company’s go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.
Since pay-as-you-go business models are rare in the semiconductor industry, we went through several steps, of which the first was to better understand the market, the available tools and stake-holders:
* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?
With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns – security, accessibility and cost.
“Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes
view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market.”
How can the on-demand cloud computing platform dramatically accelerate chip design workflows? According to Harn Hua Ng, one immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in three months’ worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.
Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).
With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.
Device volume, variety and complexity are only going to increase. Transformative technologies like virtual prototypes give organizations the tools to transcend challenges. Companies like Altera are creating competitive advantage and innovation with these solutions. Virtual prototyping is now ready for the masses.
Industry trends and challenges make virtual prototyping a must-have solution. New realities make prior adoption barriers mere myths. Virtual prototyping has become a key process for early software development and supply chain enablement. Industry trends also alter design requirements. For instance, earlier, it used to be computing and single core, which has since moved on to connectivity and multi-core.
This opens up implications for SoC development, especially, in terms of increased complexity and volume of software. There is a need to get the architecture right. No amount of downstream tools will compensate for the fundamentally wrong architecture. There is also a need to start software development earlier, in parallel with hardware design. Needless to say, hardware-software integration must be accelerated and system validation will minimize waterfall development process.
New realities of prototyping render prior barriers as mere myths. For instance, earlier, it was believed that creating a prototype is hard. IP models, TLMCentral and model creation software have come a long way, in reality. Earlier, there was a need to wait for complete prototype. Now, software can be developed incrementally and VDKs are jumpstarting the software development. Earlier, one felt the need to change software environment. In reality, the very same tools, debuggers and environment used for hardware can be used here.
Also, today, there are multiple use cases, verticals and customers of virtual prototyping. There is industry support for system-level models. The TLMCentral is an open, web-based portal that provides consolidated access to transaction-level models available across the industry, helping virtual prototype developers accelerate the creation and deployment of their prototypes for early software design.
Open and free, TLMCentral is the first industry-wide portal to aggregate available transaction-level models. It has over 1,000 models of most common IP blocks and interfaces for wireless, consumer and automotive applications. TLMCentral is supported by leading IP vendors, tool providers, service companies and universities. It also offers model developers, architects and software engineers an infrastructure for news, forums and blogs.
Integrated into the software development environment, there are popular debuggers, powerful controls and debugging information. VDK is a great starting point and for ongoing use. One can install and start using. There is no need to wait for months for a prototype. Templates, sample software and reference prototypes are available in one place. Post-silicon support and validation is provided, besides early availability for software development and testing.
Key process for earlier software development includes hardware-software integration and system validation. Semis are engaging customers earlier. The VDKs are driving tangible time-to-volume reduction. Tangible benefits of virtual prototyping include faster time to revenue, faster customer success, and faster field and ecosystem readiness.
Altera Corp. has introduced SoC FPGAs that integrates an ARM processor with the FPGA. The SoC FPGAs are said to deliver reduced board space, power and system costs, as well as increased performance. Altera also launched the FPGA industry’s first Virtual Target that enables immediate device-specific application software development prior to hardware availability.
The ARM-based FPGAs integrate 28-nm Cyclone V and Arria V FPGA fabric, a dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect into a single chip. The Cyclone V and Arria V SoC FPGAs further extend the portfolio’s reach into the embedded processing market. Embedded developers needs include increased system performance, reducing system power, and reducing board size as well as system cost. ARM + Altera = SoC FPGAs.
The SoC FPGA family highlights include the dual-core ARM Cortex-A9 MPCore processor, which includes hard memory controller, peripherals and high-bandwidth interconnect. Altera’s 28-nm FPGA fabric involves the Cyclone V SoC FPGA the and Arria V SoC FPGA, respectively. ARM’s ecosystem and Altera’s hardware development flow is also featured in the form of the Quartus II software and Qsys system integration tool. These SoC FPGAs are also said to have a proven virtual prototyping methodology in the form of SoC FPGA Virtual Target for device-specific software development.
The ARM processor has been combined with hard IP. The SoC FPGA uses the dual-core ARM Cortex-A9 MPCore processor that features 800 MHz per core (industrial grade), NEON media processing engine, single/double precision floating point unit (FPU), 32-KB/32-KB L1 caches per core and ECC-protected 512-KB shared L2 cache. The hard IP features multi-port memory controller with ECC, such as DDR2/3, mobile DDR, LPDDR2, as well as QSPI, NAND flash, NOR flash memory controller with ECC, and a wide range of common peripherals.
The advanced 28nm low-power (28LP) FPGA fabric is the optimal choice for addressing today’s power- and cost-constrained applications and boasts the lowest absolute power. The hard IP features up to three memory controllers with ECC, variable precision DSP technology, up to two hard PCIe Gen 2 x4 and high-speed transceivers operating up to 10 Gbps. Read more…
Brilliant! There’s no other word to describe the first part of this headline!
As per IC Insights’ forecast of 2010 billion-dollar fabless IC suppliers, excerpted from a ranking of top 50 fabless IC suppliers in its ‘ 2011 edition of The McClean Report’, as many as 13 fabless IC suppliers are tipped to cross the $1-billion mark in sales in 2010! As per IC Insights, this is a significant step up — from 10 companies in 2009 and eight in 2008.
Just sit back and admire this table. There are nine firms from the US — Qualcomm, Broadcom, AMD, Marvell, Nvidia, Xilinx, Altera, LSI and Avago, three from Taiwan — MediaTek, Novatek and MStar, while ST-Ericsson is Europe’s lone representation in this stellar list.
In this august club of IC billionaires, no surprises, but Qualcomm retains the top place for the third consecutive year. Broadcom moves up a place. AMD should become the world’s third largest player.
Broadcom at 53 percent, Marvell at 34 percent, Xilinx at 39 percent, Altera at 63 percent, Avago and Novatek at 40 percent each are top performers. However, MStar of Taiwan steals the show with an estimated 75 percent growth in 2010.
Qualcomm, Nvidia and LSI have performed well, especially the last two – coming pff a difficult 2009. Taiwan’s MediaTek has seen the biggest slip — down to 3 percent in 2010 from 22 percent in 2009.
There is no representation from Japan in the fabless IC billionaires club. IC Insights has indicated that the fabless/foundry hasn’t caught on in Japan and is unlikely to do so in the near future. However, Taiwan and China based firms should sooner or later find their way into this club.
I will now come to India! Read more…
The morning session rolled out with a session on ‘Today’s FPGA Ecosystem,’ where the participants included, Neeraj Varma, country manager – Sales, India and Australia/NZ, Xilinx India, Wai Leng Cheong, regional sales manager, South Asia Pacific, Altera Singapore, and Rakesh Agarwal, country manager, India & ANZ, Lattice.
Adrian Hernandez, senior manager, Xilinx USA, gave a presentation on ‘Mastering FPGA Design through Debug.’ This was followed by John Wei, High Speed System Specialist, Altera, Hong Kong delivering a lecture on the ‘Trends and challenges in designing with high speed transceivers based FPGAs, and signal Integrity concerns.’ The morning session was wrapped up by Srinivasan Venkataramanan, CTO, CVC, who presented on ‘Upgrading to SystemVerilog for FPGA Designs.’
A highlight of the afternoon session was a panel discussion on ‘State of FPGA technology and its adoption in India.”
Now, I am not really posting anything specifically on the sessions as these were mainly targeted toward engineers, and I, for a change, decided to simply sit back and listen to the speakers, rather than take notes.
Just a few points from here and there. For instance, Lattice’s Rakesh Agarwal mentioned that the company’s mid-range ECP3 is the lowest power SerDes enable FPGA in the market. The company is focused on markets where it can differentiate with high value, low power solutions, and where it has the scale to effectively compete.
The single most important feature that one must keep in mind when designing and verifying FPGA based projects is device reconfiguration. Xilinx’s Adrian Hernandez suggested that users should build on the FPGA’s reconfiguration. He called upon them to share knowledge and experiences. One of the points raised by John Wei was that advanced oscillator and hybrid CDR enables 25Gbps at the 28nm CMOS process node in FPGAs. SystemVerilog interfaces have quickly found way into new designs, as they are useful for RTL designers and verification engineers. Srinivasan Venkataramanan touched upon the ecsystem around the SV-FPGA, adding that all major EDA vendors support SystemVerilog for design.
On the event itself, Navin Kumar and his team, including the volunteers, deserve a huge round of applause for pulling off this event. It was the first of its kind in India, an open source conference — with free attendance, etc. I believe, more people turned up, than originally expected. The turnout itself was interesting, with a mix of engineers, students and of course, the industry.
There were some minor hiccups regarding the location/venue and the positioning of booths — some of which looked really cramped for space, etc. However, these are minor issues, which the FPGACentral India team is sure to address in its forthcoming events. Well done guys!
Manufactured on TSMC’s 28nm high-performance (HP) process, the Stratix V FPGA family provides up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18×18 multipliers and integrated transceivers operating up to an industry-leading 28 Gbps.
Gangatharan Gopal, country sales manager and office manager for Altera India, said that the FPGAs are suitable for devices used in next-generation high bandwidth systems. According to Altera, these offer 35 percent higher performance than alternative process options, as well as 30 percent lower total power versus other generations. These also enable the fastest and most power efficient transceivers.
He pointed out that Altera has been delivering innovations from the core to the I/O that provide higher system performance at lower cost and power.
Altera’s 28nm Stratix V FPGAs are said to have broken through the bandwidth barrier. The company is also said to be dramatically improving the density and I/O performance of the FPGAs, and further strengthening their competitive position versus ASICs and ASSPs.
Altera’s devices incorporate the industry’s highest level of application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty.
The FPGA family itself includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets. These variants include:
* Stratix V GT FPGA – Industry’s only FPGA with integrated 28-Gbps transceivers targeting 100G systems and beyond.
* Stratix V GX FPGA – Supports a wide range of applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V GS FPGA – Optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers.
* Stratix V E FPGA – Highest density FPGA ideal for ASIC prototyping, emulation or high-performance computing applications. Read more…
Altera announced an industrial safety data package for automation applications at the Embedded World Exhibition and Conference in Nuremberg, Germany.
Then, Xilinx introduced the Xilinx automotive (XA) family of Spartan-6 field FPGAs optimized for applications requiring high-speed connectivity and high-resolution video performance. At the same conference, Xilinx and Inova Semiconductors introduced an Automotive Pixel Link (APIX) IP solution for the Xilinx automotive (XA) family of FPGAs.
World’s first intelligent mixed signal FPGA
The best one, I believe, has come from Actel. Also at the Embedded World 2010, Actel unveiled SmartFusion, the world’s first intelligent mixed signal FPGA.
Now, isn’t that interesting? There has been a lot of focus on analog/mixed-signal (AMS), and Actel’s SmartFusion could not have been timed better.
I recall a story I had done some time ago with Cosmic Circuits for the India Semiconductor Association’s (ISA) website. The company said that the AMS market in India is set to expand rapidly in the next several years — driven by consumer, communications, automotive and industrial. The variety of analog chips required and the complexity are no different from those needed in other regions of the world!
Why? About 18 months ago, when speaking with Synopsys regarding the Galaxy Custom Designer, I distinctly remember the company telling me that it improves AMS productivity!
As per information, Actel’s SmartFusion devices feature Actel’s proven FPGA fabric, a complete MCU subsystem built around a hard ARM Cortex-M3 processor and programmable analog blocks on a flash process. This means, embedded designers can now easily build the system they want, with all the features they need, on a single chip.
Wonder what’s taken the FPGA suppliers so long to come out with an intelligent mixed signal FPGA. Am sure, the others have things lined up as well!
By the way, I couldn’t find anything from Achronix! Maybe, something is on the way from this company as well!
Altera Corp. has introduced the Cyclone IV FPGAs, thereby expanding the success of the low-cost Cyclone series.
The Cyclone IV GX is said to be the lowest cost, lowest power FPGAs with transceivers, and the Cyclone IV E has helped it extend the lead in combining low cost, low power, and high functionality. Simultaneously, Altera also extended its transceiver portfolio leadership.
The Cyclone IV FPGA family offers two variants. Cyclone IV GX devices have up to 150K logic elements (LEs), up to 6.5-Mbits of RAM, up to 360 multipliers, and up to eight integrated 3.125-Gbps transceivers supporting mainstream protocols including Gigabit Ethernet (GbE), SDI, CPRI, V-by-One and Cyclone IV GX has hard IP for PCI Express (PCIe).
According to Jennifer Lo, Senior Marketing Manager, Altera, the company is pushing bandwidth limits in cost-sensitive markets and products — specifically, smartphones, wireless communications, industrial Ethernet, broadcast and 3D displays.
There is said to be a huge demand from Latin America, Asia, etc., specifically in wireless. Altera is providing a low cost, low power solution. Next, the trend is also moving from 2D to 3D displays. In broadcast it is moving to high bandwidth, in order to support HD video.
Easier for designers to debug FPGA designs
With the new Cyclone IV, will it become easier for designers to debug FPGA designs, especially when looking at the hardware and software aspects? Lo said that ease of use has always been a focus for low-end products for Altera.
“To that end, with Cyclone IV FPGA’s, like other Cyclone series, we strive to provide reference designs, design examples, development boards to customers to jump-start their design. With respect to debugging, we don’t see any particular differences between Cyclone IV and previous Cyclone generations.
“However, with more training, both fundamental trainings offered free on-line and more in-depth instructor-led trainings are available to help customers get accustomed with the Altera design methodology and use of our Industry-leading development software,” she added.
Altera had introduced the Cyclone III LS FPGA development kit, as well as shipments of industry’s first FPGAs with integrated 11.3-Gbps transceivers. How are all of these going to help Altera overall, given that Q3 saw a 3 percent increase; and help boost FPGA sales?
Lo added: “FPGAs usually have a longer design cycle (at least a few months before prototyping and another few months till mass production. With the recent few product additions, Altera is in a technology leadership position that we are all very proud of and confident that we will be able to reap the results of in the near future.” Read more…