Why do we need 450mm wafers?

Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

Mike Bryant.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.

E450EDL – European 450mm equipment demo line

Malcolm Penn, chairman and CEO, Future Horizons, sent me the Enable 450 newsletter. The goal of the Enable 450 is: Co-ordination Action to enable an effective European 450 mm Equipment and Materials Network. Here, I am presenting a bit about the E450EDL – European 450mm Equipment demo line.

Malcolm Penn

The aim of the ENIAC E450EDL key enabling technology pilot project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition that started with the ENIAC JU EEMI450 initiative and proceeded with subsequent projects funded with public money, amongst others NGC450, SOI450, EEM450PR.

The demo line resulting from this project will be such that it will enable first critical process module development by combining imec infrastructure with tools remaining at the site of the manufacturers (distributed pilot line). Multi-site processing will allow partners to participate in the world first 450mm integration studies and will be enabled by the controlled exchange of 450mm wafers between different sites.

The consortium comprises 41 members (from 11 different European countries) with many SMEs and research institutes. The project is organized in five technical work packages and a work package on management and co-ordination.

In the work package on integration and wafer processing first critical modules will be developed and will demonstrate the feasibility of processing on 450mm wafers. The main objective in the work package on lithography is to develop a wafer stage test-rig, which
can be implemented into the pilot line system. In the work package on front end equipment several tools will be developed such as a plasma ion implant module, a plasma dry etch module, a RTP system and a single wafer cleaning system.

Furthermore, in the dedicated work package on metrology 450mm metrology tool types will be developed for amongst others dielectric film thickness and composition measurements, defect inspection, defect review and analysis, optical critical dimensions (CD), overlay (mask and wafer) and 3D metrology.

Finally, from the work package on wafer handling and automation a set of equipment will be provided to support the demo line operations, and facilitate the R&D dedicated to process and metrology modules.

The project will last 36 months beginning on 1st of October 2013. The budget has been given at €204.6 million of which the ENIAC JU will fund €30.8 million. This project is still considering new members so if you are interested please contact ASML.

Global semiconductor industry to grow 7.9 percent in 2013

Malcolm Penn

According to Malcolm Penn, CEO, Future Horizons, the outlook for the global semiconductor industry in 2013 is likely to be +7.9 percent. This means, the global semiconductor industry will likely grow to $315.4 billion in 2013.

Should this happen, it would be significant, given that this is the third year in a row that the market failed to break the $300 billion barrier! The global semiconductor clocked around $292.3 billion in 2012, as against $299.5 billion In 2011.

I asked Malcolm Penn the rationale behind this. He said, the rationale is exactly the same as that for 2012. There is said to be no change to last year’s fundamental market analyses. That’s not all! There are likely to be exactly the same (economic) downside risks as well.

The unit demand, capacity and ASPs are all ‘positively aligned’. Here, it is advised that one should never underestimate the economy’s capacity to derail the chip market. Even the downside forecast has been to break the $300 billion barrier.

The global chip industry growth is driven by four factors. These are economy, which is on hold due to complete loss of confidence, unit demand, which is back on the 10 percent per annum treadmill (inventory gone), fab capacity, which is currently tight (very), especially at the leading technology edge, and ASPs, which are structurally following the usual ups and downs.

There is a very safe, long-term bet, provided companies execute properly. As it is, most firms don’t, as they are too pre-occupied with chasing short-term targets.

Finally, if the year 2013 does show a recovery, the global semiconductor market will likely go ballistic in 2014.

IEF 2012: Turning recession into opportunity!

Future Horizons recently organized and held the 21st Annual Electronics Forum on Oct. 3-5 at Bratislava, Slovakia. Here are excerpts from some of the proceedings:

Mojy Chian

Mojy Chian, senior VP Design Enablement. GlobalFoundries presented on ‘Foundry 2.0: The Era of Collaborative Device Manufacturing.’: Despite some predictions to the contrary, the foundry-based fabless model is not going away, and moreover it is driving manufacturers and device designers closer together. But like all living organisms, especially those in electronics, we have to continue to evolve. There are warning signs, both technical and economic, emerging in the foundry business that warrant our attention, and in fact require a re-thinking of how best to apply our resources and energy.

Recent talks of fabless companies investing in their own fabs, and of foundries developing ‘single company fabs’ underscore the sense of urgency. Clearly, we must change – Call it Foundry 2.0! This will be driven, ironically, by a move toward a more IDM-like model. Strategic collaboration that creates a ‘virtual IDM-like interface’ to chip design companies will help further close the gap between process teams at the manufacturing companies and design teams at the fabless companies.

With daunting technical challenges like 3D stacking, 450mm fabs, new transistor architectures, multipatterning, and the long-term viability of extreme ultraviolet (EUV) lithography, collaboration – early, often and deep – is really the only practical approach given the cost and complexities involved.

John Lofton Holt. founder, and chairman of the Board of directors. Achronix, presented on “Embedded FPGAs – Enabling The Next Generation Of Flexible SoCs.’: The system-on-chip (SoC) ecosystem is at a fundamental crossroads. With total

John Holt

chip development and manufacturing costs exceeding $100 million at 22nm, it is no longer cost effective for most SoC designers to build a discrete chip for every application. As a result, SoC designers are investing in programmable intellectual property (IP) for IO expansion, emerging standards compliance and application acceleration.

This programmable IP ranges from microcontrollers and processors to simple state machines that are register-programmable. Nearly every SoC built today has some kind of programmable IP. The programmable logic industry is addressing this SoC challenge in a different way. Coming from the “other end of the spectrum”, the major public FPGA manufacturers are implementing more and more hard IP on their dies to reduce the area penalty of the programmable logic for specific applications.

These techniques, while effective for some mid-range volume applications, will not scale to high volume SoCs. The major public FPGA companies are also very hesitant to license their programmable fabric to SoC designers, fearing competition in their core markets and erosion of margins.

Rudy Lauwereins

Rudy Lauwereins, VP Smart Systems Technology Office, IMEC, presented on ‘Providing “Insite” In The Unknown Design Space’: As technology scaling nears the “final frontier”, designers are confronted with an increasing number of restrictions.

Printing smaller and smaller features remains possible, but requires more and more regular layout patterns. Transistors can still be reduced in size, but may fall short of meeting electrical specifications. Smaller wires are becoming a performance bottleneck.

As technology scaling becomes less ideal, established design paradigms start to break. Creative and innovative solutions are required to sustain the momentum of Moore’s law: hitting the sweet-spot for cost and performance requires tight interaction between the technology development community and the design community. In an increasingly fabless world, imec’s Insite program builds the bridges between these communities.

Semiconductor supply chain dynamics: Future Horizons @ IEF2011

The last decade heralded a dramatic transformation in supply chain dynamics, driven by the complexity challenge of staying on the More Moore curve. On the demand side, the high cost of fabs persuaded almost all integrated device manufacturers (IDMs) to use foundries for their leading-edge wafer supply.

The ever-increasing process complexity and its negative impact on manufacturing yields forced the adoption of sophisticated foundry-specific design-for manufacturing (DFM) techniques, effectively committing new chip designs to a single foundry and process.

At the same time, the industry adopted a much more cautious lagging rather than leading demand approach to new capacity expansion, resulting in under-supply and shortages in leading-edge wafer fab capacity. To make matters worse, the traditional oxide-based planar transistor started to misbehave at the 130nm node, as manifested by low yields and higher than anticipated power dissipation, especially when the transistors were supposed to be off, with no increase in performance, heralding the introduction of new process techniques (e.g., high-k metal gates).

Even before these structural changes have been fully digested, supply chain dynamics have been further disrupted by the prospective transition to 450mm wafer processing, to extreme ultra violet (EUV) lithography, and from planar to vertical transistor design.

Transistor design
Since the start of the industry, adding more IC functionality while simultaneously decreasing power consumption and increasing switching speed—a technique fundamentally known as Moore’s Law—has been achieved by simply making the transistor structure smaller. This worked virtually faultlessly down to the 130nm node when quite unexpectedly things did not work as planned. Power went up, speed did not improve and process yields collapsed. Simple scaling no longer worked, and new IC design techniques were needed.

While every attempt was made to prolong the life of the classic planar transistor structure, out went the polysilicon/silicon dioxide gate; although this transition was far from plain sailing, in came high-k metal gates spanning 65nm-28nm nodes. Just as the high-k metal gate structure gained industry-wide consensus at 28nm, it too ran out of steam at the 22nm-16nm nodes, forcing the introduction of more complex vertical versus planar transistor design and making the IC design even more process-dependent (i.e., foundry-dependent). Dual foundry sourcing, already impractical for the majority of semiconductor firms, will only get worse as line widths continue to shrink.

March’s ‘one-two-three’ calamity! What now for chip industry?

This is a summary by Malcolm Penn, chairman and CEO, Future Horizons. For those who wish to know more, please get in touch with me or Future Horizons.

 

Malcolm Penn, Future Horizons.

It was all going so well at the beginning of March when January’s WSTS results were released. The oil and North African issues were being taken in their stride. Then, less than two weeks later, the earthquake and tsunami disaster struck Japan and by the close of the month, the Gaddafi Libyan regime was under western international airstrike siege.

Given the fragility of industry’s confidence since the Lehman Brothers crisis, the industry has weathered these ‘incidents’ with remarkable sanguinity, with concerns focused purely on supply not demand-side issues. In our view this underlines what we have been saying all along; the 2010 recovery and 2011 outlook were both stronger than most people thought.

The industry’s biggest problems in 2011 were always going to be supply not demand driven; the situation in Japan has simply amplified and accelerated their coming.

The chip industry took March’s one-two-three knocks with remarkable calm, hit first by the spike in oil prices following the politic unrest bordering on civil wars in North Africa, then the dreadful 11 March earthquake and Tsunami in Japan, culminating on 19 March with a multi-state coalition military intervention in Libya to implement United Nations Security Council Resolution 1973.

Last year, any of these events would probably have been enough to deal the industry a knockout blow, as with the September 2008 Lehman Brothers collapse; this time around, despite the still fragile global economic confidence, the industry seems to have taken these events in its stride.

Whilst it is far too early to quantify exactly what the industry impact will be, the oil price and North Africa situation pales into insignificance when compared with the aftermath of the earthquake and tsunami. Japan is too important a cog in the global electronics industry for its impact not to have serious global repercussions. It has also brought to a head the far deeper industry problems that we have long warned of – man-made in the corporate boardrooms – that could (should) have been avoided.

In this aspect, Japan’s disasters do have parallels with the Lehman Brothers collapse and its impact of worldwide finance; we hope that the current disruption to manufacturing worldwide from will force a rethink of how the world manages production.

Aftermath of Japanese earthquake: Implications for global electronics industry!

This is a commentary on industry trends from Malcolm Penn, chairman and CEO, Future Horizons.

Importance of Japan
Japan is a major producer of semiconductor components accounting for around 22 percent of global semiconductor production. The Flash memory market sector – crucially mobile phones, iPads and their derivatives, digital cameras, and portable storage devices, account for approximately 50 percent of the market, almost all of which are produced by one Japanese firm, Toshiba/Sandisk.

Several of Japan’s major semiconductor companies locate their manufacturing spots in the northeast prefectures, for example Toshiba’s 8-inch wafer fab in lwate, Renesas Electronics’ factories in Aomori, Hoddaido and Yamagata, Elpedia Memory’s backend manufacturing facility in Akita and Fujitsu’s plants in Fukushima.

The effects of the devastating earthquake, which hit Japan on Friday 11th March, are already beginning to take hold on the global electronics industry. Damaged buildings and infrastructure and halts to some semiconductor fabs will without doubt have a knock on affect upon the global semiconductor supply chain, with many of the big names, i.e., Nokia, General Motors and Apple already experiencing supply shortages.

Many manufacturers, not directly hit by the earthquake, have experienced power failures interrupting production; just a microsecond power supply glitch can result in the scrapping of weeks of in-process production, and with manufacturers no longer holding inventory it will impact IC supply availability in Q2. To what extent, still remains to be seen. The impact will be felt both in the long and short term, affecting not only the semiconductor supply chain but nearly every other industry imaginable, as it is very rare these days to find an industry which is not reliant on chips.

Component prices
As in any shortage situation, component price increases are inevitable and this has already happened in memory, although it is not yet clear how much of this is panic profiteering and how much is sustainable. But shortages are inevitable and recovery due to the long production cycle times and already tight capacity – will not happen over night.

Automakers
The automotive semiconductor market grew 37 percent in 2010, clearly leaving the problematic 2009 behind. However the recent earthquake in Japan has once again awoken auto manufacturers concerns about the industry. Even before the earthquake purchasing managers had expressed concern about supply levels; inventories were unusually low, resulting in heightened concern from purchasing executives around the world.

It is difficult to estimate the extent auto manufacturers will be affected, but following an official announcement from Japan that car production will be down 33 percent from its normal monthly production level of 750k cars per month to 500k it looks as though the 2010 market growth may be short lived.

Toyota Motor Co, the worlds largest auto manufacturer, said all 12 Japanese assembly plants would remain closed until at least 26th March and it was not sure when they would re-open. Production lost between 14-26 March would be about 140,000 units.

Boom turned to bust? Chip industry’s future!

Malcolm Penn, Future Horizons.

Malcolm Penn, chairman and CEO, Future Horizons, asked the question at the SEMI ISS2011 Europe event at Grenoble, France, early this week: Whether this is the time to rethink the industry assumptions?

For instance, fabs have no strategic value, until you haven’t got one and lost control of your business. ASPs will keep on falling, just like house prices kept on rising? The semicon industry growth rate has slowed to ’7 percent per annum, which is only possible if ASPs keep falling 4 percent given an 11 percent unit growth.

Foundry wafers will always be cheap and freely available, just like cheap debt, right? Multiple sources will keep the foundries ‘honest’, since it is assumed that multi-sourcing at 20/22nm is going to be ‘interesting‘. It is also OK to focus on more than Moore competence, as today’s ‘More Moore’ is tomorrow’s ‘More Than Moore’.

Industry fundamental #1 – Economy: This was NOT a recession, someone turned off the lightsPre-Lehman, the chip industry was in very good shape. There was strong unit demand, and no excess inventory.There was limited wafer fab capacity, and no overspend/cutting back. Next, the ASPs were recovering, although, structurally driven. However, the strong global world economy was being deliberately slowed. The money really stopped moving in the post-Lehmann crash!

The economic coupling Is statistically weak. The economy is just one part of the equation. The chip industry marches to its own drum as well.

Industry fundamental #2: Unit demand: The Moore’s Law giveth and taketh away! Long-term average ICs/wafers grow only very slowly. There are more complex ICs counter balance die shrinks (1-2 percent productivity gain). Besides, 9-10 percent new capacity is needed to match the 11 percent average IC unit growth.

Industrial fundamental #3: Fab capacity: Let’s look at the IC manufacturing fundamentals — four quarter minimum lag from decision to impact.
* Total equipment capex = 85 percent of the total capex
* Wafer fab capex = 70 percent total equipment capex
* Order today = Wafer fab capex one quarter later* Wafer fab capex = Additional capacity two quarters later
* Additional capacity = IC units out one quarter later.

Pig cycles and cobwebs will keep happening due to long supply-side lead times (4 Months – production / 2 Years – fabs / 5+ years – design).

The fab capacity is still seriously tight. The Q4-10 status is still down 7.5 percent vs. Q3-08 peak. Also, the first relief happened in Q4-10 (from Q3/Q4-09’s spend) following six flat quarters.

The IC wafer fab capacity for Q3/Q4-09 spend, was equal to +80k ws/w In Q4-10. The 2010 spend was equal to ~400k ws/w additional by Q4-11? The wafer fab capex is still running ‘fab tight!’ Here are some more pointers:
* Not yet overheating, despite 140 percent 2010 growth.
* 2010 spend same as 2006; 10 percent lower than 2007 and 80 percent of 2000’s all time peak.
* Q1-11 book to bill <1; slowing Q2-11 sales.
* 2011 up between 5-15 percent, still within ‘safe haven’ region.
* TSMC thunders on with capex up 30 percent sales up 22 percent; the leadership gap up.

It’s Q1 seasonal slowdown, and yearly time for denial!

This is a summary by Malcolm Penn, CEO, Future Horizons. For those who wish to know more, please get in touch with me or Future Horizons.

Malcolm Penn, CEO, Future Horizons.

December’s WSTS results were as boring as they were predictable, with no serious data revisions (thankfully) and the results right where we expected. December’s year-on-year IC unit growth was 8.9 percent that, with the 3.5 percent growth (yes GROWTH) in ASPs, yielded a respectable double-digit value growthof 12.8 percent. And this, on the back of a weak Q4 memory market that saw ASPs fall 13.1 percent vs Q3-10!

The yearly growth vs 2009 weighed in at 31.8 percent, hitting $298.3 billion, just shy of the elusive $300 billion threshold. The market is right where we said it would be at our recent 2011 Forecast seminar; we reiterate our position that 2011 will be a good year for the industry. Choppy first-half waters for sure, but watch out for a whopping 2H-11 ricochet.

Connectors are up as well
It is not just semiconductors that are off to a good start. The connector industry is tight as a drum too. Orders in December 2010 were up 13.3 percent versus December 2009, with full year orders up 29.3 percent on 2009, down sequentially 11.1 percent from November 2010. The comparable data for sales was plus 18.7percent, plus 28.4 and minus 13.7 percent.

The December connector book-to-bill ratio was 1.01, unchanged from November. This industry still publishes orders and book-to-bill data by the way, unlike the chip industry which very foolishly stopped publishing this several years ago. All this in the seasonally slow first quarter of the month, yet few people believe there is a supply problem in prospect. Just as this time last year, industry denial is rampant, way beyond reasonable caution and ignoring the underlying trends.

Strong demand for mobile, server and graphics DRAM
We estimate that the worldwide growth rate for PCs in 2011 will be a healthy 10 percent, with 3.9GB the average DRAM content per box. New capacity and die shrinks are putting near-term pressure on over-supply and pricing but there are now move afoot from Elpida and others to start raising prices.

Where they can, to gain a price advantage, DRAM vendors are actively adjusting their supply in favour of mobile from commodity DRAM, given the current strong demand in the smartphone and tablet PC markets, with a 1GB per box average DRAM content.

Server demand continues to be the other star segment, not just in unit demand but in content per box as well, estimated to average around 30GB in 2011. This will drive a 50 to 60 percent increase in server DRAM demand. Finally in graphics demand for specialty DRAM is also very strong, driven by the rapid take off of3D-TV and continuing strong growth in Blue-Ray DVD.

The overall DRAM industry is thus gradually diversifying from manufacturing mainly commodity DRAM to diversified products such as mobile DRAM, serverbasis DRAM, specialty DRAM and graphic memory.DRAM vendors however are faring mixed fortunes, with Elpida and Hynix having the worst net cash positions with barely enough cash to cover their short-term debt.

The Taiwanese vendors find themselves stuck in a technology trap, unable to invest in the immersion technology needed to break through the 5*nm node, meaning that in the absence of a good market uptick to improve cash flow and profits, a shake out in the DRAM supply base seems unavoidable.

WSTS Dec. 2010 results boringly predictable!

This is a summary by Malcolm Penn, CEO, Future Horizons. For those who wish to know more, please get in touch with me, or, with Future Horizons.

Malcolm Penn, Future Horizons.

December’s WSTS results were as boring as they were predictable, with no serious data revisions (thankfully) and the results right where we expected.  December’s year-on-year IC unit growth was 8.9 percent that, with the 3.5 percent growth (yes GROWTH) in ASPs, yielded a respectable double-digit value growth of 12.8 percent.

And this, on the back of a weak Q4 memory market that saw ASPs fall 13.1 percent vs Q3-10! The yearly growth vs 2009 weighed in at 31.8 percent, hitting $298.3 billion, just shy of the elusive $300 billion threshold.

The market is right where we said it would be at our recent 2011 Forecast seminar; we reiterate our position that 2011 will be a good year for the industry.  Choppy first-half waters for sure, but watch out for a whopping 2H-11 ricochet.

Already the early warning signs are there:  HP has warned of slipped Q1 PC shipment due to component shortages, from sensors to CPUs; TSMC and UMC are curtailing their Chinese New Year annual maintenance programmes due to serious capacity shortages; there is no excess inventory in the pipeline and capacity is maxed out; the front-end book-to-bill has now dropped back below unity; and memory prices have rebounded sharply in the pre-Chinese holiday period.

The whole industry food chain is now an overstretched taunt spring … with no easy roll back option.  The 21C10 industry model is way past its sell by date … time for a radical rethink?  Plan A is NOT sustainable.