Agnisys makes design verification process extremely efficient!

Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”

Non-mainstream packaging in MEMS, LED and power electronics

Source: Yole, France.

The number of MEMS and sensors going into mobile, consumer and gaming applications is expected to continue to skyrocket. As a result, OSAT and Wafer foundry players are getting more and more interest in MEMS module packaging, as volume and complexity of MEMS SiP modules is increasing dramatically, said Dr. Eric Mourier, Yole Developpement.

It implies that IDMs needs to find second source partnersand qualify some OSATs in order to secure their supply chain. Also, standardization(coming from both foundries, OSAT, WLP houses or substrate suppliers) is critical and necessary to implement in order to keep the packaging, assembly, and test cost of MEMS modules under control. There are many different players with different designs, and it’s not likely we’ll see one solution adopted by all the players.

As for wafer-level packaging (WLP) for LEDs, WLP has not been strongly deployed in the LED industry due to associated technical challenges. In the short-term, there is ESD integration in Si substrate. In the long-term, LED drivers could be integrated at the package level for Intelligent lighting. Ultimately, there are wafer-to-wafer manufacturing schemes for certain packaget types.

Real production of HB-LEDs with a mixed approach of WLP+through silicon vias (TSV) is just starting. There are some Taiwanese players such as TSMC, Xintec, Visera, Touch MicroTech and Sibdi, and South Korea-based LG Innotek. Additional players in the semiconductor and MEMS industry are seeking to enter the field.

On-chip networks: Future of SoC design

Selection of the right on-chip network is critical to meeting the requirements of today’s advanced SoCs. There is easy IP integration with IP cores from many sources with different protocols, and an UVM verification environment.

John Bainbridge, staff technologist, CTO Office, Sonics Inc., said that it optimizes the system performance. Virtual channels offer efficient resource usage – saves gates and wires. The non-blocking network leads to an improved system performance. There are flexible topology choices with optimal network to match requirements.

Power management is key with advanced system partitioning, and an improved design flow and timing closure. Finally, the development environment allows easy design capture and has performance analysis tools.

For the record, there are several SoC integration challenges that need to be addressed, such as IP integration, frequency, throughput, physical design, power management, security, time-to-market and development costs.

SGN exceeds requirements
SGN met the tablet performance requirement with fabric frequency of 1066MHz. It has an efficient gate count of 508K gates. There are features such as an advanced system partitioning, security and I/O coherency. There is support for system concurrency as well as advanced power management.

Sonics offers system IP solutions such as SGN, a router based NoC solution, with flexible partitioning and VC (Virtual Channel) support. The frequency is optimized with credit based flow control.

SSX/SLX is message based crossbar/ShareLink solutions based on interleaved multi-channel technology. It has target based QoS with three arbitration levels. The SonicsExpress is for power centric clock domain crossing. There is sub-system re-use and decoupling. The MemMax manages and optimizes the DRAM efficiency while maintaining system QoS. There is run-time programmability for all traffic types. The SonicsConnect is a non-blocking peripheral interconnect.

Why do we need 450mm wafers?

Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

Mike Bryant.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.

Coto announces MEMS based magnetically operated switch

Stephen Day.

According to Stephen Day, VP of Technology, Coto Technology has the number 1 share in reed relays and relay products. The Coto brand is associated with the broadest portfolio, best in class quality, dedicated technical support, and a provider of innovative solutions. He was speaking at the ongoing 13th Globalpress Electronics Summit in Santa Cruz, USA.

Coto has announced the RedRock, a new MEMS based magnetically operated switch. The RS-A-2515 is the world’s smallest wafer level packaged magnetically operated reed switch. It consumes zero power, measures 2mm3 in footprint and switches at less than 0.3W. It delivers high reliability and surface mount package.

The small footprint means use of less PCB real estate, no operate power means a longer battery life. The low switching power leads to higher reliability. The high directionality leads to resistance to stray fields. Hot switchable feature leads to higher reliability.

Together, Coto has managed to combine the best of two worlds — traditional reed switches with MEMS processing. There is high aspect ratio microfabrication (HARM). This is the first commercially available switch. It produces structures that generate strong contact closure forces. The forces are many times greater than the previous MEMS based magnetic switches. It also enables hot switching up to several hundred milliwatts.

HARM is the key to making it all possible. The benefits are many, from temperature rise vs. carry current, to RedRock contact life test, 1V 1 mA hot-switched load. RedRock allows for small size, zero power consumption and high power switching.

At the moment, Coto is leveraging RedRock into high growth applications. In the future, Coto will integrate sensor solution as well. RedRock’s unique combination of features include reed — no power and high current, and MEMS — no power and small size, as well as GMR/Hall — small size and high current — to deliver the RedRock, which features no power, small size and high current.

Dr. Wally Rhines on global semiconductor industry trends for 2013

It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.

Status of global EDA industry

Dr. Wally Rhines.

First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”

For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.

Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.

In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.

DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.

Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”

According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”

“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.

Optimizing Ethernet networks for mobile access and cloud service delivery

Uday Mudoi.

Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).

Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.

Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.

ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.

ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.

Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.

The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.

Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure
network for L2 VPN services at 50 percent lower cost than alternative solutions.

Unlock your mobile with SlimPort

Andre Bouwer.

Founded in 2002, Analogix Semiconductor Inc., a fabless semiconductor company, has introduced the SlimPort that turns your mobile phone into a game console. It also turns your phone into a PC. SlimPort also turns your phone into a media library and player.

SlimPort is a simple mobile accessory that unlocks the full power of your phone or tablet. Some examples are the LG optimus G Pro, PadFone Infinity, Google nexus and Arrows Tab, respectively.

Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Andre Bouwer, VP Marketing, Analogix, said SlimPort also connects to any TV, monitor and projector. It should not be confused with DisplayPort, an open standard and owned by VESA, MyDP is an extension of DisplayPort. SlimPort is a brand of products that provide access to all of your videos, games, and work, wherever you are. It complies with MyDP.

DisplayPort is everywhere. It drives internal and external notebook screens. TVs need notebook connectivity and 4K x 2K, as do phones and tablets. DisplayPort is architected for mobile. It is used in all PCs today. It offers the highest resolutions and battery charging during display. It supports fixed data frequency and spread spectrum, and has passed EMI tests. It reduces the system power consumption as well as noise, strengthening incoming and outgoing RF signal.

SlimPort connects VGA, DVI, HDMI and DisplayPort. SlimPort performs 1920×1080 at 60Hz, making it ideal for gaming, and 1920×1200 at 60Hz, making it suitable for office. SlimPort charges and preserves the battery. It plays HD audio and video, and you can also plug in USB power to charge your phone.

SlimPort creates value. It is easy to integrate and provides seamless connectivity across the product line. It enables new mobile price points, and allows new bundling opportunities and more data usage. Analogix is not stopping here! It further intends to increase the resolution to 4K, support multi-screen, allow AV+USB data and enterprise security.

Tensilica to expand Cadence IP footprint in SoCs

Chris Rowan.

Tensilica DPU solutions are meant for broad applications. It is focusing on three key verticals — Hi-Fi audio voice, IVP imaging and Diamond controllers, as well as the Xtensa. Tensilica will expand the Cadence IP footprint in SoCs. This compliments Cadence and Cosmic Circuits interface and analog IPs.

How does all of this fit into Cadence’s vision of an IP factory? According to Chris Rowan, founder and CTO, Tensilica, there will likely be an IP bazaar, architected  for efficiency, quality and strong focus on integration. He was speaking on the concluding day of the 13th Global Electronics Summit at Santa Cruz, USA.

Complex imaging functions are now everywhere. There are some challenges here such as computational demands. The off-load opportunity means more operations, and lower power per operation.

The Tensilica IVP – image/video processing family consists of the IVP, a high-performance DSP subsystem. It is built for low energy handheld devices. It also has licensable, synthesizable core with rich software tools and libraries. The IVP core has 32 element engines. The IVP has many parallel ‘element engines’ + Xtensa control programmed as SMID  uniprocessor. Application examples include feature detection, 3D noise reduction filter, and video stabiilizer.

IVP is meeting tomorrow’s imaging requirements. It is built for very high imaging efficiency. It is easy to program and is scalable — and can use multiple cores.There is a huge market in many applications. An example of how Tensilica will fit into Cadence’s IP factory is the DTV application.

Together, Cadence and Tensilica will increase customer value. They will accelerate the time-to-market with solution proven customizable design IP. There will be fully integrated data plane solutions for optimized solutions, power and area for various applications. High quality IP subsystems are tested to work optimally together. It is highly complementary to partner CPUs. It is also highly complementary to Cadence’s broad connectivity/AMS design IP, verification IP offerings, and foundry-qualified SoC design tools.

The partnership will also bolster Cadence as a next-generation IP provider. There will be an enhanced portfolio of advanced IP in advanced nodes spanning a wide range of applications. It will address seamless designs from architecture definition to silicon
tape-out. It will also strengthen solutions to address key market segments.

Embedded systems trends and developer opportunities

Herb Hinstorff.

Today, the world is transitioning from independent devices to  connected systems. Intel has been inside the embedded systems market for over 35 years, having developed 270+ CPUs and SoCs as well as 100+ chipsets.

Herb Hinstorff, director of Marketing, Developer Products Division, Intel Software, said that Intel has been engaged at all levels of the solution stack. He was speaking at the 13th Global Electronics Summit at Santa Cruz, USA.

There are tools to deliver on developer needs, such as debuggers, analyzers, compilers and libraries. There are tools to provide the deep system-level insights into power, reliability and performance.

On the debuggers side, they increase system and device stability and reliability. There is an efficient system, SoC-wide defect analysis and ultra-fast system-wide tracing for software debug. There is an integrated application level debugger. Overall, it speeds system bring-up and development. Analyzers focus on boosting reliability, power efficiency and performance, enabling differentiated designs, system-wide analysis and deep insights.

Compilers go on to optimize performance and efficiency. There is the industry-leading C/C++ compiler. It boosts system and application performance on Intel Atom, Core and Xeon processors. Compilers also take advantage of the multicore to boost performance.

There are libraries for performance and efficiency. Software building blocks increase the developer productivity and boost performance. There are specialized testing functions that handle signal processing, data processing, complex math operations and multimedia processing. Besides, there is future-proof software investments. The libraries provide an easy way to take advantage of the multicore capabilities to boost performance.

The Intel System Studio is an integrated software tool suite that provides deep, system-wide insights to help accelerate time-to-market, strengthen system reliability, and boost power effiency and performance. The JTAG interface has system and application code running Linux.

There is a continued broadening of the OS support, and a broader range of tools to match the expanding SoC capabilities. There is more extensive software based training and simulation, as well as market-specific libraries and APIs.

Given that the market is transitioning from independent devices to connected systems, more capable SoC platforms and complex software stacks require deeper and broader system-level insights and optimizations. Embedded developers can take advantage of the Intel System Studio to accelerate the time-to-market, strengthen system reliability, and boost power efficiency and performance of the Intel architecture-based embedded and mobile systems.