We are in December, and its time for outlook 2014! First, I met up with Neeraj Varma, director-Sales, India, Xilinx. He said: “We expect the 28nm to do really well. From Apr. 13-Mar. 14, we expect revenues worth $250 milion from the 28nm line.
“We are now looking at the embedded market – and expect about $2 billion serviceable available market (SAM). We are looking at $8 billion SAM at the ASIC/ASSP displacement market, and of course $6 billion SAM for core PLD.” After a long time, Xilinx has been seeing positive capex. “We are entering a growth cycle for service providers and enterprises,” he added.
A macro view of capex equipment spend is driven by LTE 27.2 percent at 2011-16, and optical networks 15.9 percent. The other areas include data center, enterprise switching and routing, and service provider switching and routing. Next, 3D ICs will enable Nx100G OTN, 400G OTN, MuxSAR, as well as top of the rack switch, I/O virtualization.
Earlier, there were less than 50 ASICs start in communications in the top 10 OEMs. There were less than 20 28nm ASIC starts in at top 10 OEMs. As of 2012, less than 50 percent of the top 16 ASSPs vendors were losing money. Customer needs are diverse now. Companies end up over designing a chip. People end up paying for what trey are not using.
Xilinx is offering the SMARTCORE IP for smarter networks and data centers. “40 percent of our wins have been achieved by integrating or displacing ASICs and ASSPs,” he said. “We have 25 percent total wins across a broad set of apps/portfolio.”
Some other gains for Xilinx:
* Xilinx gained 3 percent increase in PLDs.
* In wired and data centers, it has 12-percent CAGR from 2013-16.
* In wireless, it has 10-12 percent CAGR.
* In automotive smarter vision, it has 20 percent CAGR growth.
* In industrial, scientific and medical (ISM), it has 12 percent CAGR growth.
* In FY13E-FY16E, Xilinx expects to grow 8-12 percent, and has plans to increase the R&D revenue to 8.6 percent.
Leaptech Corp. was established to help the electronics and semiconductor manufacturing companies in India achieve global standards by adopting the latest technologies available worldwide. It represents the world’s leading companies offering automation equipment for PCB assembly, semiconductor, automotive and final assembly automation.
Suresh Nair, director, said that Leaptech is helping the electronics, semiconductor and automotive manufacturing companies in India by bringing in world class technologies from across the globe in assembly automation, the technologies, which are state-of-the-art.
“We provide both pre-sales and post-sales support to all the systems and solutions that we offer, complete post-sales support includes installation, commissioning, training, production support and process support through our factory trained engineers strategically located in Delhi, Mumbai, Bangalore and Chennai.”
Leaptech provides audit and reconditioning services to enable customers improve productivity and uptime on their existing automated through hole and SMT assembly machines. Nair added: “We do provide audit and reconditioning services to customers where the machines were sold/supported by us. We may not be able to handle machines sold by other suppliers since that will be a breach of contract with out own principals.”
As for the training on operational and maintenance aspects of through hole insertion and SMT machines, Leaptech also provide complete training on machines for operation, periodical maintenance, trouble shooting as well as preventive maintenance.
Leaptech offers consultancy services for new electronics setup as well as for new projects in the existing facility, which includes all detailing as well as knowhow on the process of assembly/production. our expert team is upto date with all latest trends in this industry.
Connected mobile devices
It will be interesting to get Leaptech opinon regarding connected mobile devices. Nair said that connected mobile devices would grow for sure in the immediate future. Growth in the long term may depend on the contents of this segment and how interesting it is to the users.
With regard to automotive electronics driving energy efficiency, he added that Leaptech mostly sells automation equipment and the scope for these equipment toward energy efficiency for automotive sector is limited.
Indian electronics scenario in 2014 and beyond
According to Nair, the Indian electronics scenario is still dull and this may continue in the next year as well. Things could improve once the new manufacturing policy announced by the government starts seeing some investments.
To boost electronics manufacturing in India, it requires a simple action plan: make all finished electronics products imports more expensive and give incentives to local manufacturing.
However, he felt that nanotech will not emerge as a disruption in India, at least, not in the near future. It may make some impact in the long run.
Future Horizons hosted the 22nd Annual International Electronics Forum, in association with IDA Ireland, on Oct. 2-4, 2013, at Dublin, Blanchardstown, Ireland. The forum was titled ‘New Markets and Opportunities in the Sub-20nm Era: Business as Usual OR It’s Different This Time.” Here are excerpts from some of the sessions. Those desirous of finding out much more should contact Malcolm Penn, CEO, Future Horizons.
The global interest in graphene research has facilitated our understanding of this rather unique material. However, the transition from the laboratory to factory has hit some challenging obstacles. In this talk I will review the current state of graphene research, focusing on the techniques which allow large scale production.
I will then discuss various aspects of our research which is based on more complex structures beyond graphene. Firstly, hexagonal boron nitride can be used as a thin dielectric material where electrons can tunnel through. Secondly, graphene-boron nitride stacks can be used as tunnelling transistor devices with promising characteristics. The same devices show interesting physics, for example, negative differential conductivity can be found at higher biases. Finally, graphene stacked with thin semiconducting layers which show promising results in photodetection.
I will conclude by speculating the fields where graphene may realistically find applications and discuss the role of the National Graphene Institute in commercializing graphene.
The key challenge for future high-end computing chips is energy efficiency in addition to traditional challenges such as yield/cost, static power, data transfer. In 2020, in order to maintain at an acceptable level the overall power consumption of all the computing systems, a gain in term of power efficiency of 1000 will be required.
To reach this objective, we need to work not only at process and technology level, but to propose disruptive multi-processor SoC architecture and to make some major evolutions on software and on the development of
applications. Some key semiconductor technologies will definitely play a key role such as: low power CMOS technologies, 3D stacking, silicon photonics and embedded non-volatile memory.
To reach this goal, the involvement of semiconductor industries will be necessary and a new ecosystem has to be put in place for establishing stronger partnerships between the semiconductor industry (IDM, foundry), IP provider, EDA provider, design house, systems and software industries.
This presentation looks at the development of the semiconductor and electronics industries from an African perspective, both globally and in Africa. Understanding the challenges that are associated with the wide scale adoption of new electronics in the African continent.
Electronics have taken over the world, and it is unthinkable in today’s modern life to operate without utilising some form of electronics on a daily basis. Similarly, in Africa the development and adoption of electronics and utilisation of semiconductors have grown exponentially. This growth on the African continent was due to the rapid uptake of mobile communications. However, this has placed in stark relief the challenges facing increased adoption of electronics in Africa, namely power consumption.
This background is central to the thesis that the industry needs to look at addressing the twin challenges of low powered and low cost devices. In Africa there are limits to the ability to frequently and consistently charge or keep electronics connected to a reliable electricity grid. Therefore, the current advances in electronics has resulted in the power industry being the biggest beneficiary of the growth in the adoption of electronics.
What needs to be done is for the industry to support and foster research on this subject in Africa, working as a global community. The challenge is creating electronics that meet these cost and power challenges. Importantly, the solution needs to be driven by the semiconductor industry not the power industry. Focus is to be placed on operating in an off-grid environment and building sustainable solutions to the continued challenge of the absence of reliable and available power.
It is my contention that Africa, as it has done with the mobile communications industry and adoption of LED lighting, will leapfrog in terms of developing and adopting low powered and cost effective electronics.
Personalized, preventive, predictive and participatory healthcare is on the horizon. Many nano-electronics research groups have entered the quest for more efficient health care in their mission statement. Electronic systems are proposed to assist in ambulatory monitoring of socalled ‘markers’ for wellness and health.
New life science tools deliver the prospect of personal diagnostics and therapy in e.g., the cardiac, neurological and oncology field. Early diagnose, detailed and fast screening technology and companioning devices to deliver the evidence of therapy effectiveness could indeed stir a – desperately needed – healthcare revolution. This talk addresses the exciting trends in ‘PPPP’ health care and relates them to an innovation roadmap in process technology, electronic circuits and system concepts.
On the growth drivers for GP MCUs, the market growth is driven by faster migration to 32 bit platform. ST has been the first to bring the ARM Cortex based solution, and now targets leadership position on 32bit MCUs. An overview of the STM32 portfolio indicates high-performance MCUs with DSP and FPU up to 608 CoreMark and up to180 MHz/225 DMIPS.
Features of the STM32F4 product lines, specifically, the STM32F429/439, include 180 MHz, 1 to 2-MB Flash and 256-KB SRAM. The low end STM32F401 has features such as 84 MHz, 128-KB to 256-KB Flash and 64-KB SRAM.
The STM32F401 provides thebest balance in performance, power consumption, integration and cost. The STM32F429/439 is providing more resources, more performance and more features. There is close pin-to-pin and software compatibility within the STM32F4
series and STM32 platform.
The STM32 F429-F439 high-performance MCUs with DSP and FPU are:
• World’s highest performance Cortex-M MCU executing from Embedded Flash, Cortex-M4 core with FPU up to 180 MHz/225 DMIPS.
• High integration thanks to ST 90nm process (same platform as F2 serie): up to 2MB Flash/256kB SRAM.
• Advanced connectivity USB OTG, Ethernet, CAN, SDRAM interface, LCD TFT controller.
• Power efficiency, thanks to ST90nm process and voltage scaling.
In terms of providing more performance, the STM32F4 provides up to 180 MHz/225 DMIPS with ART Accelerator, up to 608 CoreMark result, and ARM Cortex-M4 with floating-point unit (FPU).
The STM32F427/429 highlights include:
• 180 MHz/225 DMIPS.
• Dual bank Flash (in both 1-MB and 2-MB), 256kB SRAM.
• SDRAM Interface (up to 32-bit).
• LCD-TFT controller supporting up to SVGA (800×600).
• Better graphic with ST Chrom-ART Accelerator:
– x2 more performance vs. CPU alone
– Offloads the CPU for graphical data generation
* Raw data copy
* Pixel format conversion
* Image blending (image mixing with some transparency).
• 100 μA typ. in Stop mode.
Some real-life examples of the STM32F4 include the smart watch, where it is the main application controller or sensor hub, the smartphone, tablets and monitors, where it is the sensor hub for MEMS and optical touch, and the industrial/home automation panel, where it is the main application controller. These can also be used in Wi-Fi modules for the Internet of Things (IoT), such as appliances, door cameras, home thermostats, etc.
These offer outstanding dynamic power consumption thanks to ST 90nm process, as well as low leakage current made possible by advanced design technics and architecture (voltage scaling). ST is making a large offering of evaluation boards and Discovery kits. The STM32F4 is also offering new firmware libraries. SEGGER and ST signed an agreement around the emWin graphical stack. The solution is called STemWin.
The Global 450mm Consortium (G450C) has been driving the effective industry 450mm development. It is co-ordinating test wafer capability supporting development and demonstrating unit process tool performance. The focus is now on improving tools with suppliers to be ready for customer operations.
Giving an update during the recently held Semicon West 2013 at San Francisco, USA, Paul Ferrer, GM, G450C, said that if one looks at the G450C lithography tool roadmap, by 1H-2014, the 300mm coupon, 450mm directed self-assembly and 450mm imprint will be completed. From 2H-2014 to 1H-2015, there will be 193i patterning service at Nikon’s site. Nikon 193i move-in will take place from 1H-2015 to 2H-2016.
Suppliers are developing the 450mm tool set with 10 tools per quarter being delivered to G450C, the global consortium for 450mm fabs. Significant progress has been made in wafer quality and wafer reclaim is almost ready. Automation and carriers are working, and suppliers are co-operating on the key initiatives. Global collaboration is said to be picking up steam.
In the NFX cleanroom, the 450mm OHT is ready for inter-fab transfer. There are nine tools in-fab — two metro, three process, and four stocker, respectively. There will be seven ODD 3Q2013, and 10 tools ODD 4Q2013, respectively.
As for 450mm notchless wafer activities, the key technical results include the backside fiducial marks that have achieved the desired accuracy (3σ = 0.5μm) using existing camera technology. There are design rules of fiducial marks, such as multiple locations (≤ 4) for robustness and speed, different patterns at multiple locations, and off crystal plane, fewer dots and shallower dots to minimize the Si crystal damage.
As for program highlights, there are collected designs from G450C member companies, tool suppliers, and optical detection suppliers. Also, there has been delivery of 300mm test wafers with fiducial marks. G450C has co-ordinated test wafer plans with suppliers. Further, for 450mm silicon wafer readiness, notchless wafers are technically achievable now.
The G450C members include CNSE/Research Foundation, GLOBALFOUNDRIES, Intel, IBM, Samsung and TSMC.
300mm is the new 200mm, said GlobalFoundries’ David Duke, during a presentation titled ‘Used Equipment Market’ at the recently held Semicon West 2013 in San Francisco, USA. Used semiconductor equipment sourcing and sales is a very interesting challenge.
Qimonda, Spansion, Powerchip and ProMOS had jumpstarted the market. Now, there is a broadening user base. There is an unexpected uptake by analog and power device producers to achieve economies of scale. There has been legacy logic scaling. Also, the 200mm fabs are being upgraded to 300mm with used equipment. Many 300mm tools can “bridge” to 200mm easily.
Parts tools are seeding the ecosystem. Third parties are also able to support refurb as well as tool moves. However, we need more! Software licensing is becoming a smaller hurdle. There has been no over-supply yet!
So, what are the ‘rough’ rules of thumb for 300mm? First, there are approximately 1,500 individual tools in the open market. Few sellers know the values as the market is still developing. Twenty percent of the transactions drive 80 percent of sales. Today, the number of 300mm buyers is around 1/10th the number of 200mm buyers!
Lithography has been the biggest difference. Leading edge DRAM is far more expensive in lithography. Lithography has seen the most dramatic financial effects with explosive pricing in technology (immersion) and the need for capacity (two-three critical passes vs. one with dual/triple gate patterning. As of now, financial shocks and bankruptcies are the main drivers for used 300mm.
Next, 200mm is now the new 150mm! The 200mm OEM support is starting to dry up. It is nearly impossible to compete in productivity vs. 300mm. Oversupply is causing values to stay suppressed. The only bright spot being: there is still strong demand for complete fabs. The 200mm market split is roughly by 40 percent Asia and 60 percent rest of the world.
So, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV.
That brings me to India! What are they doing about fabs over here? This article has enough pointers as to what should be done. Otherwise, the world is already moving to 450mm fabs! Am I right?
Xilinx Inc. has taped-out the first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture. It is said to be the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. Xilinx implemented the industry’s first ASIC-class programmable architecture called UltraScale.
These milestones expand on Xilinx’s industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite. Xilinx already has several firsts in the 28nm space, such as:
* First 28nm tape-out.
* First All Programmable SoC.
* First All Programmable 3D IC.
* First SoC-strength design suite.
Neeraj Varma, director-Sales, India, said that Xilinx’s global market share in the 28nm portfolio was 65 percent in March 2013. With the launch of the industry’s first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture, there are improvements such as 1.5-2x performance and integration, and a year ahead of the competition. It handles massive I/O bandwidth, massive memory bandwidth, massive data flow and routing, and fastest DSP processing. The architecture will scale — from monolithic to 3D IC, planar to FinFET, and ASIC-class performance.
The UltraSCALE architecture points to high performance smarter systems. For example, 1Tps in OTN networking, 8K in digital video, LTE-A in wireless communications, and digital array in radar. There will be requirements for massive packet processing over 400 Gbps wire-speed, massive data flow over 5Tbps, as well as massive I/O and memory bandwidth over 5Tbps, and DSP performance over 7 TMACs.
The mandate for ASIC-class programmable architecture is to remove bottlenecks for massive data flow and smart processing, high throughput with low latency, and efficient design closure with greater than 90 percent utilization without performance degradation. These are the benefits of applying leading edge ASIC techniques in a fully programmable architecture.
ASIC-like clocking maximizes performance margin for highest throughput. UltraSCALE ASIC-like clocking enables clock placement virtually anywhere on the die, making the clock skew problem go away. Also, highly optimized critical paths remove bottlenecks in DSP and packet processing. There is greatly enhanced DSP processing, high-speed memory cascading, and hardened IP for I/O intensive functions.
Next generation power management features also enable a leap in performance. The process node is up to 35 percent static at 20nm. There are more buffers for granular or coarse clock gating. Block RAM is dynamic power gating, hardened cascading. For transceivers, there are architectural optimizations. There is efficient packing and utilization of the logic fabric. For DSP, there are wider multipliers and fewer blocks per function. As for memory, there is DDR4, which operates at 1.2v vs.1.5v, voltage scaling.
The Xilinx KINTEX UltraSCALE will power 4×4 mixed-mode radios, 100G traffic manager NICs, super high-vision processing, 256-channel ultrasound and 48-channel T/R radar processing. The Xilinx VIRTEX UltraSCALE will power 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G muxponder and ASIC prototyping.
Xilinx worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The Xilinx Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in Q4-2013.
Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?
Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”
Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?
According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.
He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.
“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”
Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?
“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”
What will be the impact of transistor variability and other physics issues?
As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.
The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.
At Cadence, the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.
What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.
On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.