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Moore’s Law could come to an end within next decade: POET

August 28, 2013 1 comment

Dr. Geoff Taylor

Dr. Geoff Taylor

POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in integrated circuits, by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost.

POET’s current IP portfolio includes more than 34 patents and seven pending. POET’s core principles have been in development by director and chief scientist, Dr. Geoff Taylor, and his team at the University of Connecticut for the past 18 years, and are now nearing readiness for commercialization opportunities. It recently managed to successfully integrate optics and electronics onto one monolithic chip.

Elaborating, Dr. Geoff Taylor, said: “POET stands for Planar Opto Electronic Technology. The POET platform is a patented semiconductor fabrication process, which provides integrated circuit devices containing both electronic and optical elements on a single chip. This has significant advantages over today’s solutions in terms of density, reliability and power, at a lower cost.

“POET removes the need for retooling, while providing lower costs, power savings and increased reliability. For example, an optoelectronic device using POET technology can achieve estimated cost savings back to the manufacturer of 80 percent compared to the hybrid silicon devices that are widely used today.

“The POET platform is a flexible one that can be applied to virtually any market, including memory, digital/mobile, sensor/laser and electro-optical, among many others. The platform uses two compounds – gallium and arsenide – that will allow semiconductor manufacturers to make microchips that are faster and more energy efficient than current silicon devices, and less expensive to produce.

“The core POET research and development team has spent more than 20 years on components of the platform, including 32 patents (and six patents pending).”

Moore’s Law to end next decade?
Is silicon dead and how much more there is to Moore’s Law?

According to Dr. Taylor, POET Technologies’ view is that Moore’s Law could come to an end within the next decade, particularly as semiconductor companies have recently highlighted difficulties in transitioning to the next generation of chipsets, or can only see two to three generations ahead.

Transistor density and its impact on product cost has been the traditional guideline for advancing computer technology because density has been accomplished by device shrinkage translating to performance improvement. Moore’s Law begins to fail when performance improvement translates less and less to device shrinkage – and this is occurring now at an increasing rate.

He added: “For POET Technologies, however, the question to answer is not when Moore’s Law will end – but what next. Rather than focus on how many more years we can expect Moore’s Law to last – or pinpoint a specific stumbling block to achieving the next generation of chipsets, POET looks at the opportunities for new developments and solutions to continue advancements in computing.

“So, for POET Technologies, we’re focusing less on existing integrated circuit materials and processes and more towards a different track with significant future runway. Our platform is a patented semiconductor fabrication process, which concentrates on delivering increases in performance at lower cost – and meets ongoing consumer appetites for faster, smaller and more power efficient computing.”
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Agnisys makes design verification process extremely efficient!


Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.

Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.

The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.

Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.

IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”

The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.

“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.

Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which  are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.

Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.

The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.

Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.

How is IDesignSpec working as chip-level assertion-based verification?

Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
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Demystifying the MIPI SLIMbus

February 14, 2013 3 comments

SLIMbus is a multi-drop, time division multiplexed serial bus. It has one clock and one data line, with CMOS signalling and no analog PHY. It is targeted for low bandwidth connectivity between the AP/modem and audio/Bluetooth/haptic. SLIMbus was originally specified by the MIPI Alliance in 2007. Arasan’s total IP solution delivery demystifies the adoption of SLIMbus.

According to Ajay Jain, director, Mobile Connectivity Products, Arasan Chip Systems, the SLIMBus system overview includes a host component (e.g., apps processor), a device component (e.g., a broadband modem), and a SLIMbus device component (e.g., audio processor, Bluetooth modem). The logical implementation of SLIMbus system feature is realized through devices within SLIMbus IPs.

The AP/modem have software infrastructure and an active manager device that manages the SLIMbus. Any component can have a framer device activated to drive the SLIMbus CLK. Each component can have one or more generic devices to buffer and transmit/receive audio and other data.

The physical layer enables TDM. The data line NRZI is encoded. The active framer can drive clock gears 1 to 10 for power management. There is an interleaving of control and data on the SLIMbus frames.

As far as device evaluation and enumeration are concerned, each component initializes its devices in correct order under the direction of the interface device. The active framer drives the SLIMbus CLK and framing channels with default values. All components perform frames, superframes and message synchronization. All active devices report presence and characteristics with broadcast messages. Arasan provides the software stack to perform SLIMbus.

The SLIMbus allows a finite set of channel rate multipliers (data segments/superframes). If SLIMbus CLK frequency, it allows channel rate multiplier of audio data rate. Other transfer protocols may be preferred in certain cases, e.g., flow control required, pushed or pulled protocol. All transfer protocols are programmable through the Arasan software stack.

Each port-port connection needs to be mapped onto a SLIMbus data channel. There is two-channel audio on SLIMbus data channels 6 and 7. A subframe length of 32 slots is assumed. The SLIMbus is amazing, yet complex. There are a finite set of parameters. Arasan’s IPs have addressed the low-level complexities of implementation.

Sonics participates in TSMC’s Soft IP Alliance 2.0 beta program

November 30, 2012 2 comments

Milpitas, USA-based Sonics Inc. participated in TSMC’s Soft IP Alliance 2.0 beta program. Driving high quality soft IP eases customer integration and expedites time-to-market.

Sonic’s role in TSMC beta program
Speaking on the beta program and Sonics’ role, Frank Ferro, director of Product Marketing, Sonics, said: “TSMC’s Soft IP kit 2.0 beta program is part of TSMC’s Open Innovation Platform program that creates a complete ecosystem for customers with the overall goal of shortening design time. This is done by providing a large catalog of partner provided IP that is silicon-verified and production-proven.

A complex SoC with Sonics’ SGN on-chip network.

For vendors like Sonics, TSMC has extended this ecosystem to include Soft-IP (IP not designed for a specific process, but delivered as RTL). The program allows Soft-IP partners to access and leverage TSMC’s process technologies to optimize power, performance and area for their IP.

IP cores are checked through TSMC’s foundry checklist to ensure the customers have optimized design results with fast IP integration built into their design. This flow also facilitates easy IP reuse for subsequent designs. The soft IP Kit beta 2.0 program is an extension of the current program through implementing additional quality checks, improving results and making the flow easier for customers.

There are several advantages to Sonics as a participant in this program. First, customers of TSMC will have access to Sonics IP through TSMC’s IP library. Given TSMC’s strong market share, this will allow Sonics IP to be visible to a large customer base. In addition, TSMC’s customers will feel securing using Sonics IP because they know that it has been put through a rigorous series of IP checks that meet the highest quality standards. It also allows Sonics early access to TSMC’s process libraries, allowing Sonics to optimize performance and area for each IP product.

So, what can the TSMC’s Soft IP Kit 2.0 do? How does Sonics enhance its capabilities? The Soft IP Kit 2.0 provides a specific RTL design flow methodology and hand-off which includes: lint (RTL coding consistency), clock domain crossings (CDC), power (CPF/UPF), physical design (routing congestion), design for test (DFT), constraints and documentation.

Using this flow enhances Sonics IP quality and reliability because many RTL errors can be caught at an early stage. As mentioned above, this flow ensures lowest power and best performance of the IP for a given process node.

Atrenta SpyGlass improves packaging
There is a role played by Atrenta SpyGlass. According to Ferro, Atrenta SpyGlass is the tool used to run all the tests. The flow was developed to TSMC’s standards and implemented by Atrenta.  Given Sonics strong relationship with TSMC and Atrenta, we were invited to be a beta partner using our IP to test the new flow. A number of companies do participate in the program, although only Sonics has announced participation in the beta 2.0 program to date.

This tie up with Atrenta will likely improve IP packaging. As part of the overall flow, the final step, after all basic and advanced IP checks, is IP packaging. This step includes providing the IP with information on the design intent, set-up and analysis reports. Again, this is done using the SpyGlass tool from Atrenta.

This IP packaging was available to customers in the past via the Soft IP 1.0 program. The attraction of this type of IP packaging is a result of the growing number of IP cores being integrated into complex SoCs. As the number of third party IP grew, the need for a better, broader methodology was developed.
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Introducing SemiWiki — knowledge repository for semicon design and manufacturing!

January 21, 2011 2 comments

Friends, it is my pleasure to introduce SemiWiki, a website connected with the global semiconductor industry, a creation of my good friend, Daniel Nenni, otherwise, a renowned blogger on semiconductors and an industry expert!

SemiWiki is projected as a “knowledge repository for semiconductor design and manufacturing, facilitating peer-to-peer communications using Web 2.0 technologies.”

Indeed, it is a site, who’s time has come! As per the site, the SemiWiki  project is a cloud based social media platform. It enables mass collaboration using Web 2.0 technologies — such as blogs, forums and wikis — to enable new channels of communication within the semiconductor design ecosystem.

Be careful though — there is REAL user based content and REAL TIME feedback! Don’t be lulled into thinking that some of the content and some (if not, more) of those users are fictitious! In other words, the SemiWiki is a great example of REAL social media having finally come to EDA, semiconductor, IP and foundries!!

I just stopped by the SemiWiki. The site really looks cool! There is a definite attempt to bring the industry together!

There seems to be a problem, or is it due to the newness of the site — the vendor map somehow opens on a page that asks you to sign up. Perhaps, Daniel Nenni should look into this at the earliest. The more content is freely available, the more will be its usage. Of course, the companies involved should look at paying some amount, if possible, and help the site and the owner.

It would be better if the SemiWiki is available in some (or several) languages — since English is not the spoken language in the East and Far East region. There seems to be more of American/English slant as of now! Maybe, that too will change, as SemiWiki progresses.

One post immediately caught my eye — ‘SemiWiki top influencers get  Android tablets”! Man, what do I do to get hold of one (is Daniel listening? ;) )?

Pressing need to protect IP

April 18, 2007 Comments off

Now that India’s semicon policy is in place, it is necessary for India to focus on protecting IP.

Speaking at the CEO Conclave during the VLSI Conference on the topic: Making your IP viable–attracting Investments, Anil Hirani, managing partner, Majumdar & Co. and Ravindra, chief risk officer, ICICI Ventures, said most technology companies did not stress much on important documents like term sheet before, while raising venture capital or going in for private equity. A lot of them do not involve professionals in the key stage, which could easily avoid complications or issues later.

While preference shares were the norm in the United States, in the Indian scenario, most preferred equity shares, as it gave them additional protection and rights as a shareholder under the Indian companies Law. Also, debentures as an instrument, was not used that often, but was likely to be used more in the future. Voting rights was a key area of challenge as most funds and private equity firms came in as minority stakeholders.

Pricing or valuation had also become the biggest challenge. Many deals were falling apart over the differences on valuation. The price dynamics was primarily due to a resurgent stock market and a buoyant economy.

The AIM market of London had become the preferred route for medium and smaller companies trying to access the market, as entry barriers were low and regulations were not as stringent as the US where the Sarbanes-Oxley Act (SOX) had made listing an onerous and expensive process. Further, companies did not place adequate emphasis on proper record keeping and compliance, which later led to issues when a due diligence was conducted.

According to them, IP was the biggest challenge today and companies must take steps to protect it with every employee. There had been a growing interest in the sector what with global investors and arms of global venture funds being present in India.

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