Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
SiC is implemented in several power systems and is gaining momentum and credibility.
Yole Developpement stays convinced that the most pertinent market for SiC lands in high and very high voltage (more than 1.2kV), where applications are less cost-driven and where few incumbent technologies can’t compete in performance. This transition is on its way as several device/module makers have already planned such products at short term.
Even though EV/HEV skips SiC, the industry could expand among other apps. The only question remains: Is there enough business to make so many contenders live decently? Probably, yes, as green-techs are expanding fast, strongly requesting SiC. Newcomers should carefully manage strategy and properly size capex according to the market size.
Power electronics industry outlook
Electronics systems were worth $122 billion in 2012, and will likely grow to $144 billion by 2020 at a CAGR of 1.9 percent. Power inverters will grow from $41 billion in 2012 to over $70 billion by 2020 at a CAGR of 7.2 percent. Semiconductor power devices (discretes and modules) will grow from $12.5 billion in 2012 to $21.9 billion by 2020 at a CAGR of 7.9 percent. Power wafers will grow $912 million in 2012 to $1.3 billion by 2020 at a CAGR of 5.6 percent.
Looking at the power electronics market in 2012 by application and the main expectations to 2015, computer and office will account for 25 percent, industry and energy 24 percent, consumer electronics 18 percent, automotive and transport 17 percent, telecom 7 percent and others 9 percent.
The main trends expected for 2013-2015 are:
* Significant increase of automotive sector following EV and HEV ramp-up.
* Renewable energies and smart-grid implementation will drive industry sector ramp-up.
* Steady erosion of consumer segment due to pressure on price (however, volumes (units) will keep on increase).
The 2011 power devices sales by region reveals that overall, Asia is still the landing-field for more than 65 percent of power products. Most of the integrators are located in China, Japan or Korea. Europe is very dynamic as well with top players in traction, grid, PV inverter, motor control, etc. Asia leads with 39 percent, followed by Japan with 27 percent, Europe with 21 percent and North America with 13 percent.
The 2011 revenues by company/headquarter locations reveals that the big-names of the power electronics industry are historically from Japan. Nine companies of the top-20 are Japanese. There are very few power manufacturers in Asia except in Japan. Europe and US are sharing four of the top five companies. Japan leads with 42 percent, followed by Europe and North America with 28 percent each, respectively, and Asia with 2 percent.
Looking at the TAM comparison for SiC (and GaN), very high voltage, high voltage of 2kV and medium voltage of 1.2kV appear as a more comfortable area for SiC. The apps are less cost-driven and SiC added value is obvious. Low voltage from 0-900V is providing strong competition with traditional silicon technologies, SJ MOSFET and GaN. There are cost-driven apps.
Functional verification is critical in advanced SoC designs. Abey Thomas, verification competency manager, Embitel Technologies, said that over 70 percent effort in the SoC lifecycle is verification. Only one in three SoCs achieves first silicon success.
Thirty percent designs needed three or more re-spins. Three out of four designs are SoCs with one or more processors. Three out of four designs re-use existing IPs. Almost all of the embedded processor IPs have power controllability. Almost all of the SoCs have multiple asynchronous clock domains.
An average of 75 percent designs are less than 20 million gates. Significant increase in formal checking is approaching. Average number of tests performed has increased exponentially. Regression runs now span several days and weeks. Hardware emulation and FPGA prototyping is rising exponentially. There has been a significant increase in verification engineers involved. A lot of HVLs and methodologies are now available.
Verification challenges include unexpected conflicts in accessing the shared resource. Complexities can arise due to an interaction between standalone systems. Next, there are arbitration priority related issues and access deadlocks, as well as exception handling priority conflicts. There are issues related to the hardware/software sequencing, and long loops and unoptimized code segments. The leakage power management and thermal management also pose problems.
There needs to be verification of performance and system power management. Multiple power regions are turned ON and OFF. Multiple clocks are also gated ON and OFF. Next, asynchronous clock domain crossing, and issues related to protocol compliance for standard interfaces. There are issues related to system stability and component reliability. Some other challenges include voltage level translators and isolation cells.
Where are we now? It is at clock gating, power gating with or without retention, multi-switching (multi-Vt) threshold transistors, multi-supply multi-voltage (MSMV), DVFS, logic optimization, thermal compensation, 2D-3D stacking, and fab process and substrate level bias control.
So, what’s needed? There must be be low power methods without impacting on performance. Careful design partitions are needed. The clock trees must be optimized. Crucial software operations need to be identified at early stages. Also, functional verification needs to be thorough.
Power hungry processes must be shortlisted. There needs to be compiler level optimization as well as hardware acceleration based optimization. There should be duplicate registers and branch prediction optimization. Finally, there should be big-little processor approach.
Present verification trends and methodologies include clock partitions, power partitions, isolation cells, level shifters and translators, serializers-deserializers, power controller, clock domain manager, and power information format – CPF or UPF. In low-power related verification, there is on power-down and on power-up. In the latter, the behavioral processes are re-enabled for evaluation.
Open source verification challenges
First, the EDA vendor decides what to support! Too many versions are released in short time frame. Object oriented concepts are used that are sometimes unfit for hardware. Modelling is sometimes done by an engineer who does not know the difference between a clock cycle and motor cycle! Next, there is too much of open source implementations without much documentation. There can be multiple, confusing implementation options as well. In some cases, no open source tools are available. There is limited tech support due to open source.
Power aware simulation steps perform register/latch recognition from RTL design. They perform identification of power elements and power control signals.They support UPF or CPF based simulation. Power reports are generated, which can be exported to a unique coverage database.
Common pitfalls include wrapper on wrapper bugs, eg. Verilog + e wrapper + SV. There is also a dependency on machine generated functional coverage goals. There may be a disconnect between the designer and verification language. There are meaningless coverage reports and defective reference models, as well as unclear and ambiguous specification definition. The proven IP can become buggy due to wrapper condition.
Tips and tricks
There needs to be some early planning tips. Certain steps need to be completed. There should be completion of code coverage targets, completion of functional coverage targets, completion of targeted checker coverage, completion of correlation between functional coverage and checker coverage list, and a complete review of all known bugs, etc.
Tips and tricks include bridging the gap between design language and verification language. There must be use of minimal wrappers to avoid wrapper level bugs. There should be a thorough review of the coverage goals. There should be better interaction between designer and verification engineers. Run using basic EDA tool versions and lower costs.
Flip-Chip is a chip packaging technique in which the active area of the chip is ‘flipped over’ facing downward, instead of facing up and bonded to the package leads with wires from the outside edges of the chip.
Any surface area of the Flip-Chip can be used for interconnection, which is typically done through metal bumps. These bumps are soldered onto the package and underfilled with epoxy. The Flip-Chip allows for a large number of interconnects with shorter distances than wire, which greatly reduces inductance.
According to Lionel Cadix, market and technology analyst, Yole Developpement, France, metal bumps can be made of solder (tin, tin-lead or lead-free alloys), copper, gold and copper-tin or Au-tin alloys. The package substrates are epoxy-based (organic substrates), ceramic based, copper based (leadframe substrates), and silicon or glass based.
In the period 2010-2018, Flip-Chip will likely grow at a CAGR of 19 percent. In 2012, laptop and desktop PCs were the top end products using Flip-Chip. It represents 50 percent of the Flip-Chip market by end product with more than 6.2 million of wafer starts. PCs are followed by smart TV and LCD TVs (for LCD drivers), smartphones and high performance computers.
The Flip-Chip market in 2012 is around $20 billion, selling 20 billion units approximately in 12’’ equivalent wafers. Taiwan is so far the no. 1 producer. At least 50 percent of the Flip-Chips devices get into end products. By 2018, the Flip-Chip market should grow to a $35 billion market, selling 68 billion units.
Applications and market focus
Looking at the applications and market focus, Flip-Chip technology is already present in a wide range of application, from high volumes/consumer applications, to low volumes/high end applications. All these applications have their own requirements, specifications and challenges!
Some of these are military and aerospace, medical devices, automobiles, HPC, servers, networks, base stations, etc, in low volumes. It is present in set-top boxes, game stations, smart TVs/displays, desktops/laptops and smartphones/tablets in high volumes. Flip-chip applications are also in imaging, logic 2D SoCs, HB-LEDs, RF, power, analog and mixed-signal, stacked memories, and logic 3D-SiP/SoCs.
In computing applications, for instance, the Intel core i5 is the first MCM combining a 77mm2 CPU together with a 115mm2 GPU in a 37.5mm side package. Solder bumps with a pitch of 185μm are used for the slicon to substrate (1st) interconnect. This MCM configuration is suitable for office applications, with relatively low demanding processing powers. For mobile/wireless applications, there are opportunities for MEMS in smartphones/feature phones. Similarly, Flip-Chip is available for consumer applications.
For microbumping in interposers for FPGA there is a focus on Xilinx Virtex 7 HT. Last year, Xilinx announced a single-layer, multi-chip silicon interposer for its 28nm 7 series FPGAs. Key features include two million logic cells for a high level of computational performance, and high bandwidth, four slice processed in 28 nm, 25 x 31mm, 100 μm thick silicon interposer, 45 um pitch microbumps and 10 μm TSV, and 35 x 35 mm BGA with 180 μm pitch C4 bumps.
Even if the infrastructure had been ready for full 3D stacking, the 2.5D Interposer would still have been the right choice for FPGAs since the ’10,000 routing connections’ would have used up valuable chip area, making the chip slices larger and more costly than they are now. Virtex 7 HT will consist of three FPGA slices and two 28 gbps SerDes chips on an Interposer capable of operating at 2.8 Tb/sec.
This is a continuation of my coverage of the fortunes of the global semiconductor industry. I would like to acknowledge and thank Mike Cowan, an independent semiconductor analyst and developer of the Cowan LRA model, who has provided me the latest numbers.
With the ‘closing out’ of the final, overall sales result for 2012 by the WSTS, the Cowan LRA model for forecasting global semiconductor sales has been updated to include the full complement of 2012′s monthly sales numbers, thereby incorporating 29 years of historical, global semiconductor (actual) sales numbers as gathered, tracked and published each month by the World Semiconductor Trade Statistics (WSTS) organization.
The necessary mathematical computations required to update the complete set of linear regression parameters embedded in the Cowan LRA forecasting model have been carried out.
The newly derived set of linear regression parameters reflect 29 years (1984 to 2012) of historical global semiconductor sales numbers as a basis of predicting future quarterly and full year sales and sale growth forecast expectations by exercising the Cowan LRA model.
Therefore, the table given here summarizes the model’s latest 2013 sales and sales growth expectations as a function of the model’s range (low, expected and high) for January 2013′s sales forecast estimates as generated by the newly, updated model’s linear regression parameters.
It is estimated that in 2013, the global semiconductor industry is likely to reach $302.022 billion, a growth of 3.6 percent.
Note that next month’s forecast will be based on January 2013′s actual sales number, which is anticipated to be released by the WSTS at the end of the first week in March. Once posted, the model will be rerun to yield the quarterly and full year sales, and sales growth expectations for 2013, respectively.
SLIMbus is a multi-drop, time division multiplexed serial bus. It has one clock and one data line, with CMOS signalling and no analog PHY. It is targeted for low bandwidth connectivity between the AP/modem and audio/Bluetooth/haptic. SLIMbus was originally specified by the MIPI Alliance in 2007. Arasan’s total IP solution delivery demystifies the adoption of SLIMbus.
According to Ajay Jain, director, Mobile Connectivity Products, Arasan Chip Systems, the SLIMBus system overview includes a host component (e.g., apps processor), a device component (e.g., a broadband modem), and a SLIMbus device component (e.g., audio processor, Bluetooth modem). The logical implementation of SLIMbus system feature is realized through devices within SLIMbus IPs.
The AP/modem have software infrastructure and an active manager device that manages the SLIMbus. Any component can have a framer device activated to drive the SLIMbus CLK. Each component can have one or more generic devices to buffer and transmit/receive audio and other data.
The physical layer enables TDM. The data line NRZI is encoded. The active framer can drive clock gears 1 to 10 for power management. There is an interleaving of control and data on the SLIMbus frames.
As far as device evaluation and enumeration are concerned, each component initializes its devices in correct order under the direction of the interface device. The active framer drives the SLIMbus CLK and framing channels with default values. All components perform frames, superframes and message synchronization. All active devices report presence and characteristics with broadcast messages. Arasan provides the software stack to perform SLIMbus.
The SLIMbus allows a finite set of channel rate multipliers (data segments/superframes). If SLIMbus CLK frequency, it allows channel rate multiplier of audio data rate. Other transfer protocols may be preferred in certain cases, e.g., flow control required, pushed or pulled protocol. All transfer protocols are programmable through the Arasan software stack.
Each port-port connection needs to be mapped onto a SLIMbus data channel. There is two-channel audio on SLIMbus data channels 6 and 7. A subframe length of 32 slots is assumed. The SLIMbus is amazing, yet complex. There are a finite set of parameters. Arasan’s IPs have addressed the low-level complexities of implementation.
How will the global semiconductor industry perform in 2013? After a contrasting spell of predictions for 2012, I see no change in 2013! So, what’s the answer to the million-dollar question posed as my headline?
After a disappointing and challenging 2012, global semiconductor executives believe that the worst is nearly behind them, and they are making investments to position their companies for a sustained, broad-based, multi-year recovery in 2013, as per a KPMG global semiconductor survey.
On Feb. 3, the Semiconductor Industry Association (SIA) announced that worldwide semiconductor sales for 2012 reached $291.6 billion, the industry’s third-highest yearly total, ever but a decrease of 2.7 percent from the record total of $299.5 billion set in 2011. Total sales for the year narrowly beat expectations from the World Semiconductor Trade Statistics (WSTS) organization’s industry forecast.
The World Semiconductor Trade Statistics (WSTS) estimated that the global semiconductor market in 2012 will be $290 billion, down 3.2 percent from 2011, followed by a recovery of positive 4.5 percent growth to $303 billion in 2013.
The worldwide semiconductor revenue is projected to total $311 billion in 2013, a 4.5 percent increase from 2012 revenue, according to Gartner Inc. The worldwide semiconductor revenue totaled $298 billion in 2012, a 3 percent decline from 2011 revenue of $307 billion, according to preliminary results by Gartner.
The outlook for the global semiconductor industry in 2013 will likely be 7.9 percent, according to Future Horizons. It means, the industry will likely grow to $315.4 billion in 2013. The Cowan LRA foreasting model put out the following sales and year-on-year sales growth numbers for 2012 and 2013: $292.992 billion (-2.2 percent) and $309.244 billion (+5.5 percent), respectively.
Databeans expects 2013 will see a rebound, with the semiconductor industry growing by 7 percent from 2012 totals to reach $313.04 billion. IDC forecasted that the worldwide semiconductor revenues will grow 4.9 percent and reach $319 billion in 2013.
IHS iSuppli claimed that the semiconductor silicon revenue will close 2012 at $303 billion, down 2.3 percent from $310 billion in 2011. The projected decline comes in contrast to the 1.3 percent gain made last year.
IC Insights forecasted 6 percent IC unit growth for 2013 based on expectations of global GDP to rise to 3.2 percent. According to IC
Insights, in 2017, China is expected to represent 38 percent of the worldwide IC market, up from 23 percent, 10 years earlier in 2007. Does this mean the USA and Europe are loosing their sheen?
The global semiconductor industry may record only 1.5 percent growth In 2013, as per The Infornation Network. There is, however, the possibility for a snap-back in revenues for 2013, irrespective of macroeconomic factors, such as what occurred in 2010.
Over the next three years, industry analysts estimate the global industry will grow approximately 6 percent 2013-2016 CAGR, according to Somshubro Pal Choudhury, managing director, Analog Devices India Pvt. Ltd.
Late 2012, I was speaking with Dr. Wally Rhines, chairman and CEO, Mentor Graphics. He said: “After almost no growth in 2012, most of the analysts are expecting improvement in semiconductor market growth in the coming year. Currently, the analyst forecasts for the semiconductor industry in 2013 range from 4.2 percent on the low side to 16.6 percent on the high side, with most firms coming in between 6 percent and 10 percent. The average of forecasts among the major semiconductor analyst firms is approximately 8.2 percent.”
WSTS also anticipates the world market to grow 5.2 percent to $319 billion in 2014, with healthy mid single digit growth across most of geographical regions and semiconductor product categories, supported by the healthier economy of the world.
Lastly, Forbes said that 2013 will be a turning point for the global semiconductor market.
According to Malcolm Penn, CEO, Future Horizons, the outlook for the global semiconductor industry in 2013 is likely to be +7.9 percent. This means, the global semiconductor industry will likely grow to $315.4 billion in 2013.
Should this happen, it would be significant, given that this is the third year in a row that the market failed to break the $300 billion barrier! The global semiconductor clocked around $292.3 billion in 2012, as against $299.5 billion In 2011.
I asked Malcolm Penn the rationale behind this. He said, the rationale is exactly the same as that for 2012. There is said to be no change to last year’s fundamental market analyses. That’s not all! There are likely to be exactly the same (economic) downside risks as well.
The unit demand, capacity and ASPs are all ‘positively aligned’. Here, it is advised that one should never underestimate the economy’s capacity to derail the chip market. Even the downside forecast has been to break the $300 billion barrier.
The global chip industry growth is driven by four factors. These are economy, which is on hold due to complete loss of confidence, unit demand, which is back on the 10 percent per annum treadmill (inventory gone), fab capacity, which is currently tight (very), especially at the leading technology edge, and ASPs, which are structurally following the usual ups and downs.
There is a very safe, long-term bet, provided companies execute properly. As it is, most firms don’t, as they are too pre-occupied with chasing short-term targets.
Finally, if the year 2013 does show a recovery, the global semiconductor market will likely go ballistic in 2014.
How will 2013 turn out to be for the global semiconductor industry? Will there be growth for the global EDA industry? Importantly, how will the Indian semiconductor industry perform in 2013? I asked Jaswinder Ahuja, corporate VP and MD, Cadence Design Systems India these questions.
Outlook for global semicon industry in 2013
First, how is the outlook for global semiconductor industry in 2013 going to be? Ahuja said: “The long term outlook for the semiconductor industry remains positive, with mobility and cloud computing being the key drivers. The global economy is forecast to grow around 4 percent annually through 2016, according to an April 2012 report from the International Monetary Fund (IMF).
“In its June 2012 report, Gartner predicted growth in electronics and semiconductor industries to outpace that of the world GDP growth, at 5½ percent annually to approach $2 trillion for electronics and 6 percent annually for semiconductors through 2016. So, the semiconductor industry outlook remains very positive overall.
“In the near term, multiple challenges will need to be weathered with respect to the global economic climate, especially in European markets. The JP Morgan/GSA Semiconductor Index of Leading Indicators points to a soft semiconductor industry in 2013. However, there are lot of new products in the mobile and tablet space that are driving demand, such as the iPhone 5, Microsoft Surface, and Samsung Galaxy S III.
“The China semiconductor space is emerging as a key market for semiconductor company revenue, and forecasts predict that it will show rapid annual growth rate. The consolidation and M&A activities that we are seeing in the global semiconductor industry also indicate a positive outlook for the upcoming year.
“In India as well, the semiconductor industry will continue to see growth. The injection of funds and other support outlined in the National Policy on Electronics will provide an impetus to home-grown design and manufacturing, which should start gaining traction in 2013.”
Five trends for 2013
What would be the three or five trends likely to be visible in 2013? Ahuja said Cadence sees five big trends that will drive growth in the near and long term. These are: mobility, application driven design, video, cloud and security.
Probably, the most pervasive change in electronics recently has been mobility. When we talk about mobility, it’s just not about smart phones or tablets, but any kind of device which is mobile. Within the mobile space, software applications help system manufacturers and vendors differentiate themselves and stand apart from the competition. The need to have apps on all kinds of devices is driving rapid growth, as well as placing new demands on EDA companies.
The entertainment industry will be the key driver for video, and as the year progresses, we will continue to see more and more products and solutions introduced to tap into the demand. For the semiconductor industry, video will drive growth both in the end consumer market (mobile platforms) and the enterprise space (networking industry).
In many ways, the backbone to mobility is the cloud. With its network servers and infrastructure, the cloud is what delivers much of the content and value to all of those mobile devices. Statistics show that we need one server for every 600 smart phones and one for every 120 tablets. So there is a big need for data centers which can provide support for all the computing and back-end operations.
Security of data in mobile devices and the cloud will continue to be a challenge in the near future. There will be renewed calls to develop products that can protect critical infrastructure and sensitive information from security breaches.