The EDA 360 was an industry vision. It reflected a change in market requirements. It was application driven system design. From a Cadence perspective, the company has done system design enablement, according to Nimish Modi, senior VP, marketing and business development, Cadence Design Systems Inc.
In Apple’s case, the iOS is unique. Cadence feels that the heart of the design is the SoC. The electrical analysis is becoming very important. For instance, how do you optimize before tape-out? Hardware and software conversion presents a huge problem as well. The IP plays an important part. Cadence did IP-as-a-service. It now has an IP strategy.
Today, EDA is about possibility, not productivity. Cadence provides tools and content for semiconductor and systems companies. It is now realizing the EDA 360 vision.
According to Modi, each IP is immensely complex. Standards based or interface IP is not enough! Silicon-proven design is the need of the hour. Now, more and more IP blocks are said to be coming together.
Cadence is offering the Palladium XP, and its primary use is for system verification. Software development is becoming a little bit difficult. People are providing software prototypes. The Palladium compile, turnaround and debug are very fast, best-in-class. All memory, clocking, partitioning, etc., is now automated.
The capacity of the Protium platform is 100 million gates. It will enable hardware and software developers. The use model for Protium is:
* Hardware folks use it for hardware regression.
* Software folks use it for early software development.
The main value proposition is the faster bring-up time. Also, the Palladium hybrid model helps customers overcome the boot problem. It is a hybrid of emulation and virtual prototyping. The dynamic power analysis is another issue. The Palladium hybrid model helps to do the testing.
Collaboration with ARM
ARM provides processor IPs. Cadence works closely with ARM. Cadence is also co-optimizing its tools to provide the best PPA. Physical libraries and tools get optimized. Cadence’s tools are optimized for ARM architecture. Cadence is also the first ones on the access to the V8 ARM models.
According to Vasudevan Aghoramoorthy, VP at Wipro Technologies, a product-centric approach targets multiple customers as well as diverse needs.An example is the desktop server. He was delivering the guest keynote on day two at the CDNLive 2014 in Bangalore, India.
For an app-centric approach, it addresses one specific market and has multiple end customers.Examples are set-top boxes and mobile phones. A services-centric approach addresses the service providers’ needs. Examples would be PoS machines, base stations, ATMs, patient monitors, etc.
A customer-centric approach has diverse needs. These are faster time-to-market, diversification into complementary markets, reduction in product costs, completion of product portfolio, market development, expansion and customization, as well as leveraging analytics.
As a case study, he referred to Wipro engineering a low-cost, low-power ATM with battery back-up. It has been implemented with multi-language display and voice instruction, with spoil-proof keyboard. It also has a fingerprint biometric reader, and serves as a tamper-proof machine for secured transactions.
What did the product development process achieve? Product cost was reduced by 60 percent, and power consumption was reduced by 50 percent. The concept to deployment time was 10 months. An innovative design was used to address the strict power requirements. Wipro used an agile approach to develop the product.
Another case was of a patient-monitoring machine at a fraction of the cost. There was cost reduction by 5X at the physician’s end and 50 percent at the patient’s end. There was ease of use for physicians as connectivity options were enabled for smartphones and tablets.
All of these cases tell us that the product development ecosystem must be efficient. Product management and understanding use cases are key. In Wipro’s case, the development methodology was adapted to market needs. Product differentiation can be done by software. There is a need for cross-disciplinary engineering skills. It will lead to newer methodologies, enabling joint reviews in collaboration for cross-disciplinary projects.
Market opportunities are available for product development and retaining value. Market-driven needs drive innovation, and possibly, lead to the growth of the ESDM sector in India.
According to Charlie Huang, senior VP, Worldwide Field Operations and System & Verification Group, Cadence, today, we are talking about tremendous data growth. Mobile has been driving the growth of semiconductors, besides medical, industrial, consumer and automotive electronics as well. Trends are also driving disruptive opportunities — from driving growth in China to growth in India. He was delivering the keynote on day two at the CDNLive 2014 in Bangalore, India.
"We can innovate to build things that are yet to be imagined. Greater things are yet to come for the Indian semicon design opportunities.
"Today, the iPad has become a system of systems. Now, everyone is waiting for the next big thing. People are also talking about the IoT. Everything will get revolutionized by the newer SoCs. Diverse requirements for IoT have been evolving. There are development challenges from all directions. More functions also means that more IP cores need to be integrated and verified. The IP cores per SoC is likely to be 123 in 14nm, from 108 in 20/22nm. The complexity is just unimaginable!
"Eighty percent of SoC development costs come from software, verification and validation. We should now look at innovating software design with SoC design.
Cadence has invested substantially in IP. It enables system design enablement from end product down to chip level. System-level design with high level synthesis is used to shorten the development cycle and get better quality of results (QoR).
IoT gathering pace as revolution: Guru Ganesan
By 2020, there will be over 8 billion people on our planet. This will also bring tremendous innovations and challenges. ARM has been connecting intelligence at every level, said Guru Ganesan, president and MD, ARM India.
He was delivering the guest keynote at the recently held CDNLive 2014 event in Bangalore, India.
Newer apps are helping connect with the world. As per Gartner, $27 billion worth apps were downloaded in 2013. By 2020, this is estimated to rise to $80 billion.
According to Ganesan, consumer trends are driving innovation in embedded apps, including rich user interface (UI). ARM is also at the heart of wearable technologies, for example, Smart Glasses from Google. Some examples from India include Lechal from Ducere Technologies, GOQ Pi remote fitness companion, Fin+ navigation and device control gesture based device from RHLVision, and Smarty Ring that brings instant smartphone alerts to your fingers from Chennai.
So, what are the key requirements for wearables? These are video/image, audio, display, software, OS, connectivity and battery life! In 2013, over 1 billion smartphones were shipped. Further, mobile data 12 times over between now and 2018.
In medical electronics, besides humans, it has extended to keeping the cattle healthy and have intelligent agriculture with OnFarm, by using sensors. IoT as a revolution is gathering pace. As per a survey conducted by ARM, 95 percent of the users expect to be using IoT over the next three years. Common standards are being developed for interoperability. Similarly, mobility and connectivity are also happening in automotives.
Now, let’s see the development challenges for high-end embedded. Embedded applications today integrate more functions. Consequently, design and verification challenges continue to grow. Further, lot of smart devices are now generating lot of data. The question is: how are we using that data?
Ganesan added that by 2020, there will be new challenges in transportation, healthcare, energy and education. Once devices start communicating with each other, we are likely to see the evolution of a smart infrastructure.
There have been several innovations of innovations happening in the global technology industry. The IoT, mobility, cloud computing, etc., are creating opportunities for the system of systems, according to Lip-Bu Tan, president and CEO, Cadence Design Systems Inc.
Tan was delivering the main keynote. at the recently held CDNLive 2014 in Bangalore, India,
Some of the trends driving the global semiconductor market growth in the end markets include automotives at $24 billion, computers at $76 billion, industrial electronics at $14,1 billion, medical electronics at $12.5 billion, and mobile phones at $100 billion. In India, especially, a lot of fabless companies are said to be coming up.
The tablet is a system of systems. It has communications, navigation, recording and photography, etc. Even the automotive vehicle is a convincing example. Next, there is the IoT. There are said to be diverse needs for the IoT.
There are said to be several challenges for the system of systems. Some of these are more IP and software requirements, and more needs for low power and mixed signal. System design enablement requires system integration, packaging and board, etc.
Cadence has a comprehensive SoC IP solution. The mixed signal verification solution ensures functionality, reliability and performance. Cadence also introduced the Voltus-Fi custom power integrity solution in Shanghai the week before. Its Quantus QRC extraction solution gives up to 5X performance.
Next, the Jasper acquisition expands the Cadence development suite. Cadence also provides the FPGA-based prototyping with Palladium flow for software development.
Tan concluded that new technologies always require closer collaboration — from IP through manufacturing. Cadence is here to help designers innovate — from systems to silicon.
Cadence Design Systems Inc. recently announced the Quantus QRC extraction solution had been certified for TSMC 16nm FinFET.
So, what’s the uniqueness about the Cadence Quantus QRC extraction solution?
KT Moore, senior group director – Product Marketing, Digital and Signoff Group, Cadence Design Systems, said: “There are several parasitic challenges that are associated with advanced node designs — especially FinFET – and it’s not just about tighter geometries and new design rules. We can bucket these challenges into two main categories: increasing complexity and modeling challenges.
“The number of process corners is exploding, and for FinFET devices specifically, there is an explosion in the parasitic coupling capacitances and resistances. This increases the design complexity and sizes. The netlist is getting bigger and bigger, and as a result, there is an increase in extraction runtimes for SoC designs and post-layout simulation and characterization runtimes for custom/analog designs.
“Our customers consistently tell us that, for advanced nodes, and especially for FinFET designs, while their extraction runtimes and time-to-signoff is increasing, their actual time-to-market is shrinking and putting an enormous amount of pressure on designers to deliver on-time tapeout. In order to address these market pressures, we have employed the massively parallel technology that was first introduced in our Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution to our next-generation extraction tool, Quantus QRC Extraction Solution.
“Quantus QRC Extraction Solution enables us to deliver up to 5X better performance than competing solutions and allows scalability of up to 100s of CPUs and machines.”
Support for FinFET features
How is Quantus providing significant enhancements to support FinFET features?
Parasitic extraction is at the forefront with the introduction of any new technology node. For FinFET designs, it’s a bit more challenging due to the introduction of non-planar FinFET devices. There are more layers to be handled, more RC effects that need to be modeled and an introduction of local interconnects. There are also secondary and third order manufacturing effects that need to modeled, and all these new features have to be modeled with precise accuracy.
Performance and turnaround times are absolutely important, but if you can’t provide accuracy for these devices — especially in correlation to the foundry golden data — designers would have to over-margin their designs and leave performance on the table.
How can Cadence claim that it has the ‘tightest correlation to foundry golden data at TSMC vs. competing solutions’? And, why 16nm only?
According to Moore, the foundry partner, TSMC, asserts that Quantus QRC Extraction Solution provides best-in-class accuracy, which was referenced in the recent press announcement:
“Cadence Quantus QRC Extraction Solution successfully passed TSMC’s rigorous parasitic extraction certification requirements to achieve best-in-class accuracy against the foundry golden data for FinFET technology.”
FinFET structures present unique challenges since they are non-planar devices as opposed to its CMOS predecessor, which is a planar device. We partnered with TSMC from the very beginning to address the modeling challenges, and we’ve seen many complex shapes and structures over the year that we’ve modeled accurately.
“We’re not surprised that TSMC has recognized our best-in-class accuracy because we’re the leader in providing extraction solutions for RF designs. Cadence Quantus QRC Extraction Solution has been certified for TSMC 16nm FinFET, however, it’s important to note that we’ve been certified for all other technology nodes and our QRC techfiles are available to our customers from TSMC today.”
At the recently held Semicon West 2014, Daniel P. Tracy, senior director, Industry Research and Statistics, SEMI, presented on SEMI Materials Outlook. He estimated that semiconductor materials will see unit growth of 6 percent or more. There may be low revenue growth in a large number of segments due to the pricing pressures and change in material.
For semiconductor eequipment, he estimated ~20 percent growth this year, following two years of spending decline. It is currently estimated at ~11 percent spending growth in 2015.
Overall, the year to date estimate is positive growth vs. same period 2013, for units and materials shipments, and for equipment billings.
For equipment outlook, it is pointing to ~18 percent growth in equipment for 2014. Total equipment orders are up ~17 percent year-to-date.
For wafer fab materials outlook, the silicon area monthly shipments are at an all-time high for the moment. Lithography process chemicals saw -7 percent sales decline in 2013. The 2014 outlook is downward pressure on ASPs for some chemicals. 193nm resists are approaching $600 million. ARC has been growing 5-7 percent, respectively.
For packaging materials, the Flip Chip growth drivers are a flip chip growth of ~25 percent from 2012 to 2017 in units. There are trends toward copper pillar and micro bumps for TSV. Future flip chip growth in wireless products are driven by form factor and performance. BB and AP processors are also moving to flip chip.
There has been growth in WLP shipments. Major applications for WLP are driven by mobile products such as smartphones and tablets. It should grow at a CAGR of ~11 percent in units (2012-2017).
Solder balls were $280 million market in 2013. Shipments of lead-free solder balls continues to increase. Underfillls were $208 million in 2013. It includes underfills for flip chip and packages. The increased use of underfills for CSPs and WLPs are likely to pass the drop test in high-end mobile devices.
Wafer-level dielectrics were $94 million market in 2013. Materials and structures are likely to enhance board-level reliability performance.
Die-attach materials has over a dozen suppliers. Hitachi Chemical and Henkel account for major share of total die attach market. New players are continuing to emerge in China and Korea. Stacked-die CSP package applications have been increasing. Industry acceptance of film (flow)-over-wire (FOW) and dicing die attach film (DDF) technologies are also happening.