We are in December, and its time for outlook 2014! First, I met up with Neeraj Varma, director-Sales, India, Xilinx. He said: “We expect the 28nm to do really well. From Apr. 13-Mar. 14, we expect revenues worth $250 milion from the 28nm line.
“We are now looking at the embedded market – and expect about $2 billion serviceable available market (SAM). We are looking at $8 billion SAM at the ASIC/ASSP displacement market, and of course $6 billion SAM for core PLD.” After a long time, Xilinx has been seeing positive capex. “We are entering a growth cycle for service providers and enterprises,” he added.
A macro view of capex equipment spend is driven by LTE 27.2 percent at 2011-16, and optical networks 15.9 percent. The other areas include data center, enterprise switching and routing, and service provider switching and routing. Next, 3D ICs will enable Nx100G OTN, 400G OTN, MuxSAR, as well as top of the rack switch, I/O virtualization.
Earlier, there were less than 50 ASICs start in communications in the top 10 OEMs. There were less than 20 28nm ASIC starts in at top 10 OEMs. As of 2012, less than 50 percent of the top 16 ASSPs vendors were losing money. Customer needs are diverse now. Companies end up over designing a chip. People end up paying for what trey are not using.
Xilinx is offering the SMARTCORE IP for smarter networks and data centers. “40 percent of our wins have been achieved by integrating or displacing ASICs and ASSPs,” he said. “We have 25 percent total wins across a broad set of apps/portfolio.”
Some other gains for Xilinx:
* Xilinx gained 3 percent increase in PLDs.
* In wired and data centers, it has 12-percent CAGR from 2013-16.
* In wireless, it has 10-12 percent CAGR.
* In automotive smarter vision, it has 20 percent CAGR growth.
* In industrial, scientific and medical (ISM), it has 12 percent CAGR growth.
* In FY13E-FY16E, Xilinx expects to grow 8-12 percent, and has plans to increase the R&D revenue to 8.6 percent.
Xilinx Inc. has taped-out the first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture. It is said to be the semiconductor industry’s first 20nm device, and the PLD industry’s first 20nm All Programmable device. Xilinx implemented the industry’s first ASIC-class programmable architecture called UltraScale.
These milestones expand on Xilinx’s industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite. Xilinx already has several firsts in the 28nm space, such as:
* First 28nm tape-out.
* First All Programmable SoC.
* First All Programmable 3D IC.
* First SoC-strength design suite.
Neeraj Varma, director-Sales, India, said that Xilinx’s global market share in the 28nm portfolio was 65 percent in March 2013. With the launch of the industry’s first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture, there are improvements such as 1.5-2x performance and integration, and a year ahead of the competition. It handles massive I/O bandwidth, massive memory bandwidth, massive data flow and routing, and fastest DSP processing. The architecture will scale — from monolithic to 3D IC, planar to FinFET, and ASIC-class performance.
The UltraSCALE architecture points to high performance smarter systems. For example, 1Tps in OTN networking, 8K in digital video, LTE-A in wireless communications, and digital array in radar. There will be requirements for massive packet processing over 400 Gbps wire-speed, massive data flow over 5Tbps, as well as massive I/O and memory bandwidth over 5Tbps, and DSP performance over 7 TMACs.
The mandate for ASIC-class programmable architecture is to remove bottlenecks for massive data flow and smart processing, high throughput with low latency, and efficient design closure with greater than 90 percent utilization without performance degradation. These are the benefits of applying leading edge ASIC techniques in a fully programmable architecture.
ASIC-like clocking maximizes performance margin for highest throughput. UltraSCALE ASIC-like clocking enables clock placement virtually anywhere on the die, making the clock skew problem go away. Also, highly optimized critical paths remove bottlenecks in DSP and packet processing. There is greatly enhanced DSP processing, high-speed memory cascading, and hardened IP for I/O intensive functions.
Next generation power management features also enable a leap in performance. The process node is up to 35 percent static at 20nm. There are more buffers for granular or coarse clock gating. Block RAM is dynamic power gating, hardened cascading. For transceivers, there are architectural optimizations. There is efficient packing and utilization of the logic fabric. For DSP, there are wider multipliers and fewer blocks per function. As for memory, there is DDR4, which operates at 1.2v vs.1.5v, voltage scaling.
The Xilinx KINTEX UltraSCALE will power 4×4 mixed-mode radios, 100G traffic manager NICs, super high-vision processing, 256-channel ultrasound and 48-channel T/R radar processing. The Xilinx VIRTEX UltraSCALE will power 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G muxponder and ASIC prototyping.
Xilinx worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The Xilinx Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in Q4-2013.
Today, the challenge is all about abstraction and putting automation around it. Productivity is automation and abstraction. Tom Feist, senior marketing director, Design Methodology Marketing, Xilinx said that the company’s strategy has been about All Programmable abstractions. He was speaking at the ongoing 13th Global Electronics Summit being held in Santa Cruz, USA.
Today’s hardware design abstractions include accelerated time to integration, abstracting hardware. For IP abstractions, Xilinx has introduced the IP integrator. It enables IP re-use and time to integration. The Vivado uses multiple plug-and-play IP. Vivado IP integrator is co-optimized for platforms and for silicon, respectively.
Vivado IP integrator has features such as correct-by-construction and automated IP systems. Vivado high-level synthesis allows C/C++ abstractions. Xilinx introduced the OpenCV library, accelerating smarter vision. It supports frame-level processing library for PS. It also supports pixel processing interfaces and basic functions for analytics.
Mathworks has model based abstraction. The automatic C and HDL code generation is supported from the same algorithmic level.
Hardware/software partitioning is supported for Zynq-7000 AP SoCs. There are comprehensive video, motor control and signal processing IP libraries. There are automated workflows targeting Xilinx platforms.
Xilinx is also working with National Instruments. The automated C and HDL code generation is from the same graphical syntax in the LabVIEW IDE. It automatically generates a hardware implementation to meet requirements, abstracting Xilinx tool flow. There is a comprehensive software, hardware and I/O platform for creating control and monitoring systems.
Abstraction evolution has evolved to system level abstraction. It is abstracting all hardware through an increasing layer of automation.
All Programmable realization empowers software and systems engineers. There is a common compilation environment for heterogenous systems. It consumes C, C++ or OpenCL and libraries with user directives. There is automated flow — the user determines the program modules that run on various components.
The Vivado Design Suite 2013 abstractions with IP based design, C, C++, SystemC and OpenCV is new. Mathworks and National Instruments system level design abstractions with new levels of automation is emerging. Xilinx’s vision has been to empower the software and systems engineers by extending abstractions and automation.
Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.
To find out more about how are Xilinx’s solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: “Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the VivadoTM Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.
“Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.
“Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp.”
Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?
According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.
Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.
How are the solutions going to address the challenges with ASICs and ASSPs?
He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.
Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.
ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.
Components Direct is a leading source for authorized end-of-life and excess electronic components. The products are guaranteed grade A factory sealed direct from the manufacturer and inventoried in a ESD 20.20 certified and ISO 9001 certified state-of-the art-facility. Components Direct is headquartered in Milpitas, CA with locations in the US and Asia.
It has a leading cloud-based platform for excess and obsolete (E&O) inventory. In 2012, Avnet and Components Direct entered in a strategic relationship. Components Direct is the exclusive channel for Avnet’s factory authorized excess and end-of-life components.
Compared to leading industry giants, such as Element14 and RS Components, Components Direct, currently, doesn’t have a detailed menu showcasing listed products, at least not on the home page, as yet. One hopes that’ll make an appearance soon.
Speaking on the mission of Components Direct, Anne Ting, executive VP, Marketing said: “Components Direct is the premier authorized distributor for excess and end-of-life electronic components. We are the only company working directly with manufacturers and their franchised distributors to offer 100 percent guaranteed traceable E&O components as well as technology services to combat counterfeit components and other gray market activity.
“For our supplier partners, we enable them to put excess product back into the control of an authorized source, as opposed to the gray market. For buyers, we provide them with a secure, authorized one-stop shop for excess, obsolete and unsold factory components.”
Combating gray market
How important is it to combat the gray market? Why will this endeavor stop/lessen gray market activity?
According to Ting, the gray market is a serious and growing problem. As early as 2008, a study by KPMG and the Alliance for Gray Market and Counterfeit Abatement (AGMA) stated that as much as $58 billion of technology products were passing through the gray market, and the problem has only gotten worse.
The gray market is rampant throughout all industries, with everyone from engineers, to procurement professionals and consumers impacted negatively when the products they purchase are advertised as new and authentic, but in reality could be used, refurbished or even worse, counterfeit.
In fact, a 2012 study by market research firm IHS found that over 12 million counterfeit electronics and semiconductor components
have entered the distribution chain since 2007, with 57 percent of all counterfeit parts obsolete or end-of-life components. Many of these parts make their way into mission-critical industries, such as defense and aerospace, where a malfunctioning counterfeit part can mean the difference between life and death.
While provisions in the 2012 National Defense Authorization Act have enabled the government and trade groups to make some progress towards regulating the supply chain to ensure that components are only sourced directly from the manufacturers or their franchised distributors, the problem has not abated. The Act empowers the federal government to hold contractors financially responsible for replacing counterfeit products.
This, together with other changes, puts more responsibility on suppliers of electronic component to have risk mitigation procedures in place. The issue is become more topical and the industry must act in order to comply with the new legislation.
Components Direct takes this problem seriously, and provides supplier insights and tools to help combat gray market activity. In a recent study we conducted for a leading semiconductor supplier of both analog and digital devices, we discovered that over 124 million units of their product were floating in the gray market across 6,500 plus part numbers.
Over 70 percent of the products were found in Asia, and 20 percent also appeared in both North America and EMEA. The product age spanned many years with date codes of less than one year accounting for 22 percent of their gray market product. A further 5 percent had date codes over 11 years, demonstrating that whether you were an OEM looking for the newest product, or a military sub-contractor looking for obsolete components, no end customer is immune to the presence of unauthorized product.
Components Direct’s technology tools and services track gray market activity and provide suppliers with unprecedented visibility to their product leakage in the gray market by part number, region, data code etc. This data enables our suppliers to trace leakage in their supply chain and lessen potential unauthorized product from getting into the gray market.
Additionally, Components Direct provides suppliers and buyers with a secure, factory authorized channel for selling or purchasing 100 percent guaranteed traceable components. “We only sell products that come directly with manufacturers or their franchised distributors and all our products are inventoried in an ESD 20.20 and ISO 9001 certified facility,” said Ting.As an extension of the manufacturer, Components Direct provides the supply chain buyer with complete confidence and peace of mind that all products originate directly from the manufacturer and have been properly stored, handled and packaged. Sourcing from an authorized source like Components Direct eliminates the risks surrounding product quality, reliability and liability. Read more…
Singapore based Plunify claims that chip design companies can design faster and better using cloud computing. Stressing on the company’s go-to-market strategy, Plunify’s founder, Harn Hua Ng, said the Plunify partners with tool vendors, their distributors and complementary sales representatives.
Since pay-as-you-go business models are rare in the semiconductor industry, we went through several steps, of which the first was to better understand the market, the available tools and stake-holders:
* How is the market reacting to cloud computing and licensing schemes?
* What are current tool capabilities with regards to multiple CPUs/servers? Which parts of the chip design workflow can best take advantage of scalable, parallel features?
* What tools are more suitable for a cloud environment?
With these in mind, the next step was to build the cloud platform and the application clients to address immediate concerns – security, accessibility and cost.
“Then, we partner with tool vendors, their distributors and sales reps to bring our solutions to end-users. Companies of different sizes
view the advantages of cloud computing differently, so solutions need to be customized accordingly. Some see Plunify as solving longer term IT problems of scaling and provisioning; while others use us as an immediate way to speed up their design workflows. We are still in the process of learning about the market.”
How can the on-demand cloud computing platform dramatically accelerate chip design workflows? According to Harn Hua Ng, one immediate benefit is an almost instantaneous fulfillment of peak demand IT requirements, for example, a urgent request to do 100 synthesis builds to fix a problem due yesterday. Or if the problem cannot be fixed, at least the design team will find out in a day rather than potentially in three months’ worth of runtime without a cloud solution. The longer term acceleration is a gradual parallelization of the design workflow.
Currently, chip designers tend to visualize the design workflow as a chain of mostly serial steps with many dependencies, just because many steps can be time-consuming (both in terms of runtime and time taken to analyze intermediate results).
With an on-demand compute platform, designers can have more room to experiment and to optimize, more readily incorporating agile practices in hardware development.
Xilinx Inc. has announced its 20nm portfolio strategy. The 20nm portfolio will allow Xilinx to offer twice the performance at half the power. It will increase productivity by 4x, and improve integration by 1.5- 2x. Besides, there will be 20-50 percent lower BOM cost.
Xilinx’s 20nm all programmable portfolio builds on 28nm breakthroughs to stay a generation ahead. ”At 20nm, we were able to break out to become an all programmable company,” said Neeraj Varma, country manager, sales, India, Australia and New Zealand, Xilinx India.
The next generation FPGAs, second generation SoCs and 3D ICs will be ‘co-optimized’ with Vivado for the most compelling alternative ever to ASICs and ASSPs. From enabling programmable logic, the Xilinx 20nm portfollio will enable programmable systems integration!
The first SoC strength design suite was shipped in Q2-2012. It has been built from ground up for the next decade of all programmable devices. Today, the Xilnix Vivado is used for over 30 percent of 28nm FPGAs and 100 percent for 3D ICs.
Xilinx has been expanding on its next generation competencies. The 3D IC expertise and supply chain has gone from homogenous to heterogenous. The SoC and embedded software has also undergone change, as have XCVRs and analog mixed signal (AMS), communications BU and applications IP, and next generation design automation. Xilinx is now charting an aggressive course forward.
Xilinx’s 20nm portfolio has been co-optimized for performance, power and integration to address the market needs at 20nm. For the next-generation FPGA,, it will provide unmatched system optimized transceivers at highest channel quality w/ second generation auto equalization. There will be higher bandwidth w/over 100 transceivers @ 33Gb/s.
There will be 2X performance optimization, with faster DSP and BRAM, DDR4, transceivers and 2x memory bandwidth. There will be over 90 percent routing architecture enabling high bandwidth bussing and fast design. One half power optimization will provide an optimized performance/watt. There will be next generation block level power management. There will be 1.5x integration/BOM in terms of 1.5x logic, DSP, BRAM, AMS, VCXO, etc. Read more…
Xilinx Inc. has announced the Vivado Design Suite. It enables an IP and system centric next generation design environment. Especially meant for the next decade of ‘All-Programmable’ devices, it also accelerates the integration and implementation up to 4X. And, why now? That’s because the all-programmable devices enable programmable systems ‘integration.
There are system integration bottlenecks, such as design and IP re-use, integrating algorithmic and RTL level IP, mixing DSP, embedded, connectivity and logic, and verification of blocks and “systems”.
There are implementation bottlenecks as well, such as hierarchical chip planning, multi-domain and multi-die physical optimization, predictable ‘design’ vs. ‘timing’ closure, and late ECOs and rippling effect of changes.
Vivado accelerates productivity up to 4X. The design suite elements include an integrated design environment, has a shared scalable data model, is scalable to 100 million gates, and debug and analysis. It shares design information between implementation steps that ensures fast convergence and timing closure. This enables highly efficient memory utilization. Also, it is scalable to future families, that are greater than 10 million logic cells (100 million gates) and enables cross-probing across the entire design.
Vivado also enables packaging designs into system-level IP for re-use. You can share IP within your team, project or company. Any 3rd party IP is delivered with a common look and feel. You can re-use IP at any point in the implementation process. The IP can be source, placed, or placed and routed.
Moshe Gavrielov, president and CEO, Xilinx Inc. was in Hyderabad, India to inaugurate Xilinx India’s new, expanded India site at Hi-Tech city. The new Hyderabad site is a 131,000 square-foot office building — more than 2X the size of the previous site. It is equipped with engineering labs for end-to-end development and has a larger, energy-efficient data center. It also has facilities for customer and employee events.
This site is Xilinx’s largest R&D centre outside of US headquarters. Pivotal to record-fast delivery of 28nm technologies, it has a stellar worldwide technical support team. Xilinx has been committed to be the first to process nodes. It is pioneering 3-D IC technology and leading edge processing sub-systems. It is also offering programmable analog/mixed signal solutions as well as system to IC tools and IP to enable silicon.
Gavrielov said that Xilinx’s business drivers have been the programmable imperative, relentless system integration and an insatiable intelligent bandwidth. The programmable imperative has further accelerated. For instance, 28nm = 2X 45nm cost. Insatiable bandwidth has now expanded to Latin America. It is said to be almost 2x the size of the US market. There has been 20 percent growth in mobile subscribers and 318 percent growth in Facebook users.
There has been insatiable bandwidth across India as well, while bandwidth is also said to be growing in Africa. Some of the trends driving insatiable intelligent bandwidth include extreme bandwidth – which has seen 5X growth in five years, smart vision, ubiquitous computing and embedded security. Read more…