Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?
Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”
Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?
According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.
He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.
“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”
Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?
“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”
What will be the impact of transistor variability and other physics issues?
As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Some time ago, Cadence Design Systems Inc. had announced the EDA360 vision! As per Jaswinder Ahuja, corporate VP and MD of Cadence Design Systems India, the Cadence vision of EDA360 is said to be well and alive. The organization has been aligned around the EDA360 vision.
The EDA360 is a five-year vision for defining the trends in the EDA industry, based on what Cadence is observing in the industry and the direction in which, it feels, the industry will go.
At Cadence, the Silicon Realization Group is headed by Dr. Chi-ping Hsu. The SoC Realization Group is headed by Martin Lund, and Nimish Modi is looking after the System Realization Group. Cadence’s focus has been on in-house development and innovation. Tempus has been a major announcement from the Silicon Realization Group.
What’s going on with EDA360?
There has been a renewed thrust in the SoC Realization Group at Cadence. Already, there have been three acquisitions this year — Cosmic Circuits, Tensilica and Evatronix. Cadence is buying the IP part of the business from Evatronix. This acquisition is ongoing and will be announced in June 2013.
On the relationship between the electronics and the EDA industries, Ahuja said the electronics industry is going through a transition, and that the EDA industry needs to change. The importance of system-level design has increased. Companies are currently focusing on optimizing the end user experience.
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.
Status of global EDA industry
First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”
For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.
Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.
In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.
DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.
Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”
According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”
“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.
Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash.
With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto infotainment and home applications.
The Tensilica IP also complements industry-standard processor architectures, providing application-optimized subsystems to increase differentiation and get to market faster. Finally, over 200 licensees, including system OEMs and seven of the top 10 semiconductor companies, have shipped over 2 billion Tensilica IP cores.
Talking about the rationale behind Cadence acquiring Tensilica, Pankaj Mayor, VP and head of Marketing, Cadence, said: “Tensilica fits and furthers our IP strategy – the combination of Tensilica’s DPU and Cadence IP portfolio will broaden our IP portfolio. Tensilica also brings significant engineering and management talent. The combination will allow us to deliver to our customers configurable, differentiated, and application-optimized subsystems that improve time to market.”
It is expected that the Cadence acquisition will also see the Tensilica dataplane IP to complement Cadence and Cosmic Circuits’ IP. Cadence had acquired Cosmic Circuits in February 2013.
What are the possible advantages of DPUs over DSPs? Does it mean a possible end of the road for DSPs?
As per Mayor, DSPs are special purpose processors targeted to address digital signaling. Tensilica’s DPUs are programmable and customizable for a specific function, providing optimal data throughput and processing speed; in other words, the DPUs from Tensilica provide a unique combination of customized processing, plus DSP. Tensilica’s DPUs can outperform traditional DSPs in power and performance.
So, what will happens to the MegaChips design center agreement with Tensilica? Does it still carry on? According to Mayor, right now, Cadence and Tensilica are operating as two independent companies and therefire, Cadence cannot comment until the closing of the acquisition, which is in 30-60 days.
Last month, Cadence Design Systems Inc. unveiled an integrated chip planning and implementation solution. This has been achieved through the integration of Cadence InCyte Chip Estimator and the Cadence Encounter Digital Implementation (EDI) System technologies.
Cadence has called this breakthrough solution, which provides design and implementation engineers with superior visibility and predictability of chip performance, area, power consumption, cost, and time to market across the full range of design activities, including system-level design and IP selection through final implementation and signoff.
I got into a brief conversation with Adam Traidman, Group Marketing Director, Cadence, Dave Desharnais, Product Marketing Group Director, Cadence, and Rahul Arya, Director, Marketing & Technology Sales, Cadence Design Systems India Pvt Ltd.
EDA industry revenue dips 10.7 percent in Q1-09
By the way, the EDA Consortium (EDAC) Market Statistics Service (MSS) today announced that the EDA industry revenue for Q1 2009 declined 10.7 percent to $1192.1 million, compared to $1334.2 million in Q1 2008, driven primarily by an accounting shift at one major EDA company. The four-quarter moving average declined 11.3 percent.
“The business environment remained difficult for EDA as for other industries, with Q1 EDA revenues declining in all regions except Asia Pacific,” said Walden C. Rhines, EDA Consortium chair and Mentor Graphics CEO and chairman. “Nevertheless, for Q1, the overall decline was less than for the previous quarter.”
Back to the current discussion then! It’d be interesting to see how all these tools bring the EDA industry back above the red level!
Why this solution?
The obvious question, why the Integrated Chip Planning and Implementation Solution now?
Adam Traidman said that the Chip Estimator is quite unique! It helps customers early in the IC design cycle.
“We go beyond EDA and estimate cost, etc. We help the designers to do an early architectural level ecomnomical and techical analysis and estimation, etc. Statistics show that during the early phases of design, those decisions can contribute to 80 percent of final design. Today, very few EDA companies provide set of tools and methodologies that allow such trade-off,” he added.
According to him, every customer does this analysis, probably, manually. Cadence is now automating this method. In this respect, it has integrated chip planning with implementation.
“The results of the analysis — you are concerned about accuracy; you look to the EDA vendors to help converge from initial implementation to the actual convergence. Think of it like a cockpit for the design engineer, general manager, program manager, etc.,” he noted.
“You’ve made all the fundamental decisions, etc. If you’re sitting on the physical implementation tool, and you need think through the implications that can be there. For example, to re-synthesize new libraries, etc. We are talking about chip planning at a much, much higher level,” added Traidman.
Helping with IP selection!
The Cadence solution also leverages the vast ecosystem of IP at the ChipEstimate.com portal where over 200 IP suppliers and foundries contribute data. Helping with IP selection has been mentioned among the processes, perhaps, an indicator that designers may have not been able to select the right IPs all this while.
According to Traidman, IP selection and qiuality are key issues. “A lot of people, doing these tradeoffs, could be design managers, general manager, etc. When they sit with this tool, and when it pops up, they can see a huge library of 7,000 IPs from about 200 IP suppliers and foundries. Any design team can view all of the IPs as a free service,” he elaborated. By the way, ChipEstimate is owned by Cadence!
He further added that the ChipEstimate portal allows customers to lower the risks of converging. The portal has been growing since 2006, and receives 1 million page view each month.
Just for interest’s sake, there’s another site — Design And Reuse — that claims to be the world’s largest directory of 8,000 silicon IPs from more than 400 vendors! I have also got into some other discussions — that are ongoing — for developing a similar site in India, for the Indian semiconductor industry!
What about Cadence Encounter?
Post the integration, what happens now to the Cadence Encounter solution and whether it is still available standalone?
Dave Desharnais said the Cadence Encounter solution is still available standalone. “We have integrated some key functions from InCyte. From InCyte, you would normally not have the link to get into physical implementation. Likewise, with feeding back of a fully realized database,” he said.
Last December (2008), Cadence had announced the Encounter Digital Implementation System, a next generation complete RTL-to-GDSII solution for logic and physical implementation.
Along with a fundamental new memory architecture and end-to-end multicore backplane to address the requirements of leapfrog capacity and faster turnaround time for billion transistor designs, it also delivers complete implementation and signoff-in-the-loop for low power, mixed signal, and advanced node design; including the latest 28nm process node where it has been used on over half of the designs being done at this node today.
As per Rahul Arya, since the initial launch, there has been significant usage and endorsement from the world’s largest semiconductor companies, including ST, Toshiba, NEC, NXP, Fujitsu, AMD, and many more that are requested as non-public endorsements.
He added: “The announcement of InCyte and EDI System integration brings a whole new dimension for both system-level and design implementation teams. While both solutions — InCyte and EDI System — are still available as standalone, using both solutions together enables designers at all levels to now have complete visibility into all aspects of the design — from system level architecture requirements and IP selection, to full physical floorplanning, final low power and implementation signoff results.
“The bringing together of both of these solutions delivers literally unprecedented predictability, visibility, and accuracy into all steps of the chip creation and implementation flow for faster design convergence.”
The design solution will be demonstrated at the Design Automation Conference (DAC 2009) in San Francisco this month and made available later this year.
Recently, Synopsys Inc. introduced an IC Validator design rule checking/layout verification signoff (DRC/LVS) for in-design physical verification and signoff for advanced designs at 45nm and below.
Said to provide a step up in physical designer productivity, it is architected to deliver the high accuracy necessary for leading-edge process nodes, superior scalability for efficient utilization of available hardware, and ease-of-use.
What does IC Validator do?
According to Sanjay Bali, Director of Marketing, Physical Verification & DFM, Synopsys, the IC Validator is a complete physical verification tool, performing increasingly complex DRC and LVS sign-off checks.
It has been specifically architected for in-design physical verification. This means: the place-and-route engineers can run DRC and practical DFM steps alongside place and route within the familiar IC Compiler physical design environment.
And, why need for such a solution? He added that three key summary challenges are driving the need for a new approach and hence the new tool. These are:
a) Increase in complexity and count of manufacturing rules.
b) Unabated growth on design complexity.
c) Increasing DFM challenges, which just cannot be handled in a post processing approach.
Currently, the solution is aimed at 45nm and below as these nodes largely represent the challenges listed above.
Enhancing physical designer’s productivity
Three key tenants of the IC Validator that offer improved physical designer productivity are:
a) High accuracy necessary for leading-edge process nodes.
b) Superior scalability for efficient utilization of available hardware. And,
c) Ease of use with seamless integration of IC Validator and IC Compiler
Bali said: “The IC Validator has been architected from the ground up for in-design physical verification. In-design physical verification enables place-and-route engineers to accelerate the time to tapeout by enabling sign-off quality physical verification from within implementation or physical design. Physical designers designing with IC Compiler can now benefit from the in-design physical verification approach with the push of a button, incurring minimal overhead cost to eliminate surprises late in the design.
“With the verify-as-you-go approach replacing the implement-then-verify approach, physical designers can significantly reduce iteration count, eliminate streamouts and streamins, and accelerate time to tapeout. In addition, the integration enables several productivity enhancing flows like incremental DRC verification, incremental metal fill flows and ECO flows — all leading to significant reduction in time to tapeout.”
It would be interesting to determine or know by approximately what percent is the total physical verification time reduced, and what all does it cover in the process?
Bali added that in extreme cases, finding and fixing DRC violations can easily impact the schedules by a few weeks! The key here is that physical designers typically wait until the final stages of the tapeout to run physical verification. Inevitably, the schedule at this point is squeezed and the cost of fixing the error is high.
“With a sign-off quality physical verification tool integrated into the physical design environment, place-and-route engineers can verify as they implement and eliminate late surprises while speeding up the total physical verification turnaround time. In addition, the outcome of this process is a sign-off clean design.
The Synopsys IC Validator is also said to ‘production ready!” What exactly does that mean?
The IC Validator has been successfully used to tapeout designs at several chip manufacturers, said Bali. In addition, it is currently being used for production designs at Nvidia and Toshiba. Besides other leading foundry’s and chip manufactures it is also qualified by TSMC for 40nm and 28nm process nodes.
For those interested, Toshiba already has Synopsys as its key EDA partner, and NVIDIA adopted the IC Validator for sign-off physical verification, within days of its launch! More are bound to follow!
Saving design spins!
Will the IC Validator approach be able to save design spins? How much is the physical design cycle time reduced?
With the in-design physical verification, place-and-route engineers will be able to run sign-off quality DRC checks, timing aware and sign-off quality metal fill, all within the familiar IC Compiler environment. Linear scalability for efficient use of hardware, sign-off accuracy and integration with IC Compiler will enable productivity enhancing flows like auto detect and autofix, incremental verification flows — all can significantly reduce time to tapeout.
How can it help in avoiding the painful sign-off failure-to-physical-redesign iterations that are increasingly common below 90nm?
With the seamless integration of the IC Validator with the IC Compiler, physical designers can now verify the design as they implement for manufacturing sign-off accuracy.
Incremental DRC’s strength
How good is the incremental design-rule checker (DRC)? Is it really parallelized for the multicore servers?
According to Bali, incremental flows are one of the strongest tenants of IC Validator. To improve physical designer productivity, rule-based only or layer-based only incremental verification runs can be initiated from within IC Compiler.
He said: “For ECO validation, the IC Validator supports window or an area-based incremental verification approach to speed up surgical checks. The incremental flows are meant to be quick, but the IC Validator has multicore capability to further speed up the process.”
The IC Validator discovers and fixes design rule violations within the global context of the design as well. How is this made possible?
With the in-design physical verification, the IC Validator can accurately and automatically identify DRC violation and automatically provide fix guidance to IC Compiler to fix the violation and then re-verify it again.
Handling metal fills and design changes
Operations typically performed during physical verification, such as metal fills, may trigger additional design changes to achieve timing closure. How is this handled by the IC Validator?
Bali said that the prevailing post-processing oriented DFM flows introduce excessive and lengthy discover-fix iterations. Metal fill insertion, a mandatory DFM step at the advanced nodes, exemplifies this issue.
“Physical designers stream out the timing closed post-fill design for signoff validation and then stream it back in to fix any signoff errors flagged during physical verification. This multi-hour discover-fix loop is typically repeated per block till the post-fill design is both signoff qualified and timing clean.
“With in-design physical verification, the IC Validator and IC Compiler address the challenges of DFM, within the place-and-route environment. The seamless integration enables a single pass metal fill flow that is timing aware and of signoff quality and is void of expensive streamouts and streamins,” he added.
This is a continuation of the previous post based on the recent India visit of Hanns Windele, VP Europe and India, Mentor Graphics, where he met key industry figures in a session organized by the India Semiconductor Association. Windele is standing sixth from left, and Poornima Shenoy, president, ISA is standing fifth from right.
Multimode, multicorner tools
Windele mentioned that in every likelihood, another new routing tool would be coming in once the industry enters the 45nm/32nm space. “There is an increasing static timing analysis signoff complexity. The explosive growth in complexity requires multimode and multicorner tools,” he said.
Multicorner and multimode (MCMM) and manufacturing variability will drive the next generation place and route technology. Even in the low-growth markets, technical discontinuities create opportunities for market share changes. For instance, 65nm brings along more than 21 corners/modes scenarios; while 90nm has 10 corners, and 130nm only has four corners.
Therefore, another place and route tool will cover the upcoming MCMM problem. Even in low-growth markets, technical discontinuities create opportunities for market share changes.
Companies cannot afford the growing cost of EDA. Even the cost of design is growing exponentially, especially, verification, as well as embedded software development costs. Even the EDA revenue has been a flat 2 percent of the IC revenue. However, productivity has been growing as the number of engineers don’t seem to be multiplying in a great way. For example, the transistors produced per electronic engineer has been hearly four-orders of magnitude since 1985.
Showing optimism in recession
Turning to the ongoing recession, which has impacted the semiconductor industry, Windele said that 2009 will be most likely turn out to be the worst recession in the history of the global semiconductor industry.
“It seems to be heading that way. There is also a lot of reason for optimism. I feel that 2009 will be a lot milder than 1985 and 2001,” he said. Even the electronics indsutry’s growth rates have been slowing, decade by decade as well.
Therefore, with this ongoing global recession, why should we remain optimistic? Simple! A crisis translates into opportunities!!
Betting on India
No prizes for guessing where the most opportunities lie — India! Significantly, the ‘middle class’ in urban India becoming a majority. There is likely to be $3 trillion of discretionary spending by 2010. “People who can afford electronic and consumer goods will be growing further,” he added.
Windele cited ISA’s figures, which says that India’s electronics consumption is headed toward $300 billion by 2015. India’s electronic equipment consumption will likely grow at a CAGR of 30 percent through 2015. It was around $28 billion in 2005, and is likely to increase to $127 billion by 2010, and to $363 billion by 2015.
Yet another reason is the growing number of new cell phone subscribers in China and India, which will be 2x larger than the total US subscribers until 2011. Asia is, by far, the most attractive market for new cell phone sales. India will grow fastest, he added.
Comparing the downturns of the recent years, Windele noted that 2008 and 2009 look different than the other downturns. “There is hardly any inventory left in the industry. One prediction is: as the price upswing comes, prices in the semicon industry will go up very quickly,” he noted.
Seeds already being sown for recovery in 2010. Already, the industry has experiecned two years of severe price declines in memory. Further, systems will be re-designed to take advantage of lower bit prices of FLASH and DRAM.
There will be consolidation and reduced investment in semiconductor capacity in 2008 and 2009. Ramp-up of new system designs will likely happen in 2010 during the period of reduced semiconductor supply.
Concluding, he added that Mentor Graphics became the number 1 EDA company in Europe as the company managed the crisis better than some of our competitors.
During his recent trip to India, Hanns Windele, VP Europe and India, Mentor Graphics, took time off to meet key leaders from the Indian semiconductor industry over a session organized by the India Semiconductor Association (Windele is seen here admiring a memento presented by the ISA). He presented his observations of the global semiconductor industry.
According to him, the electronics industry is having a roller coaster ride today. “In the past, it was the same for everyone. Today, it is different! Those who have niche products are doing better than others. The economic crisis is accelerating the downturn in the semiconductor industry,” he added. Windele apprised the audience that the IC unit shipments had fallen 15 percent in Q408 (YoY).
Windele touched upon the various forecasts presented by various analysts (see chart). The common thing has been — all analysts have forecasted negative growth. The one key stand out has been Future Horizons, which otherwise remains optimistic, but this time forecast a deep negative growth in the industry.
Is the semicon industry really consolidating?
Given the downturn, is the global semiconductor industry really consolidating, as it should? Windele examined some significant revenue and rankings in an attempt to unravel this case. So, do the big keep getting bigger?
As per the semiconductor concentration of revenue, the No. 1 player has had less share in 2007 than in 1972. Applying the same yardstick with the top five companies, they too have had less share in 2007 than they have in 1972! Extending this to the top 10 companies indicated a similar picture!
This goes on to indicate that the global semiconductor industry has actually been “deconsolidating’ since the 1960s! Windele said that between 1965-72, 29 companies entered the market and captured share from the big companies.
Each decade seems to bring in more change. Also, new product families bring new opportunities. Consequently, leadership seems to be changing regularly as well. For instance, 2008 brought the first fabless company — Qualcomm — into the top 10!
Also, new fab-lite strategies are working as well, with companies such as Texas Instruments (TI), STMicroelectronics, Renesas, and Sony among the top 10 as per the H1-08 list.
Based on these assessments, Windele said that few companies have managed to stay on the top for more than three decades. The top 10 seems to be changing every decade, he added. The global semiconductor industry has definitely NOT been consolidating. The top fabs, however, have definitely been consolidating, but not the fabless! “You need to be with the right product at the right time at the right place, otherwise you’d disappear,” he cautioned.
Why hasn’t consolidation happened?
It would be interesting to note why the global semiconductor industry hasn’t been consolidating (yet)! According to Windele, this could be due to:
* Unlike trends in steel, chemicals and automobiles, etc., the electronics industry achieves a reduction in cost per transistor of about 35 percent per year, every year.
* This change enables totally new applications addressing totally new markets.
* These new applications and markets are driven by innovators that are frequently new entrants into the electronics industry.
Opportunities for change
Once the EDA market stabilizes, would there be opportunities for change? There should be plenty of opportunities!
The place and route market has definitely not been growing. Rather, it has been a flat market over the past several years. Nevertheless, new EDA startups lead each new generation of place and route technology. According to Windele, there will be another new routing tool coming in once the industry enters the 45nm/32nm space.
Part II of this post continues in the next blog post.