Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Speaking about the IDesignSpec, Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable forms and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.
This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.
It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.
In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every 18 months, this time period coming from a different statement concerning transistor performance.
Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.
The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:
Improvements in yield – this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.
Increasing levels of automation – this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.
Introducing larger wafer sizes – this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus at the 300mm transition the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.
It is always a pleasure speaking with Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. I met him on the sidelines of the 13th Global Electronics Summit, held at the Chaminade Resort & Spa, Santa Cruz, USA.
Status of global EDA industry
First, I asked Dr. Rhines how the EDA industry was doing. Dr. Rhines said: “The global EDA industry has been doing pretty well. The results have been pretty good for 2012. In general, the EDA industry tends to follow the semiconductor R&D by at least 18 months.”
For the record, the electronic design automation (EDA) industry revenue increased 4.6 percent for Q4 2012 to $1,779.1 million, compared to $1,700.1 million in Q4 2011.
Every region, barring Japan, grew in 2012. The Asia Pacific rim grew the fastest – about 12.5 percent. The Americas was the second fastest region in terms of growth at 7.4 percent, and Europe grew at 6.8 percent. However, Japan decreased by 3 percent in 2012.
In 2012, the segments that have grown the fastest within the EDA industry include PCB design and IP, respectively. The front-end CAE (computer aided engineering) group grew faster than the backend CAE. By product category, CAE grew 9.8 percent. The overall growth for license and maintenance was 7 percent. Among the CAE areas, design entry grew 36 percent and emulation 24 percent, respectively.
DFM also grew 28 percent last year. Overall, PCB grew 7.6 percent, while PCB analysis was 25 percent. IP grew 12.6 percent, while the verification IP grew 60 percent. Formal verification and power analysis grew 16 percent each, respectively. “That’s actually a little faster than how semiconductor R&D is growing,” added Dr. Rhines.
Status of global semicon industry
On the fortunes of the global semiconductor industry. Dr. Rhines said: “The global semiconductor industry grew very slowly in 2012. Year 2013 should be better. Revenue was actually consolidated by a lot of consolidations in the wireless industry.”
According to him, smartphones should see further growth. “There are big investments in capacities in the 28nm segment. Folks will likely redesign their products over the next few years,” he said. “A lot of firms are waiting for FinFET to go to 20nm. People who need it for power reduction should benefit.”
“A lot of people are concerned about Japan. We believe that Japan can recover due to the Yen,” he added.
Demand for Ethernet networks is growing. It is driven by mobile backhaul and cloud access. The service revenue is forecast to reach $48 billion by 2016 (Ovum, Sept.2012).
Speaking at the 13th Global Electronics Summit at Santa Cruz, USA, Uday Mudoi, Product Marketing director, Vitesse, said that carriers are making a lot of money by providing Ethernet based services. It is required to provide services to enterprises.
Businesses need cloud access. There were multiple solutions. Some were processor based, while some were Ethernet switches or FPGAs. Vitesse has introduced the service-aware switch engines. Vitesse has introduced ViSAA, which is integrated into the Vitesse switch engine.
ViSAA delivers CE networking and MEF services. It has a rich, granular set of per-connection feature control and resource allocation. There is hardware offload of performance-critical functions such as OAM and protection switching. Besides, there is switch resource allocation for support of the internal network operations, independent of service.
ViSAA matters because of wirespeed performance and extremely low power (less than 1.6W for CE access switches). It also offers many services with MEPS and service allocation.
Vitesse has enabled a new generation of access devices. It is an MEF CE 2.0 compliant hardware and software for mobile and cloud. The CE Services software is complementary to ViSAA and simplifies the service provider management.
The Vitesse CE Services software reduces complexity, TTM and development cost for OEMs. It enables rapid deployment of the standardized and differentiated service offerings by the operators. Many of Vitesse’s customers are already CE 2.0 certified.
Vitesse has also introduced the Serval-2 for higher bandwidth mobile backhaul and cloud service delivery. It allows a simple upgrade path to higher speeds, density and scale. When combined with the Vitesse Intellisec-enabled PHYs, the Serval family enables a secure
network for L2 VPN services at 50 percent lower cost than alternative solutions.
The insulated-gate bipolar transistor (IGBT) is a three-terminal power semiconductor device. The main trends impacting IGBT include the power stack trend, revolution of Chinese IGBT, growth of IGBT use in consumer applications, and competition from SiC and GaN based devices, respectively.
According to Alexander Avron, Yole Developpement, current density of the IGBT has been multiplied by 3.5 in 20 years. IGBT technology is now very mature, using trenches and thin wafer. Wafer size for IGBT production is still growing and Infineon is currently the leader.
Infineon expects a cost advantage of 20-30 percent by increasing the wafer size from 8- to 12-inches. For Infineon, the 12-inch production line is for MOSFETSs, and they will probably produce IGBT 600V on thin wafer. Fairchild and IR prefer to remain at 8-inch.
A new generation release is always a low voltage product (600-900V). Main improvements have been in losses reduction. In the IGBT supply chain, vertically integrated companies are Japanese only, besides a few, like ABB. Only a few companies, like Danfoss, take advantage of doing module and inverter for motor drives. In a cost-driven market, there is not much competitive advantage in developing own module.
Trends impacting IGBT
Power stack trend - The need for more modularity and higher performance made components makers (active and passive) to join and create consortiums or JVs. It is trending toward more integration.
Revolution of the Chinese IGBT - First Chinese companies are starting to manufacture IGBTs using standard technology and low cost, perfect for a local market. Asian players are becoming a greater part of the IGBT market. While they do not make a lot of devices as yet, it is expected that they will quickly gain market shares in low cost local businesses.
Some new entrants include CSMC, Hua-Hong NEC, PSMC, BYD, Grace Semiconductor, Alpha & Omega Semiconductor, etc. Many Chinese companies are very close to or already able to manufacture their own IGBTs. This will grow and create a Chinese IGBT.
Growth of IGBT use in consumer applications - IGBTs are becoming more part of the consumer lifestyle. Renewable energies and EV/HEV are good examples. Pioneers of HV IGBT have the best market shares. Margin for HV IGBT modules is high. It is first in the EV/HEV and renewables markets. New markets are targeted by all players.
The ASP evolution of consumer markets has dropped down very fast as compared to the industrial markets. Also, DLB or direct lead bonding is a specific technology from Mitsubishi Electric to produce epoxy molded power modules for hybrid and electric cars. Mass production is targeted for 2013.
Competition from SiC and GaN - Next generation devices are becoming available. They will displace IGBT, but not at all the levels and in all the applications. Characteristics of GaN-based inverters are: they primarily target medium voltage apps (200-600V range). SiC diodes are already in production, mainly coupled with IGBT. Penetration of SiCs in wind turbines will happen later than expected.
As for the 2006-2020 power devices market forecast, Yole expects a more stable growth by 2020. There was an unanticipated slowdown in 2012. The market share in 2011 was Mitsubishi 27 percent, Infineon 23 percent, Fuji Electric 11 percent, etc. The IGBT market share was Infineon 35 percent, Mitsubishi 32 percent, Hitachi 12 percent, ABB 9 percent, respectively.
Yole estimates that at least 15 companies – foundries, fab lights and fabs — are working on IGBT development in China.
MEMS still has a long way to go to meet the challenges of commercialization! Critical success factors include efficient process transfer from breadboard to production. There is a need to pay attention to customers’ needs. More resources need to be adopted from the semiconductor industry, said Roger Grace, president, Roger Grace Associates.
There is a need to create significant awareness as to the unique solution benefits of MEMS based systems and establish defensible product differentiation. Firms need to better understand customer/market needs.
Emerging opportunities include single MEMS based system solutions, especially in analytical instruments, double magnetic MEMS, triple point-of-care bio, energy harvesting/storage, etc. There are barriers to commercialization of MEMS. Until recently, it is plagued by lack of high-volume apps. There is lack of well-defined direction from roadmaps, industry standards and associations. Packaging and testing costs are typically at 70 percent of total value. There is also a lack of focus on customer needs and lack of capital formation opportunities, risk averse investors.
Besides, successive bubble busts, i.e., biomems, optical telecom, have seen wary investors. There are very fragmented markets, many small companies and few large players. Also, there are limited ‘success stories’ of MEMS/MST companies, eg., Invensense. There are new market opportunities for large volume apps, eg. in automotive, CE, etc.
Downturn hit research hard! R&D remains a novelty for most firms. Now, there is an increase in university and R&D labs for MEMS development. There is still plenty of R&D available from DARPA, SBIR and STTRs. Now, we are seeing a healthy amount of activity in new devices and systems research.
As for DfM (design for manufacturing), Invensense’s ‘shuttle’ process may finally become a usable standard. New approaches are also changing the paradigm of cost structure. Examples are Invensense gyros, Freescale chip-stacking accelerometers, ST, etc.
While there seems to be strong MEMS infrastructure, there is some fraying at the ends. The industry needs to remain competitive and lean. As for profitability, while the margins don’t seem great for high volume MEMS devices, they are holding on somewhat. The general consensus of the VC community has been that MEMS has lot of growth potential, but it doesn’t have a good track record of producing profitable firms, as yet.
The lack of DfM emphasis and the absence of a coherent package and test capability is the lack of management insight. As for standards, the creation of the first Standardized Sensor Performance Parameter Definitions is a huge step in the right direction.
Malcolm Penn, chairman and CEO, Future Horizons, sent me the Enable 450 newsletter. The goal of the Enable 450 is: Co-ordination Action to enable an effective European 450 mm Equipment and Materials Network. Here, I am presenting a bit about the E450EDL – European 450mm Equipment demo line.
The aim of the ENIAC E450EDL key enabling technology pilot project is to continue the engagement of the European semiconductor equipment and materials industry in the 450mm wafer size transition that started with the ENIAC JU EEMI450 initiative and proceeded with subsequent projects funded with public money, amongst others NGC450, SOI450, EEM450PR.
The demo line resulting from this project will be such that it will enable first critical process module development by combining imec infrastructure with tools remaining at the site of the manufacturers (distributed pilot line). Multi-site processing will allow partners to participate in the world first 450mm integration studies and will be enabled by the controlled exchange of 450mm wafers between different sites.
The consortium comprises 41 members (from 11 different European countries) with many SMEs and research institutes. The project is organized in five technical work packages and a work package on management and co-ordination.
In the work package on integration and wafer processing first critical modules will be developed and will demonstrate the feasibility of processing on 450mm wafers. The main objective in the work package on lithography is to develop a wafer stage test-rig, which
can be implemented into the pilot line system. In the work package on front end equipment several tools will be developed such as a plasma ion implant module, a plasma dry etch module, a RTP system and a single wafer cleaning system.
Furthermore, in the dedicated work package on metrology 450mm metrology tool types will be developed for amongst others dielectric film thickness and composition measurements, defect inspection, defect review and analysis, optical critical dimensions (CD), overlay (mask and wafer) and 3D metrology.
Finally, from the work package on wafer handling and automation a set of equipment will be provided to support the demo line operations, and facilitate the R&D dedicated to process and metrology modules.
The project will last 36 months beginning on 1st of October 2013. The budget has been given at €204.6 million of which the ENIAC JU will fund €30.8 million. This project is still considering new members so if you are interested please contact ASML.
About 318 engineers and managers completed a blind, anonymous survey on ‘On-Chip Communications Networks (OCCN), also referred to as an “on-chip networks”, defined as the entire interconnect fabric for an SoC. The on-chip communications network report was done by Sonics Inc. A summary of some of the highlights is as follows.
The average estimated time spent on designing, modifying and/or verifying on-chip communications networks was 28 percent (for the respondents that knew their estimate time).
The two biggest challenges for implementing OCCNs were meeting product specifications and balancing frequency, latency and throughput. Second tier challenges were integrating IP elements/sub-systems and getting timing closure.
As for 2013 SoC design expectations, a majority of respondents are targeting a core speed of at least 1 GHz for SoCs design starts within the next 12 months, based on those respondents that knew their target core speeds. Forty percent of respondents expect to have 2-5 power domain partitions for their next SoC design.
A variety of topologies are being considered for respondents’ next on-chip communications networks, including NoCs (half), followed by crossbars, multi-layer bus matrices and peripheral interconnects; respondents that knew their plans here, were seriously considering an average of 1.7 different topologies.
Twenty percent of respondents stated they already had a commercial Network-on-Chip (NoC) implemented or plan to implement one in the next 12 months, while over a quarter plan to evaluate a NoC over the next 12 months. A NoC was defined as a configurable network interconnect that packetizes address/data for multicore SoCs.
For respondents who had an opinion when commercial Networks-on-Chip became an important consideration versus internal development when implementing an SoC, 43 percent said they would consider commercial NoCs at 10 or fewer cores; approximately two-thirds said they would consider commercial NoCs at 20 or fewer cores.
The survey participants’ top three criteria for selecting a Network on Chip were: scalability-adaptability, quality of service and system verification, followed by layout friendly, support for power domain partitioning. Half of respondents saw reduced wiring congestion as the primary reason to use virtual channels, followed by increased throughput and meeting system concurrency with limited bandwidth.