Archive

Posts Tagged ‘low-power design’

Rapidly growing local market bring new opportunities for EDA in India

December 25, 2008 Comments off

Those following the EDA industry are well aware that its been an industry in some trouble right through this year.

If you visited EDA Consortium’s web site, this becomes clear. In Q1-08, the global EDA industry revenue for Q1 2008 declined 1.2 percent to $1,350.7 million compared to $1,366.8 million in Q1 2007.

Later, the EDA industry revenue for Q2 2008 declined 3.7 percent to $1357.4 million compared to $1408.8 million in Q2 2007, as reported by the EDA Consortium.

I am still waiting to see how the Q3 results shape up. My guess is, it would be even lower than Q2, unless there are a few surprises!

The EDA market in India, as per the ISA F&S Report 2005, was US$110m. The latest figures are not yet available, though I would believe the Indian EDA industry is likely to do better than the global industry, unless, there have been some slowdown effects here as well.

I had an interesting discussion with Jaswinder Ahuja, Corporate Vice President and Managing Director, Cadence Design Systems (I) Pvt. Ltd and Chairman, India Semiconductor Association (ISA), on the (dipping?) fortunes of the EDA industry lately.

According to Ahuja, 2008 has been a challenging year. The global financial crisis has impacted several industries and the EDA industry was no exception. Due to the overall downturn in the economy, companies are being more cautious and are delaying purchase decisions, a move that is impacting the overall EDA industry.

Coming to the drivers for EDA in India this year, there are a few key ones! First, the design centres have gained expertise and are now doing cutting-edge designs out of India. They have moved up the value chain from doing block-level design to increasingly owning up end-to-end design and design starts.

Second, several Indian design services companies have made significant acquisitions, showing that their businesses have not just taken root, but also flourished. MindTree Consulting’s acquisition of TES PV and Wipro’s acquisition of Oki’s wireless chip design arm are cases in point, added Ahuja.

He said: “The Indian EDA industry has been growing and we will see more technology adoptions and proliferations in India Design Centers. Also, the rapidly growing local market is unfolding new opportunities.”

EDA outlook 2009
Going forward, market pressures and design complexities are just some of the issues design teams face today. Cadence’s customers, for instance, would like to plan in the context of IP selection, run analysis around power, performance and cost perspectives. Design predictability will be a priority, said Ahuja.

The key focus areas for the EDA industry will be new design for manufacturing technologies as designs move to advanced nodes; verification and verification IPs and multicore processing support for EDA flows as a result of increased integration.

Also, SaaS is likely to gain traction as companies are compelled to consider flexible engagement models to access state-of-the art design environments that help design teams reduce risk and cost, yet increase time-to-productivity.

Are there any opportunities for EDA folks in solar? Ahuja disclosed that in a recent poll by ISA, to the question ‘Solar PV has potential in India’, almost 90 percent of respondents replied Agree or Strongly Agree.

With the worldwide focus on alternative energy systems, India has witnessed several companies announcing investments in PV segment. This is good news for the Indian semiconductor ecosystem.

Cadence has a broad portfolio of technologies that addresses the needs of different players in the ecosystem.

Low power initiatives
Low power has always been a key focus area in semiconductors. According to Ahuja, power efficient design is gaining importance across the design chain and EDA companies will have to look closely at ‘green’ technologies.

Energy efficiency at the system and application level for wired and wireless products will be one of the focus areas. Emerging technologies that allow applications and systems developers to evaluate how their programs use power both individually and in a dynamic, multi-application model of the end system will help expand the role of EDA into system-level design.

The Power Forward Initiative (PFI), an industry alliance comprising of companies across the semiconductor design chain will work towards a more systematic, integrated approach to low-power design.

Outlook 2009
With the new year about to start in less than a week’s time, the impact of the financial crisis will see an increased demand for mid-range product technology as consumers shift spend toward ‘essential’, rather than ‘desirable’ electronic products.

As per Ahuja, globally, semiconductor companies are focusing on their core strengths, consolidating and realigning resources. Across sectors, they will look for systems that marry functionality with cost efficiencies.

“Growth for semiconductor companies will come from energy related and low-power technologies that are able to drive market share shifts,” he noted.

Altera strategy to partner with Indian design services firms

December 7, 2008 Comments off

Turning my attention to the programmable logic market, I took advantage of my recent meeting with Jordan Plofsky, Senior Vice President Market, Altera Corp., during the Altera SOPC conference.

Programmable logic consumption in India has been estimated at between $20-$25 million in 2008, largely driven by strong growth in communications infrastructure and increased spending in the military sector. The Indian programmable logic market is likely to grow at a CAGR of 25 percent over the next three years.

Altera’s India strategy
In this context, it will be interesting to note Altera’s strategy within the Indian semiconductor industry.

Plofsky says that as multinational companies are transferring more design work to their R&D teams in India, local companies are expanding their range of products, and independent design service companies are capturing a bigger piece of the outsourced design pie, Altera forecasts the increased need for high quality application support.

He says: “Unlike other companies who have design services operations in India, which compete with the local independent design services, our strategy is to partner with the local India design services industry. We are expanding our direct and indirect support channels to provide higher quality services to our customers here.”

Altera is also supporting the development of the education sector in India, which is modernizing to turn out well trained engineers to satisfy the appetite of the industry. “We also run industrial workshops and seminars, like the recent SOPC World in Bangalore and New Delhi, to educate the design community on the direction of semiconductor technology,” adds Plofsky.

Altera has also set up Altera Joint Laboratories in leading universities across India to provide a better platform for undergraduates to grasp basics of programmability.

Role in solar?
With investments in solar/PV happening, is there a role for Altera and other FPGA companies? This is a question that I invariably ask everyone in the semiconductor industry!

According to Plofsky, one of the promising applications is smart metering. It is the practice of getting the users and the infrastructure to be power aware and then using different usage patterns to lower energy usage and energy costs by applying smart algorithms.

Addressing low-power design
Power consumption has always been a big concern for designers in all markets and Altera has a number of different solutions.

In the CPLD area, Altera announced its zero power MAX IIZ devices in late 2007. Offering the highest density and I/O count in packages as small as 5x5mm, compared to macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements and lower power while saving board space.

Consuming 75 percent less power than competing FPGAs, the Altera Cyclone III devices are the industry’s first and only 65-nm low-cost FPGA family, and offer digital system designers an unprecedented combination of density, power and cost.

To address the low-power demands of high density customers, the Stratix III and Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design. And in addition these designs can be converted to HardCopy ASIC devices that can reduce power consumption by 50-70 percent.

As for new products in the LTE, TD-SCDMA and NFC spaces, Plofsky says that with the new 40-nm devices, Altera is uniquely positioned to deliver solutions that provide the density, performance and power for these emerging applications. The combination of DSP blocks, memory and transceivers was optimized for these communication applications.

Roadmap beyond
Altera just announced its 40nm devices in May and it is said to be on target to deliver those devices by the end of 2008.

Adds Plofsky: “We have already started development work on smaller process geometries with test chips in fab now, but it is too early to go into any family detail at this time.”

TI’s TPS62601 converter for telecom apps

October 10, 2008 Comments off

This August, Texas Instruments India (TII) announced the industry’s smallest and thinnest 500-mA, step-down DC/DC converter solution, the TPS62601 converter, for space-constrained applications.

According to TI, It gives portable designers the ability to add more features and functions on a handheld device. The high-efficiency power management IC is the first 6-MHz, 500-mA converter to achieve a 13-mm2 solution size with an ultra-thin 0.6-mm total height.

I caught up with Ramprasad Ananthaswamy, Director, Power Management Products, Texas Instruments India, to find out a bit more about this so-called industry’s smallest and thinnest converter solution, and its essential design trends.

So what exactly is the TPS62601 power converter targeted toward? According to Ananthaswamy, the TPS62601, a high-efficiency power management IC is the first 6-MHz, 500-mA converter to achieve a 13mm2 solution size with an ultra-thin 0.6-mm total height.

The TPS62601 converter achieves up to 89-percent power efficiency and only 30-uA typical operating quiescent current, all from a 0.9×1.3mm chip scale package roughly the size of a flake of pepper. The synchronous, switch-mode device’s fixed frequency of 6 MHz allows the use of only one 0.47-uH inductor with a height of 0.6 m and two low-cost ceramic capacitors, without compromising performance and efficiency.

The device supports applications, such as memory modules, GPS modules, Bluetooth and Wi-Fi modules or other wireless micro-modules used in ultra-thin smart phones, digital still cameras, portable disk drives and media players.

Applications areas of this device include: Smart and media phones; Cell phones; Media players; Mobile Internet devices; DSCs; and Other portable communications devices.

This chip will help powering sources such as: WLAN modules; WiFi modules; Bluetooth modules; Memory modules; and Generic micro modules.

Essential design trends
There is a need to understand the essential design trends of the TPS62601 that makes it unique. Ananthaswamy added that the TPS62601 can deliver DC voltage regulation accuracy of +/- 1.5 percent. In addition, its excellent load transient response, wide input voltage range of 2.3V to 5.5V and 1.8V of output allows the device to effectively support single-rail voltage requirements as designers add new features and functions.

The converter also applies energy-saving techniques to help maximize battery run-time. For example, the converter automatically enters a power save mode during light-load operating conditions via an automatic pulse frequency modulation and pulse width modulation switching feature. In shutdown mode, the device’s current consumption is reduced to less than 1 uA. 

Size and high-performance are important. The converter achieves up to 89-percent power efficiency and only 30-uA typical operating quiescent current, from a small chip scale package.

A high switching frequency of 6MHz reduces the size of the external components used around this chip, thereby reducing the total size of the power solution. A low quiescent current of 30 uA also makes it very attractive for portable applications requiring long run times.

Helping portable designers
Let us understand how the TPS62601 will actually enable the portable designers to add more features and functions on to a handheld device. Ananthaswamy says: “Portable system designers continue to desire more features on their devices, which require smaller, efficient DC/DC converters to maintain long battery life and system run-times. As the size of the total power solution is small, more PCB space becomes available for additional features that need to get added on to the cell phone. The TPS62601 gives portable designers access to the smallest, thinnest 500-mA DC/DC solution, which simplifies design and reduces board space and time-to-market.”

The converter also applies energy-saving techniques to help maximize battery run-time. For example, the converter automatically enters a power save mode during light-load operating conditions via an automatic pulse frequency modulation and pulse width modulation switching feature. In shutdown mode, the device’s current consumption is reduced to less than 1uA.

Power management
How well does the TPS62601 tackle power management issues? The biggest issue inside feature rich cell phones today is thermal management. This power converter, consuming only 30uA for its own operation, manages the thermal problem through efficient power conversion. “Better efficiency means less heat,” added Ramaswamy.

Energy-saving techniques
Elaborate on the energy-saving techniques that can help maximize battery run-time, he said: “Globally, switching regulators are efficient means of power conversion. This device is a buck derived switching regulator that efficiently converts the single cell Li-ion battery voltage to the one that is required by the various multimedia rich cell phone chips, like applications processors, GPS modules, digital multimedia broadcast chips, camera engines, WiFi etc.

“It can power all of these chips, while consuming as little as 30uA for its own operation. Depending on the input to output voltage ration, the conversion efficiency can also reach close to 90 percent. Less consumption, better conversion efficiencies, etc., all of these result in longer battery run times.”

Is it then safe to say that the maximizing battery run-time problem has been tackled with the TPS62601? Not exactly!!

According to Ramaswamy, the TPS62601 addresses part of the battery run-time issue. “With this initiative, TI has gone a step ahead in making the battery last longer,” he noted.

Making power converters efficient is only a part of the battery run-time issue. Along with making power converters efficient, one also has to look at how much power is consumed by the various chips that are used in a cell phone, the operating system that runs the cell phone and the overall power saving features that are built into the cell phone system. The speaker volume settings, backlight brightness settings and the duration of the backlight and some of the other user friendly settings have an effect on the battery run times.

Despite EDA challenges, Mentor keeps faith on India

September 21, 2008 Comments off

Great! All of these EDA firms, despite their current financial woes, remain strong and bullish on India! Mentor Graphics is no exception in this case!

It is well documented that the global EDA industry, along with the global semiconductor industry, has not had a smooth ride this year. However, this situation has only made both the industries work harder toward restoring some recovery.

Thanks to Veeresh Shetty, a dear friend, and Marcom Manager-Pacrim South, Mentor Graphics, I had the pleasure of meeting up with Joseph Sawicki, vice president & GM, Design to Silicon Division, Mentor Graphics Corp., during the recently held EDA Tech Forum in Bangalore.

We discussed a range of issues, such as the state of the EDA industry, Mentor’s focus on India, and low-power design challenges. I did not discuss the proposed acquisition of Mentor by Cadence, as I feel it is no point in going over what was never on the cards, at least, for now.

According to Sawicki, Mentor Graphics is very optimistic about semiconductors and electronics, especially in India. “The EDA industry is currently having a pretty challenging environment. The recession in 2002 was the deepest in its history,” he says.

“We (the EDA industry) haven’t had the growth rates we would like. However, we have done better. We have re-invented Mentor,” adds Sawicki. “We have now invested more in back-and-route ICs, which is about 40 percent of our revenue. Our product portfolio is the youngest within the company.” He adds that the recession has been more in semiconductors. However, take out memory, and the scenario changes.

The drive of the semiconductor industry toward smaller and smaller features sizes requires more sophisticated correction methods to guarantee the final tolerances for the etched features in both wafer manufacturing and mask making.

Flat growth likely for EDA
Commenting on EDA industry’s growth, Sawicki, adds that growth will be flat in 2008. Interestingly, the growth rate for EDA was 10 percent during the last two years. He notes: “EDA always does best when it delivers new technology. There are two reasons. One, on the manufacturing side of things. The extra results will be completely delivered by the software.”

The other reason is that the aspects of manufacturing power and manageability will assume great importance. “Finally, the ESL space also provides the potential for growth. It also brings out a whole new design capability,” he notes.

Given the global semiconductor scenario, Mentor is also looking at other markets outside semiconductors, especially automotive. Sawicki adds that this quarter, 20 percent of Mentor’s business has been from the automotive segment.

There have been several global initiatives aimed at consolidation in the recent past. Sawicki says: “Consolidation should not be looked at as a goal. We also do acquisitions in the technology space. It augments a strong position.”

So what are some of the other challenges facing the industry? Sawicki lists those as the economics of the industry itself, especially the design and verification costs.

On low power design, Sawicki agrees that there has been a transition of electronics from the US to Asia. “You have got to handle far lower power downward. We can reduce leakage current by 20-30 percent. Looking forward, how do you tie in ESL with physical design? When doing ESL, you can do architectural exploration. I will have my ESL to drive the place-and-route tool. I can get fast execution as well as low leakage power.”

He advises that India has the ability to go beyond the innovation that has been happening.

Mentor in India
Mentor Graphics has three sites in India. It has R&D centers in Hyderabad and Noida, near New Delhi, and a sales and support office in Bangalore. The Hyderabad R&D center handles system design, while the Noida R&D center takes care of the front-end side, such as functional verification products.

Raghu Panicker, sales director, India, Mentor Graphics, says that the company has been very bullish on India. “We do not see any lull anywhere. Lot of design starts are happening here, in India,” he adds.

I will continue my conversation with Joseph Sawicki in the next blog!

Synopsys’ Dr Chi-Foon Chan on India, low power design and solar

September 11, 2008 1 comment

There have been reports about the troubles within the EDA industry in recent times, especially those related with quarter sales. Interestingly, Synopsys has been the one sailing along fine! If that’s not enough, it made its intention known of playing a role on the solar/PV segment, an area where lot of investments have been happening!

Given this scenario, I was fortuitous enough, rather, extremely lucky to be able to get into a conversation with Dr. Chi-Foon Chan, President and Chief Operating Officer, Synopsys Inc., during his recent visit to India.

On the state of the global semiconductor industry, he said, it was somewhere now in the low 10s [well below 10 percent]. The EDA industry is currently tracking below that level. However, Synopsys has been growing at around 10 percent. He said, “The technology challenges today are very high.”

Synopsys has a substantial number of R&D population based out of India. Giving his assessment of the Indian semiconductor industry, Dr. Chan added: “Our main interest in India is largely talent and the academia. India can very well get more into the product development side. Even the outsourcing of designs have increased. Our capabilities, of the Indian team, have also increased.”

As with any good semiconductor ecosystem, the Indian industry also needs a proactive industry association, a role played to near perfection by the ISA (India Semiconductor Association). Acknowledging the ISA’s role, Dr. Chan said, “The ISA has also formed a very cohesive team.”

There is little doubt about India’s growing importance in technology strengths and managerial leadership. Dr. Chan added: “We are more on the high-end side and also track what others design. In India, the profiles of designs are definitely high-end in nature. This is largely due to the presence of a large number of MNCs. A very high percentage of designs are in the 45nm and 65nm process technology nodes.”

There is another significant indicator of India’s growing importance, and that is the huge rise in the attendance of the SNUG. In 2000, this event attracted 180 people. However, in 2008, the SNUG attracted over 2,000 people.

Moving India to next level
Given the very high level of commitment on Synopsys’ part toward India, there was a need to find out from Dr. Chan what exactly India needs to do to move to the next level in the value chain in the semiconductor ecosystem.

He advised: “India can do two to three things. One, for the system to grow, you need the government, academia and industry to grow together. India has all of the ingredients required to drive products.”

Comparing India with China, he highlighted the fact that while in China, the local consumption was higher than local supply, that was not the case with India!

“Therefore, looking at merely the local market is not the only thing. Products developed here can also be targeted at the Middle East and Southeast Asia.” He was quite forthright in his analysis, adding: “Industries start when you find markets. The skill sets are already present here. There can well be multiple startups.”

Dr. Chan also touched upon the fab vs. fabless issue, noting that there could well be more of fabless companies in India. “Building a fab requires lot of capital. Also, consolidation will continue to happen.”

What role does Dr. Chan see Synopsys playing in the Indian context? He said: “Synopsys will continue to be a catalyst for the industry. A healthy design industry in India continues to help us. We also work well with the Indian universities. Having more people from the universities will always help. We also invest a lot in application support. The application team also trains others. I now look forward to seeing more fabless companies here and India to become even more global.”

On low power design
India is also a centre of expertise in low power design, given that low power is hugely important in today’s electronics ecosystem. Dr. Chan commented that low power has always been the number one design issue. It cannot be taken care of at one single stage.

He added: “A slightly new concept that has emerged is low-power verification. There are so many schemes for attacking low power, such as multiple voltage islands. We (Synopsys) are spending a lot of effort in low power.

“As a designer, you require detailed analysis. Low-power verification is now coming up. Another area is testing. As an example, if so much power is required, how do you have the power cut from the tool you are using to test? From a Synopsys point of view, we are involved in several points, such as front-end synthesis, testing, sign-off, verification, etc. We are trying to put in a whole lot of methodologies.”

Synopsys in solar
EDA may be able to help by lowering power requirements and leakage on better products. Especially, the Synopsys’ TCAD product can be used to create more efficient and effective solar cells. Now, this is not a new development anymore. Synopsys, along with Magma, have already made known their intentions about setting foot in the solar/PV space.

On the TCAD, Dr. Chan said: “We have a very strong position in the TCAD, commercially. Now, it is one of our most critical elements in high-performance. Our TCAD is among the strongest in the EDA industry.

“In solar, it does not have to be a complicated place-and-route, etc. From an entire solar industry point of view, we have now used some effort from TCAD into this space. Heat transfer issues, etc., are more in the EDA space.”

I will continue my conversation with Synopsys on its solar initiative sometime later. Keep watching this space, folks

Xilinx on microprocessor trends, solar/PV

August 13, 2008 Comments off

This semicon blog will basically examine the key trends in microprocessors, as well as whether companies such as Xilinx — a key player in FPGAs — has any kind of role to play in the solar/PV domain.

For the record, this is the concluding part of the discussion with Vincent Ratford, Senior Vice President, Solutions Development Group, Xilinx.

First, on to solar/PV! We have been reading and hearing a lot about the rapid advances being made in solar/PV. With so much investments in solar/PV happening globally, is there a role for Xilinx to play in this segment?

Ratford said: “Perhaps! Our devices are great for prototyping new ideas and often find their way into new markets. In base stations, our devices are used to reduce the power up to 50 percent. In signal processing applications, we have a decided performance/power advantage vs. discrete signal processors. Many of these ‘Green’ applications require some form of signal and embedded processing.” Interesting, and this point needs some further examination!

Another area of main concern within the global semiconductor industry is low-power design. According to Ratford, there are a variety of ways to save system power.

He added: “We are designing features in our new products that will reduce active and standby power. We also have power-estimation and optimization tools. I would say, there is a lot more to be done in this area at all levels, software, IP and silicon.”

Ratford was however, tight-lipped about Xilinx’s product roadmap beyond the Virtex V. Obviously, we need to remain very tuned toward this!

Key microprocessor trends
Now this is another interesting area. A few weeks ago, I had received a great article from Texas Instruments, which mentioned about five key microprocessor trends today.

Microprocessors have always been among the key areas of interest for semiconductor design and development. On being quizzed on what could be the five major trends for microprocessors, Xilinx’s Ratford said: “For our embedded customers it is:

* Rising adoption of Linux.
* Increasing use of multi-core and some multi-processing.
* Accelerating trend to increase the connectivity, bandwidth and reduce the latency between the processor and the FPGA.
* Improve the OOBE (Out of the Box Experience) for non-FPGA developers.
* Reduce power.

Before signing off, my thoughts also veered toward LTE and TD-SCDMA, one 4G and the other, a 3G technology. Both these technologies have been very much in the news lately, especially, TD-SCDMA, which is currently in use at the Beijing Olympics.

As expected, Xilinx has also forayed into both LTE and TD-SCDMA spaces!

Ratford said: “Yes, we have complete reference designs for LTE and TD-SCDMA and have secured most of the prototype sockets for these air interface standards with Virtex-5. We have a very strong IP portfolio for the radio shelf and baseband and our Sytem Generator and AccelDSP tools are used extensively.”

Tackling low-power design issues — Synopsys

July 1, 2008 Comments off

Managing power efficiently is not a choice, but an imperative. Semiconductor content is increasing everywhere, and in fact, consumers and globalization are driving the semiconductor content in electronic systems.

A glance at the ecosystem pyramid reveals that the global electronics industry stands at US$3,200 billion, semiconductors at US$274 billion, equipment and materials at US$86 billion, and EDA at US$4.4 billion. EDA is at the heart of the electronics industry.

Subhash Bal, country director, Synopsys (India) EDA Software Pvt. Ltd, says that for low power imperatives, it is important to look at systemic factors. Energy usage and carbon emissions, especially, have been growing alarmingly, and will continue to do so for quite some time. This is largely due to uncontrolled consumption of devices and other electronic equipment. “We need to support energy usage without carbon emissions. In that respect, solar is a good solution,” he adds.

Computing is energy intensive by nature. Consider these stats — approximately 1 billion of the world’s PCs are switched on for nine hours per day, requiring 95,000MW. And of the US$250 billion spent globally each year powering computers, about 85 percent of that energy is wasted, while the computer stands idle.

Today, more devices and gadgets are being introduced, with more features and at lower prices. All of these devices demand a huge amount of battery power. Speed increases at the expense of energy consumption. Leakage has also become a major issue. There is therefore a growing need to solve power-related problems.

The Synopsys Sentaurus
Synopsys’ Sentaurus optimizes a device’s power. It also addresses photovoltaics. The Sentaurus process is an advanced 1D, 2D, and 3D process simulator for developing and optimizing silicon and compound semiconductor process technologies.

Created by combining features from Synopsys and former ISE TCAD products, together with a wide range of new features and capabilities, Sentaurus is a new-generation process simulator for addressing the challenges found in current and future process technologies. “The Sentaurus takes care of the processing part. It does modeling, 2D/3D simulation, etc. It can be applied to both semiconductors and solar,” says Bal.

Eclypse low-power solution
Synopsys’ goal is to deliver the most comprehensive solution, enabling designers to build the most advanced, low power chips and systems in the world. In the hope of achieving this, it has introduced the Eclypse low-power solution. Sharat D Kaul, sales and marketing manager, Synopsys India, highlights the fact that the Eclypse looks at the design side specifically.

The silicon-level concerns include factors such as more functionality, more computing power, limited power budget, design complexity, verification complexity, testing, reliability and schedule. System-level concerns include factors such as battery life, system cooling, reliability, packaging cost, operating cost, air conditioning cost, carbon footprint and green initiatives. Most design teams are both overwhelmed and under prepared.

The Eclypse low power solution is aimed at addressing such needs. It provides an alignment of technology, IP, methodology, services and industry standards — geared to meet the challenges of advanced low power designs.

Eclypse supports the industry-standard Unified Power Format (UPF) language, used to capture low power design requirements. It offers low power education programs, end-to-end UPF support, multi-voltage verification with assertions, automated clock tree synthesis, and automated power switch optimization.

%d bloggers like this: