SEMICON Europa was recently held in Dresden, Germany on Oct. 8-10, 2013. I am extremely grateful to Malcolm Penn, chairman and CEO, Future Horizons for sharing this information with me.
SEMICON Europa included a supplier exhibition where quite a few 450mm wafers were on display. One highlight was a working 450mm FOUP load/unload mechanism, albeit from a Japanese manufacturer. These exhibits did illustrate though that 450mm is for real and no longer a paper exercise. There was also a day-long conference dedicated to 450mm in the largest room. This was crowded throughout the time and a large number of papers were given.
Paul Farrar of G450C began with a presentation about Supply Chain Collaboration for 450mm. His key message was there are 25 different tools delivered to G450C of which 15 are installed in the NFN cleanroom. This number will grow to 42 onsite and 19 offsite by Q1 2015.
He stated that Nikon aims to have a working 193i litho machine in 2H 2014 and install one in Albany in 1H 2015. Farrar also reported a great improvement in wafer quality which now exceed the expected M76 specification, and prime wafers to the M1 spec should be available in Q3 2014. There has also been good progress on wafer reclaim and it is hoped some wafers can be reused up to 10 times, although at least three is the target.
Metrology seems to be one of the most advanced areas with eight different machines already operational. The number of 450mm wafers in their inventory now stands at over 10,000 with these moving between the partners more rapidly. It was immediately noticeable from Farrar’s speech that G450C is now recognising the major contribution Europe is making to 450mm and is looking for more collaborations.
Facilities part of F450C
Peter Csatary of M&W then dealt with the facilities part of G450C, known as F450C. This group consists of:
• M&W (co-ordination)
• Mega Fluid Systems
• Haws Corp.
• Air Liquide
• Ceres Technlogies
• CS Clean Systems
F450C is seen as streamlining communications with the semiconductor companies and their process tool suppliers. The group will focus on four key areas, namely Environmental Footprint, Facility Interface Requirements, Cost and Duration, and Safety and Sustainability.
One interesting point raised was that 450mm equipment is inherently more massive and one suggestion has been that ceiling mounted cranes will be required to install and remove equipment. This of course means that fab roofs would need to be stronger than previously. This topic was discussed at the latest F450C meeting subsequent to this conference.
Another new concept is that of a few standardised 3D templates and adapter plates to allow fab services to be pre-installed before the equipment is placed. An interesting point made elsewhere by M&W is that the current preference is to place a fab where there are already other fabs in existence so that the infrastructure to transport products, materials and services is already in place, as are basic utilities such as power, natural gas and water supply.
However, the scale of the expected utility demand at 450 mm ups the stakes as for example a large 300 mm facility uses about 4 million gallons of water per day, whereas a 450 mm fab will use almost double that, putting immense strain on a location’s infrastructure should there be other fabs in the region. This could affect future site selections.
An outcome of this phenomenon is that the reduction, reclaim and re-use of materials will no longer be driven only by the desire to be a good corporate citizen, but will also be driven by cost control and to ensure availability of required resources such as power, water, specialty gases and chemicals.
The government of India recently approved the setting up of two semiconductor wafer fabrication facilities in the country. It is expected to provide a major boost to the Indian electronics system design and manufacturing (ESDM) ecosystem. A look at the two proposals:
Jaiprakash Associates, along with IBM (USA) and Tower Jazz (Israel). The outlay of the proposed fab is about Rs. 26,300 crore for establishing the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I, 28nm node in phase II with the option of establishing a 22nm node in phase III. The proposed location is Greater Noida.
Hindustan Semiconductor Manufacturing Corp. (HSMC) along with ST Microelectronics (France/Italy) and Silterra (Malaysia). The outlay of the proposed fab is about Rs. 25,250 crore for the fab facility of 40,000 wafer starts per month of 300mm size, using advanced CMOS technology. Technology nodes proposed are 90nm, 65nm and 45nm nodes in phase I and 45nm, 28nm and 22nm nodes in phase II. The proposed location is Prantij, near Gandhinagar, Gujarat.
Now, this is excellent news for everyone interested in the Indian semiconductor industry.
One look at the numbers above tell me – NONE OF THESE are going to be 450mm fabs! Indeed, both will be 300mm fabs! After waiting for such a long time to even get passed by the Union Cabinet, are these 300mm fabs going to be enough for India? Is the technology choice even right for the upcoming wafer fabs in India? Let’s examine!
As you can probably see, both the projects have placed 22nm right at the very last phase! That’s very interesting!
Intel just showcased its Xeon processor E5-2600 v2 product family a few days back. I distinctly remember Intel’s Narendra Bhandari showing off the 22nm wafer sometime last week during a product launch!
For discussion’s sake, let’s say, a fab in India comes up by say, early 2015. Let’s assume that Phase 1 takes a full year. Which means, Phase 2, where 22nm node would be used, shall only be touched in 2016 or even beyond! Isn’t it? Where will the rest of the global industry be by then?
You are probably aware of the Global 450 Consortium or G450C, which has Intel, IBM, Samsung, GlobalFoundries and TSMC among its members. What is the consortium currently doing? It is a 450mm wafer and equipment development program, which is leveraging on the industry and government investments to demonstrate 450mm process capabilities at the CNSE’s Albany Nanotech Complex. CNSE, also a consortium member, is the SUNY’s College of Nanoscale Science and Engineering!
So, what does all of this tell me?
One, these upcoming fabs in India will probably produce low- to mid-range chips, and some high-end ones at a later stage. Well, two, this does raise a question or two about India’s competitive advantage in the wafer fab space! Three, there is lot of material on 450mm fabs, and some of that is available right here, on this blog! Have the Indian semiconductor industry folks paid enough attention to all that? I really have no idea!
Four, only the newer 300mm fabs built with higher ceilings and stronger floors will be able to be upgraded to 450mm, as presented by The Information Network’s Dr. Robert Castellano at the Semicon West 2013. Five, what are the likely alternative markets for 200mm and 300mm fabs? These are said to be MEMs and TSV, LEDs and solar PV. Alright, stop!
Perhaps, these product lines will be good for India and serve well, for now, but not for long!
San Jose, USA-based Atrenta’s SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed. I recently met up with Dr. Ajoy Bose, chairman, president and CEO, Atrenta, to find out more.
I started by asking how Atrenta provides early design analysis for logic designers? He said: “The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate ‘predictions’, without the time and cost required to actually send a design through detailed implementation.”
There’s a saying: electronic system level (ESL) is where the future of EDA lies. Why? Its because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.
Now, how will this help EDA to move up the embedded software space? According to Dr. Bose, the ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.
How are SpyGlass and GenSys platforms helping the industry? What problems are those solving? Dr. Ajoy Bose said: “SpyGlass is Atrenta’s platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation.SpyGlass is also used to select and qualify semiconductor IP – a major challenge for all SoC design teams.
“GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. As a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.”
How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs? He added that it’s the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.
On another note, I asked him why Apple’s choice of chips a factor in influencing the global chip industry? The primary reason is their volume and buying power. Apple is something of a “King Maker” when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.
Finally, the global semiconductor industry! How is the global semicon industry doing in H1-2013? As per Dr. Bose: “We see strong growth. Our customers are undertaking many new designs at advanced process technology nodes. We think that this speaks well for future growth of the industry. At a macro level, the consumer sector will drive a lot of the growth ahead. For EDA, the higher levels of abstraction is where the growth will be.”
POET Technologies Inc., based in Storrs Mansfield, Connecticut, USA, and formerly, OPEL Technologies Inc., is the developer of an integrated circuit platform that will power the next wave of innovation in integrated circuits, by combining electronics and optics onto a single chip for massive improvements in size, power, speed and cost.
POET’s current IP portfolio includes more than 34 patents and seven pending. POET’s core principles have been in development by director and chief scientist, Dr. Geoff Taylor, and his team at the University of Connecticut for the past 18 years, and are now nearing readiness for commercialization opportunities. It recently managed to successfully integrate optics and electronics onto one monolithic chip.
Elaborating, Dr. Geoff Taylor, said: “POET stands for Planar Opto Electronic Technology. The POET platform is a patented semiconductor fabrication process, which provides integrated circuit devices containing both electronic and optical elements on a single chip. This has significant advantages over today’s solutions in terms of density, reliability and power, at a lower cost.
“POET removes the need for retooling, while providing lower costs, power savings and increased reliability. For example, an optoelectronic device using POET technology can achieve estimated cost savings back to the manufacturer of 80 percent compared to the hybrid silicon devices that are widely used today.
“The POET platform is a flexible one that can be applied to virtually any market, including memory, digital/mobile, sensor/laser and electro-optical, among many others. The platform uses two compounds – gallium and arsenide – that will allow semiconductor manufacturers to make microchips that are faster and more energy efficient than current silicon devices, and less expensive to produce.
“The core POET research and development team has spent more than 20 years on components of the platform, including 32 patents (and six patents pending).”
Moore’s Law to end next decade?
Is silicon dead and how much more there is to Moore’s Law?
According to Dr. Taylor, POET Technologies’ view is that Moore’s Law could come to an end within the next decade, particularly as semiconductor companies have recently highlighted difficulties in transitioning to the next generation of chipsets, or can only see two to three generations ahead.
Transistor density and its impact on product cost has been the traditional guideline for advancing computer technology because density has been accomplished by device shrinkage translating to performance improvement. Moore’s Law begins to fail when performance improvement translates less and less to device shrinkage – and this is occurring now at an increasing rate.
He added: “For POET Technologies, however, the question to answer is not when Moore’s Law will end – but what next. Rather than focus on how many more years we can expect Moore’s Law to last – or pinpoint a specific stumbling block to achieving the next generation of chipsets, POET looks at the opportunities for new developments and solutions to continue advancements in computing.
“So, for POET Technologies, we’re focusing less on existing integrated circuit materials and processes and more towards a different track with significant future runway. Our platform is a patented semiconductor fabrication process, which concentrates on delivering increases in performance at lower cost – and meets ongoing consumer appetites for faster, smaller and more power efficient computing.”
The Global 450mm Consortium (G450C) has been driving the effective industry 450mm development. It is co-ordinating test wafer capability supporting development and demonstrating unit process tool performance. The focus is now on improving tools with suppliers to be ready for customer operations.
Giving an update during the recently held Semicon West 2013 at San Francisco, USA, Paul Ferrer, GM, G450C, said that if one looks at the G450C lithography tool roadmap, by 1H-2014, the 300mm coupon, 450mm directed self-assembly and 450mm imprint will be completed. From 2H-2014 to 1H-2015, there will be 193i patterning service at Nikon’s site. Nikon 193i move-in will take place from 1H-2015 to 2H-2016.
Suppliers are developing the 450mm tool set with 10 tools per quarter being delivered to G450C, the global consortium for 450mm fabs. Significant progress has been made in wafer quality and wafer reclaim is almost ready. Automation and carriers are working, and suppliers are co-operating on the key initiatives. Global collaboration is said to be picking up steam.
In the NFX cleanroom, the 450mm OHT is ready for inter-fab transfer. There are nine tools in-fab — two metro, three process, and four stocker, respectively. There will be seven ODD 3Q2013, and 10 tools ODD 4Q2013, respectively.
As for 450mm notchless wafer activities, the key technical results include the backside fiducial marks that have achieved the desired accuracy (3σ = 0.5μm) using existing camera technology. There are design rules of fiducial marks, such as multiple locations (≤ 4) for robustness and speed, different patterns at multiple locations, and off crystal plane, fewer dots and shallower dots to minimize the Si crystal damage.
As for program highlights, there are collected designs from G450C member companies, tool suppliers, and optical detection suppliers. Also, there has been delivery of 300mm test wafers with fiducial marks. G450C has co-ordinated test wafer plans with suppliers. Further, for 450mm silicon wafer readiness, notchless wafers are technically achievable now.
The G450C members include CNSE/Research Foundation, GLOBALFOUNDRIES, Intel, IBM, Samsung and TSMC.
Its a pleasure to talk to Dr. Walden (Wally) C. Rhines, chairman and CEO, Mentor Graphics Corp. On his way to DAC 2013, where he will be giving a ten-minute “Visionary Talk”, he found time to speak with me. First, I asked him given that the global semiconductor industry is entering the sub-20nm era, will it continue to be ‘business as usual’ or ‘it’s going to be different this time’?
Dr. Rhines said: “Every generation has some differences, even though it usually seems like we’ve seen all this before. The primary change that comes with “sub-20nm” is the change in transistor structure to FinFET. This will give designers a boost toward achieving lower power. However, compared to 28nm, there will be a wafer cost penalty to pay for the additional process complexity that also includes two additional levels of resolution enhancement.”
Impact of new transistor structures
How will the new transistor structures impact on design and manufacturing?
According to him, the relatively easy impact on design is related to the simulation of a new device structure; models have already been developed and characterized but will be continuously updated until the processes are stable. More complex are the requirements for place and route and verification; support for “fin grids” and new routing and placement rules has already been implemented by the leading place and route suppliers.
He added: “Most complex is test; FinFET will require transistor-level (or “cell-aware”) design for test to detect failures, rather than just the traditional gate-level stuck-at fault models. Initial results suggest that failure to move to cell-aware ATPG will result in 500 to 1000 DPM parts being shipped to customers.
“Fortunately, “cell-aware” ATPG design tools have been available for about a year and are easily implemented with no additional EDA cost. Finally, there will be manufacturing challenges but, like all manufacturing challenges, they will be attacked, analyzed and resolved as we ramp up more volume.”
Introducing 450mm wafer handling and new lithography
Is it possible to introduce 450mm wafer handling and new lithography successfully at this point in time?
“Yes, of course,” Dr. Rhines said. “However, there are a limited number of companies that have the volume of demand to justify the investment. The wafer diameter transition decision is always a difficult one for the semiconductor manufacturing equipment companies because it is so costly and it requires a minimum volume of machines for a payback. In this case, it will happen. The base of semiconductor manufacturing equipment companies is becoming very concentrated and most of the large ones need the 450mm capability.”
What will be the impact of transistor variability and other physics issues?
As per Dr. Rhines, the impact should be significant. FinFET, for example requires controlling physical characteristics of multiple fins within a narrow range of variability. As geometries shrink, small variations become big percentages. New design challenges are always interesting for engineers but the problems will be overcome relatively quickly.
Agnisys Inc. was established in 2007 in Massachusetts, USA, with a mission to deliver innovative automation to the semiconductor industry. The company offers affordable VLSI design and verification tools for SoCs, FPGAs and IPs that makes the design verification process extremely efficient.
Agnisys’ IDesignSpec is an award winning engineering tool that allows an IP, chip or system designer to create the register map specification once and automatically generate all possible views from it. Various outputs are possible, such as UVM, OVM, RALF, SystemRDL, IP-XACT etc. User defined outputs can be created using Tcl or XSLT scripts. IDesignSpec’s patented technology improves engineer’s productivity and design quality.
The IDesignSpec automates the creation of registers and sequences guaranteeing higher quality and consistent results across hardware and software teams. As your ASIC or FPGA design specification changes, IDesignSpec automatically adjusts your design and verification code, keeping the critical integration milestones of your design engineering projects synchronized.
Register verification and sequences consume up to 40 percent of project time or more when errors are the source of re-spins of SoC silicon or an increase in the number of FPGA builds. IDesignSpec family of products is available in various flavors such as IDSWord, IDSExcel, IDSOO and IDSBatch.
IDesignSpec more than a tool for creating register models!
Anupam Bakshi, founder, CEO and chairman, Agnisys, said: “IDesignSpec is more than a tool for creating register models. It is now a complete Executable Design Specification tool. The underlying theme is always to capture the specification in an executable form and generate as much code in the output as possible.”
The latest additions in the IDesignSpec are Constraints, Coverage, Interrupts, Sequences, Assertions, Multiple Bus Domains, Special Registers and Parameterization of outputs.
“IDesignSpec offers a simple and intuitive way to specify constraints. These constraints, specified by the user, are used to capture the design intent. This design intent is transformed into code for design, verification and software. Functional Coverage models can be automatically generated from the spec so that once again the intent is captured and converted into appropriate coverage models,” added Bakshi.
Using an add-on function of capturing Sequences, the user is now able to capture various programming sequences in the spec, which are translated into C++ and UVM sequences, respectively. Further, the interrupt registers can now be identified by the user and appropriate RTL can be generated from the spec. Both edge sensitive and level interrupts can be handled and interrupts from various blocks can be stacked.
Assertions can be automatically generated from the high level constraint specification. These assertions can be created with the RTL or in the external files such that they can be optionally bound to the RTL. Unit level assertions are good for SoC level verification and debug, and help the user in identifying issues deep down in the simulation hierarchy.
The user can now identify one or more bus domains associated with Registers and Blocks, and generate appropriate code from it. Special Registers such as shadow registers and register aliasing is also automatically generated.
Finally all of the outputs such as RTL, UVM, etc., can be parameterized now, so that a single master specification can be used to create outputs that can be parameterized at the elaboration time.
How is IDesignSpec working as chip-level assertion-based verification?
Bakshi said: “It really isn’t an assertion tool! The only assertion that we automatically generate is from the constraints that the user specifies. The user does not need to specify the assertions. We transform the constraints into assertions.”
MEMS still has a long way to go to meet the challenges of commercialization! Critical success factors include efficient process transfer from breadboard to production. There is a need to pay attention to customers’ needs. More resources need to be adopted from the semiconductor industry, said Roger Grace, president, Roger Grace Associates.
There is a need to create significant awareness as to the unique solution benefits of MEMS based systems and establish defensible product differentiation. Firms need to better understand customer/market needs.
Emerging opportunities include single MEMS based system solutions, especially in analytical instruments, double magnetic MEMS, triple point-of-care bio, energy harvesting/storage, etc. There are barriers to commercialization of MEMS. Until recently, it is plagued by lack of high-volume apps. There is lack of well-defined direction from roadmaps, industry standards and associations. Packaging and testing costs are typically at 70 percent of total value. There is also a lack of focus on customer needs and lack of capital formation opportunities, risk averse investors.
Besides, successive bubble busts, i.e., biomems, optical telecom, have seen wary investors. There are very fragmented markets, many small companies and few large players. Also, there are limited ‘success stories’ of MEMS/MST companies, eg., Invensense. There are new market opportunities for large volume apps, eg. in automotive, CE, etc.
Downturn hit research hard! R&D remains a novelty for most firms. Now, there is an increase in university and R&D labs for MEMS development. There is still plenty of R&D available from DARPA, SBIR and STTRs. Now, we are seeing a healthy amount of activity in new devices and systems research.
As for DfM (design for manufacturing), Invensense’s ‘shuttle’ process may finally become a usable standard. New approaches are also changing the paradigm of cost structure. Examples are Invensense gyros, Freescale chip-stacking accelerometers, ST, etc.
While there seems to be strong MEMS infrastructure, there is some fraying at the ends. The industry needs to remain competitive and lean. As for profitability, while the margins don’t seem great for high volume MEMS devices, they are holding on somewhat. The general consensus of the VC community has been that MEMS has lot of growth potential, but it doesn’t have a good track record of producing profitable firms, as yet.
The lack of DfM emphasis and the absence of a coherent package and test capability is the lack of management insight. As for standards, the creation of the first Standardized Sensor Performance Parameter Definitions is a huge step in the right direction.
Xilinx Inc. has announced solutions for significant and growing gaps in ASIC and ASSP offerings targeting next-generation smarter networks and data centers. It has been acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services that leverage Xilinx’s All Programmable FPGAs, SoCs, and 3D ICs.
To find out more about how are Xilinx’s solutions targeting growing ASIC and ASSP gaps for next-gen smarter networks and data centers, I spoke with Neeraj Varma, director, Sales-India, Xilinx. He said: “Over the past several years, Xilinx has been making a transition from the leading FPGA vendor to a provider of All Programmable Solutions for Smarter Systems. With its All Programmable 7 Series FPGAS, All Programmable SoCs and the VivadoTM Design Suite, Xilinx now offers a comprehensive set of solutions that provide end-to-end system implementation.
“Through strategic acquisitions, investments in silicon products and IP development, Xilinx has started to replace entire ASSPs and ASICs in the communications market by offering a complete IP cores portfolio which allows customers to design Smarter Systems for networking, communications and data center applications.
“Xilinx is calling this set of IP cores, SmartCORE IP, because they are the critical application-specific building blocks needed to develop smarter networking and communications systems. We are responding to market need and that need has accelerated recently as the viability of ASICs and more recently ASSPs have been severely challenged. Xilinx is a generation ahead in SoC and tools and its leadership at 28nm borne out with revenue ramp.”
Developing SmartCORE IP portfolio
What is meant by Xilinx acquiring and developing a SmartCORE IP portfolio and a critical mass of application specialists and services?
According to him, 28nm design process devices require a new and a different set of tools to exploit all the capabilities. That was one of the reasons for Xilinx to invest heavily in resources and time to come up with the Vivado Design Suite, to be able to support the large designs and get them into production with minimal effort and ease.
Vivado supports the growing use of IP blocks to reduce the complexity of the designs which are very critical in the implementation of complex networking and communications systems. This is one of the main reasons Xilinx spent years to develop strategic partnerships and making acquisitions such as Omiino (OTN IP solutions), Modelware (Traffic Management and Packet processing IP solutions), Sarance (Ethernet and Interlaken IP solutions) and Modesat (Microwave and Eband backhaul IP solutions) to offer a comprehensive set of IP cores to design Smarter Systems for networking, communications and data centre applications.
How are the solutions going to address the challenges with ASICs and ASSPs?
He said that ASICs and ASSPs targeting the communications, networking, and data center equipment markets have been disappearing at a surprisingly rapid pace due to many factors, including escalating IC-design costs and the need for much greater levels of intelligence and adaptability—all driven by wide variance in application and device requirements.
Additionally, the equipment markets no longer accept “me too” equipment design, which means that ASSP-based equipment design has almost vanished due to limited flexibility. These growing gaps are pervasive across all markets.These challenges, coupled with the rapidly increasing design costs and lengthy design cycles for both ASICs and ASSPs have created significant solution gaps for equipment design teams.
ASSPs and ASICs are either too late to market to meet OEM or operator requirements, are significantly overdesigned to satisfy the superset requirements of many diverse customers, are not a good fit for specific target applications, and/or provide limited ability for customers to differentiate their end products. Equipment vendors face many or all of these gaps when attempting to use the solutions offered by ASIC and ASSP vendors.
Last week (March 11, 2013), Cadence Design Systems Inc. entered into a definitive agreement to acquire Tensilica Inc., a leader in dataplane processing IP, for approximately $380 million in cash.
With this acquisition, Tensilica dataplane processing units (DPUs) combined with Cadence design IP will deliver more optimized IP solutions for mobile wireless, network infrastructure, auto infotainment and home applications.
The Tensilica IP also complements industry-standard processor architectures, providing application-optimized subsystems to increase differentiation and get to market faster. Finally, over 200 licensees, including system OEMs and seven of the top 10 semiconductor companies, have shipped over 2 billion Tensilica IP cores.
Talking about the rationale behind Cadence acquiring Tensilica, Pankaj Mayor, VP and head of Marketing, Cadence, said: “Tensilica fits and furthers our IP strategy – the combination of Tensilica’s DPU and Cadence IP portfolio will broaden our IP portfolio. Tensilica also brings significant engineering and management talent. The combination will allow us to deliver to our customers configurable, differentiated, and application-optimized subsystems that improve time to market.”
It is expected that the Cadence acquisition will also see the Tensilica dataplane IP to complement Cadence and Cosmic Circuits’ IP. Cadence had acquired Cosmic Circuits in February 2013.
What are the possible advantages of DPUs over DSPs? Does it mean a possible end of the road for DSPs?
As per Mayor, DSPs are special purpose processors targeted to address digital signaling. Tensilica’s DPUs are programmable and customizable for a specific function, providing optimal data throughput and processing speed; in other words, the DPUs from Tensilica provide a unique combination of customized processing, plus DSP. Tensilica’s DPUs can outperform traditional DSPs in power and performance.
So, what will happens to the MegaChips design center agreement with Tensilica? Does it still carry on? According to Mayor, right now, Cadence and Tensilica are operating as two independent companies and therefire, Cadence cannot comment until the closing of the acquisition, which is in 30-60 days.