Home > EDA, FPGAs, GateRocket > New developments in FPGAs, EDA

New developments in FPGAs, EDA

April 24, 2007

Couple of announcements today caught one’s eye! The first was GateRocket Inc.’s announcment of the availability of its Device Native verification product that gives the designers of FPGAs (field programmable gate arrays) the power to validate designs with one to two orders of magnitude faster simulation, and realize actual device behavior early in the design process.

Its RocketDrive is a hardware and software solution that adds significant value to existing design verification environments without a change in design flow or verification methodology.

GateRocket’s software allows the verification engineer to place any portions of the FPGA design into the RocketDrive and link it to his or her existing simulation platform. This allows the FPGA to be used natively to speed verification by replacing FPGA models with actual hardware, investigate hardware bugs and test alternatives, and run application level software against a Device Native representation of the design.

The other announcement was from Synopsys, who announced the availability of the latest release of its Design Compiler synthesis solution, Design Compiler 2007.

The new release extends topographical technology to accelerate design closure for designs utilizing advanced low-power and test techniques, boosting designers’ productivity and IC performance.

Topographical technology allows designers to accurately estimate a chip’s power consumption during synthesis and address any power issues early in the design cycle. Moreover, topographical technology supports new test compression technology in Design Compiler 2007 to achieve high test quality while reducing test time and test data volume by more than 100x. This alleviates potential wire-routing congestion later during routing due to test implementation.

Topographical technology also delivers tight correlation between performance results seen during synthesis and what is achieved after layout. This eliminates the need for time-consuming iterations between RTL synthesis and physical layout to achieve design closure.

Those interested to know more can log on to the company pages via this blog posting.

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Categories: EDA, FPGAs, GateRocket Tags: ,
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